2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Jesse Barnes <jbarnes@virtuousgeek.org>
26 * New plane/sprite handling.
28 * The older chips had a separate interface for programming plane related
29 * registers; newer ones are much simpler and we can use the new DRM plane
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_fourcc.h>
35 #include <drm/drm_rect.h>
36 #include <drm/drm_atomic.h>
37 #include <drm/drm_plane_helper.h>
38 #include "intel_drv.h"
39 #include "intel_frontbuffer.h"
40 #include <drm/i915_drm.h>
44 format_is_yuv(uint32_t format)
57 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
61 if (!adjusted_mode->crtc_htotal)
64 return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock,
65 1000 * adjusted_mode->crtc_htotal);
68 #define VBLANK_EVASION_TIME_US 100
71 * intel_pipe_update_start() - start update of a set of display registers
72 * @crtc: the crtc of which the registers are going to be updated
73 * @start_vbl_count: vblank counter return pointer used for error checking
75 * Mark the start of an update to pipe registers that should be updated
76 * atomically regarding vblank. If the next vblank will happens within
77 * the next 100 us, this function waits until the vblank passes.
79 * After a successful call to this function, interrupts will be disabled
80 * until a subsequent call to intel_pipe_update_end(). That is done to
81 * avoid random delays. The value written to @start_vbl_count should be
82 * supplied to intel_pipe_update_end() for error checking.
84 void intel_pipe_update_start(struct intel_crtc *crtc)
86 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
87 long timeout = msecs_to_jiffies_timeout(1);
88 int scanline, min, max, vblank_start;
89 wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
92 vblank_start = adjusted_mode->crtc_vblank_start;
93 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
94 vblank_start = DIV_ROUND_UP(vblank_start, 2);
96 /* FIXME needs to be calibrated sensibly */
97 min = vblank_start - intel_usecs_to_scanlines(adjusted_mode,
98 VBLANK_EVASION_TIME_US);
99 max = vblank_start - 1;
103 if (min <= 0 || max <= 0)
106 if (WARN_ON(drm_crtc_vblank_get(&crtc->base)))
109 crtc->debug.min_vbl = min;
110 crtc->debug.max_vbl = max;
111 trace_i915_pipe_update_start(crtc);
115 * prepare_to_wait() has a memory barrier, which guarantees
116 * other CPUs can see the task state update by the time we
119 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
121 scanline = intel_get_crtc_scanline(crtc);
122 if (scanline < min || scanline > max)
126 DRM_ERROR("Potential atomic update failure on pipe %c\n",
127 pipe_name(crtc->pipe));
133 timeout = schedule_timeout(timeout);
138 finish_wait(wq, &wait);
140 drm_crtc_vblank_put(&crtc->base);
142 crtc->debug.scanline_start = scanline;
143 crtc->debug.start_vbl_time = ktime_get();
144 crtc->debug.start_vbl_count = intel_crtc_get_vblank_counter(crtc);
146 trace_i915_pipe_update_vblank_evaded(crtc);
150 * intel_pipe_update_end() - end update of a set of display registers
151 * @crtc: the crtc of which the registers were updated
152 * @start_vbl_count: start vblank counter (used for error checking)
154 * Mark the end of an update started with intel_pipe_update_start(). This
155 * re-enables interrupts and verifies the update was actually completed
156 * before a vblank using the value of @start_vbl_count.
158 void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work)
160 enum pipe pipe = crtc->pipe;
161 int scanline_end = intel_get_crtc_scanline(crtc);
162 u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);
163 ktime_t end_vbl_time = ktime_get();
164 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
167 work->flip_queued_vblank = end_vbl_count;
168 smp_mb__before_atomic();
169 atomic_set(&work->pending, 1);
172 trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end);
174 /* We're still in the vblank-evade critical section, this can't race.
175 * Would be slightly nice to just grab the vblank count and arm the
176 * event outside of the critical section - the spinlock might spin for a
178 if (crtc->base.state->event) {
179 WARN_ON(drm_crtc_vblank_get(&crtc->base) != 0);
181 spin_lock(&crtc->base.dev->event_lock);
182 drm_crtc_arm_vblank_event(&crtc->base, crtc->base.state->event);
183 spin_unlock(&crtc->base.dev->event_lock);
185 crtc->base.state->event = NULL;
190 if (intel_vgpu_active(dev_priv))
193 if (crtc->debug.start_vbl_count &&
194 crtc->debug.start_vbl_count != end_vbl_count) {
195 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n",
196 pipe_name(pipe), crtc->debug.start_vbl_count,
198 ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
199 crtc->debug.min_vbl, crtc->debug.max_vbl,
200 crtc->debug.scanline_start, scanline_end);
202 #ifdef CONFIG_DRM_I915_DEBUG_VBLANK_EVADE
203 else if (ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time) >
204 VBLANK_EVASION_TIME_US)
205 DRM_WARN("Atomic update on pipe (%c) took %lld us, max time under evasion is %u us\n",
207 ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
208 VBLANK_EVASION_TIME_US);
213 skl_update_plane(struct drm_plane *drm_plane,
214 const struct intel_crtc_state *crtc_state,
215 const struct intel_plane_state *plane_state)
217 struct drm_device *dev = drm_plane->dev;
218 struct drm_i915_private *dev_priv = to_i915(dev);
219 struct intel_plane *intel_plane = to_intel_plane(drm_plane);
220 struct drm_framebuffer *fb = plane_state->base.fb;
221 enum plane_id plane_id = intel_plane->id;
222 enum pipe pipe = intel_plane->pipe;
223 u32 plane_ctl = plane_state->ctl;
224 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
225 u32 surf_addr = plane_state->main.offset;
226 unsigned int rotation = plane_state->base.rotation;
227 u32 stride = skl_plane_stride(fb, 0, rotation);
228 int crtc_x = plane_state->base.dst.x1;
229 int crtc_y = plane_state->base.dst.y1;
230 uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
231 uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
232 uint32_t x = plane_state->main.x;
233 uint32_t y = plane_state->main.y;
234 uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
235 uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
236 unsigned long irqflags;
238 /* Sizes are 0 based */
244 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
246 if (IS_GEMINILAKE(dev_priv)) {
247 I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
248 PLANE_COLOR_PIPE_GAMMA_ENABLE |
249 PLANE_COLOR_PIPE_CSC_ENABLE |
250 PLANE_COLOR_PLANE_GAMMA_DISABLE);
254 I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
255 I915_WRITE_FW(PLANE_KEYMAX(pipe, plane_id), key->max_value);
256 I915_WRITE_FW(PLANE_KEYMSK(pipe, plane_id), key->channel_mask);
259 I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (y << 16) | x);
260 I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
261 I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
263 /* program plane scaler */
264 if (plane_state->scaler_id >= 0) {
265 int scaler_id = plane_state->scaler_id;
266 const struct intel_scaler *scaler;
268 scaler = &crtc_state->scaler_state.scalers[scaler_id];
270 I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id),
271 PS_SCALER_EN | PS_PLANE_SEL(plane_id) | scaler->mode);
272 I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
273 I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);
274 I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id),
275 ((crtc_w + 1) << 16)|(crtc_h + 1));
277 I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0);
279 I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x);
282 I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
283 I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
284 intel_plane_ggtt_offset(plane_state) + surf_addr);
285 POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
287 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
291 skl_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
293 struct drm_device *dev = dplane->dev;
294 struct drm_i915_private *dev_priv = to_i915(dev);
295 struct intel_plane *intel_plane = to_intel_plane(dplane);
296 enum plane_id plane_id = intel_plane->id;
297 enum pipe pipe = intel_plane->pipe;
298 unsigned long irqflags;
300 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
302 I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
304 I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);
305 POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
307 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
311 chv_update_csc(struct intel_plane *intel_plane, uint32_t format)
313 struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
314 enum plane_id plane_id = intel_plane->id;
316 /* Seems RGB data bypasses the CSC always */
317 if (!format_is_yuv(format))
321 * BT.601 limited range YCbCr -> full range RGB
323 * |r| | 6537 4769 0| |cr |
324 * |g| = |-3330 4769 -1605| x |y-64|
325 * |b| | 0 4769 8263| |cb |
327 * Cb and Cr apparently come in as signed already, so no
328 * need for any offset. For Y we need to remove the offset.
330 I915_WRITE_FW(SPCSCYGOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(-64));
331 I915_WRITE_FW(SPCSCCBOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
332 I915_WRITE_FW(SPCSCCROFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
334 I915_WRITE_FW(SPCSCC01(plane_id), SPCSC_C1(4769) | SPCSC_C0(6537));
335 I915_WRITE_FW(SPCSCC23(plane_id), SPCSC_C1(-3330) | SPCSC_C0(0));
336 I915_WRITE_FW(SPCSCC45(plane_id), SPCSC_C1(-1605) | SPCSC_C0(4769));
337 I915_WRITE_FW(SPCSCC67(plane_id), SPCSC_C1(4769) | SPCSC_C0(0));
338 I915_WRITE_FW(SPCSCC8(plane_id), SPCSC_C0(8263));
340 I915_WRITE_FW(SPCSCYGICLAMP(plane_id), SPCSC_IMAX(940) | SPCSC_IMIN(64));
341 I915_WRITE_FW(SPCSCCBICLAMP(plane_id), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
342 I915_WRITE_FW(SPCSCCRICLAMP(plane_id), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
344 I915_WRITE_FW(SPCSCYGOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
345 I915_WRITE_FW(SPCSCCBOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
346 I915_WRITE_FW(SPCSCCROCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
349 static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,
350 const struct intel_plane_state *plane_state)
352 const struct drm_framebuffer *fb = plane_state->base.fb;
353 unsigned int rotation = plane_state->base.rotation;
354 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
357 sprctl = SP_ENABLE | SP_GAMMA_ENABLE;
359 switch (fb->format->format) {
360 case DRM_FORMAT_YUYV:
361 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
363 case DRM_FORMAT_YVYU:
364 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
366 case DRM_FORMAT_UYVY:
367 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
369 case DRM_FORMAT_VYUY:
370 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
372 case DRM_FORMAT_RGB565:
373 sprctl |= SP_FORMAT_BGR565;
375 case DRM_FORMAT_XRGB8888:
376 sprctl |= SP_FORMAT_BGRX8888;
378 case DRM_FORMAT_ARGB8888:
379 sprctl |= SP_FORMAT_BGRA8888;
381 case DRM_FORMAT_XBGR2101010:
382 sprctl |= SP_FORMAT_RGBX1010102;
384 case DRM_FORMAT_ABGR2101010:
385 sprctl |= SP_FORMAT_RGBA1010102;
387 case DRM_FORMAT_XBGR8888:
388 sprctl |= SP_FORMAT_RGBX8888;
390 case DRM_FORMAT_ABGR8888:
391 sprctl |= SP_FORMAT_RGBA8888;
394 MISSING_CASE(fb->format->format);
398 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
401 if (rotation & DRM_ROTATE_180)
402 sprctl |= SP_ROTATE_180;
404 if (rotation & DRM_REFLECT_X)
407 if (key->flags & I915_SET_COLORKEY_SOURCE)
408 sprctl |= SP_SOURCE_KEY;
414 vlv_update_plane(struct drm_plane *dplane,
415 const struct intel_crtc_state *crtc_state,
416 const struct intel_plane_state *plane_state)
418 struct drm_device *dev = dplane->dev;
419 struct drm_i915_private *dev_priv = to_i915(dev);
420 struct intel_plane *intel_plane = to_intel_plane(dplane);
421 struct drm_framebuffer *fb = plane_state->base.fb;
422 enum pipe pipe = intel_plane->pipe;
423 enum plane_id plane_id = intel_plane->id;
424 u32 sprctl = plane_state->ctl;
425 u32 sprsurf_offset = plane_state->main.offset;
427 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
428 int crtc_x = plane_state->base.dst.x1;
429 int crtc_y = plane_state->base.dst.y1;
430 uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
431 uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
432 uint32_t x = plane_state->main.x;
433 uint32_t y = plane_state->main.y;
434 unsigned long irqflags;
436 /* Sizes are 0 based */
440 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
442 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
444 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B)
445 chv_update_csc(intel_plane, fb->format->format);
448 I915_WRITE_FW(SPKEYMINVAL(pipe, plane_id), key->min_value);
449 I915_WRITE_FW(SPKEYMAXVAL(pipe, plane_id), key->max_value);
450 I915_WRITE_FW(SPKEYMSK(pipe, plane_id), key->channel_mask);
452 I915_WRITE_FW(SPSTRIDE(pipe, plane_id), fb->pitches[0]);
453 I915_WRITE_FW(SPPOS(pipe, plane_id), (crtc_y << 16) | crtc_x);
455 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
456 I915_WRITE_FW(SPTILEOFF(pipe, plane_id), (y << 16) | x);
458 I915_WRITE_FW(SPLINOFF(pipe, plane_id), linear_offset);
460 I915_WRITE_FW(SPCONSTALPHA(pipe, plane_id), 0);
462 I915_WRITE_FW(SPSIZE(pipe, plane_id), (crtc_h << 16) | crtc_w);
463 I915_WRITE_FW(SPCNTR(pipe, plane_id), sprctl);
464 I915_WRITE_FW(SPSURF(pipe, plane_id),
465 intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
466 POSTING_READ_FW(SPSURF(pipe, plane_id));
468 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
472 vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
474 struct drm_device *dev = dplane->dev;
475 struct drm_i915_private *dev_priv = to_i915(dev);
476 struct intel_plane *intel_plane = to_intel_plane(dplane);
477 enum pipe pipe = intel_plane->pipe;
478 enum plane_id plane_id = intel_plane->id;
479 unsigned long irqflags;
481 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
483 I915_WRITE_FW(SPCNTR(pipe, plane_id), 0);
485 I915_WRITE_FW(SPSURF(pipe, plane_id), 0);
486 POSTING_READ_FW(SPSURF(pipe, plane_id));
488 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
491 static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state,
492 const struct intel_plane_state *plane_state)
494 struct drm_i915_private *dev_priv =
495 to_i915(plane_state->base.plane->dev);
496 const struct drm_framebuffer *fb = plane_state->base.fb;
497 unsigned int rotation = plane_state->base.rotation;
498 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
501 sprctl = SPRITE_ENABLE | SPRITE_GAMMA_ENABLE;
503 if (IS_IVYBRIDGE(dev_priv))
504 sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
506 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
507 sprctl |= SPRITE_PIPE_CSC_ENABLE;
509 switch (fb->format->format) {
510 case DRM_FORMAT_XBGR8888:
511 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
513 case DRM_FORMAT_XRGB8888:
514 sprctl |= SPRITE_FORMAT_RGBX888;
516 case DRM_FORMAT_YUYV:
517 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
519 case DRM_FORMAT_YVYU:
520 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
522 case DRM_FORMAT_UYVY:
523 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
525 case DRM_FORMAT_VYUY:
526 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
529 MISSING_CASE(fb->format->format);
533 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
534 sprctl |= SPRITE_TILED;
536 if (rotation & DRM_ROTATE_180)
537 sprctl |= SPRITE_ROTATE_180;
539 if (key->flags & I915_SET_COLORKEY_DESTINATION)
540 sprctl |= SPRITE_DEST_KEY;
541 else if (key->flags & I915_SET_COLORKEY_SOURCE)
542 sprctl |= SPRITE_SOURCE_KEY;
548 ivb_update_plane(struct drm_plane *plane,
549 const struct intel_crtc_state *crtc_state,
550 const struct intel_plane_state *plane_state)
552 struct drm_device *dev = plane->dev;
553 struct drm_i915_private *dev_priv = to_i915(dev);
554 struct intel_plane *intel_plane = to_intel_plane(plane);
555 struct drm_framebuffer *fb = plane_state->base.fb;
556 enum pipe pipe = intel_plane->pipe;
557 u32 sprctl = plane_state->ctl, sprscale = 0;
558 u32 sprsurf_offset = plane_state->main.offset;
560 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
561 int crtc_x = plane_state->base.dst.x1;
562 int crtc_y = plane_state->base.dst.y1;
563 uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
564 uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
565 uint32_t x = plane_state->main.x;
566 uint32_t y = plane_state->main.y;
567 uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
568 uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
569 unsigned long irqflags;
571 /* Sizes are 0 based */
577 if (crtc_w != src_w || crtc_h != src_h)
578 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
580 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
582 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
585 I915_WRITE_FW(SPRKEYVAL(pipe), key->min_value);
586 I915_WRITE_FW(SPRKEYMAX(pipe), key->max_value);
587 I915_WRITE_FW(SPRKEYMSK(pipe), key->channel_mask);
590 I915_WRITE_FW(SPRSTRIDE(pipe), fb->pitches[0]);
591 I915_WRITE_FW(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
593 /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
595 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
596 I915_WRITE_FW(SPROFFSET(pipe), (y << 16) | x);
597 else if (fb->modifier == I915_FORMAT_MOD_X_TILED)
598 I915_WRITE_FW(SPRTILEOFF(pipe), (y << 16) | x);
600 I915_WRITE_FW(SPRLINOFF(pipe), linear_offset);
602 I915_WRITE_FW(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
603 if (intel_plane->can_scale)
604 I915_WRITE_FW(SPRSCALE(pipe), sprscale);
605 I915_WRITE_FW(SPRCTL(pipe), sprctl);
606 I915_WRITE_FW(SPRSURF(pipe),
607 intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
608 POSTING_READ_FW(SPRSURF(pipe));
610 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
614 ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
616 struct drm_device *dev = plane->dev;
617 struct drm_i915_private *dev_priv = to_i915(dev);
618 struct intel_plane *intel_plane = to_intel_plane(plane);
619 int pipe = intel_plane->pipe;
620 unsigned long irqflags;
622 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
624 I915_WRITE_FW(SPRCTL(pipe), 0);
625 /* Can't leave the scaler enabled... */
626 if (intel_plane->can_scale)
627 I915_WRITE_FW(SPRSCALE(pipe), 0);
629 I915_WRITE_FW(SPRSURF(pipe), 0);
630 POSTING_READ_FW(SPRSURF(pipe));
632 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
635 static u32 ilk_sprite_ctl(const struct intel_crtc_state *crtc_state,
636 const struct intel_plane_state *plane_state)
638 struct drm_i915_private *dev_priv =
639 to_i915(plane_state->base.plane->dev);
640 const struct drm_framebuffer *fb = plane_state->base.fb;
641 unsigned int rotation = plane_state->base.rotation;
642 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
645 dvscntr = DVS_ENABLE | DVS_GAMMA_ENABLE;
647 if (IS_GEN6(dev_priv))
648 dvscntr |= DVS_TRICKLE_FEED_DISABLE;
650 switch (fb->format->format) {
651 case DRM_FORMAT_XBGR8888:
652 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
654 case DRM_FORMAT_XRGB8888:
655 dvscntr |= DVS_FORMAT_RGBX888;
657 case DRM_FORMAT_YUYV:
658 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
660 case DRM_FORMAT_YVYU:
661 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
663 case DRM_FORMAT_UYVY:
664 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
666 case DRM_FORMAT_VYUY:
667 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
670 MISSING_CASE(fb->format->format);
674 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
675 dvscntr |= DVS_TILED;
677 if (rotation & DRM_ROTATE_180)
678 dvscntr |= DVS_ROTATE_180;
680 if (key->flags & I915_SET_COLORKEY_DESTINATION)
681 dvscntr |= DVS_DEST_KEY;
682 else if (key->flags & I915_SET_COLORKEY_SOURCE)
683 dvscntr |= DVS_SOURCE_KEY;
689 ilk_update_plane(struct drm_plane *plane,
690 const struct intel_crtc_state *crtc_state,
691 const struct intel_plane_state *plane_state)
693 struct drm_device *dev = plane->dev;
694 struct drm_i915_private *dev_priv = to_i915(dev);
695 struct intel_plane *intel_plane = to_intel_plane(plane);
696 struct drm_framebuffer *fb = plane_state->base.fb;
697 int pipe = intel_plane->pipe;
698 u32 dvscntr = plane_state->ctl, dvsscale = 0;
699 u32 dvssurf_offset = plane_state->main.offset;
701 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
702 int crtc_x = plane_state->base.dst.x1;
703 int crtc_y = plane_state->base.dst.y1;
704 uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
705 uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
706 uint32_t x = plane_state->main.x;
707 uint32_t y = plane_state->main.y;
708 uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
709 uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
710 unsigned long irqflags;
712 /* Sizes are 0 based */
718 if (crtc_w != src_w || crtc_h != src_h)
719 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
721 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
723 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
726 I915_WRITE_FW(DVSKEYVAL(pipe), key->min_value);
727 I915_WRITE_FW(DVSKEYMAX(pipe), key->max_value);
728 I915_WRITE_FW(DVSKEYMSK(pipe), key->channel_mask);
731 I915_WRITE_FW(DVSSTRIDE(pipe), fb->pitches[0]);
732 I915_WRITE_FW(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
734 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
735 I915_WRITE_FW(DVSTILEOFF(pipe), (y << 16) | x);
737 I915_WRITE_FW(DVSLINOFF(pipe), linear_offset);
739 I915_WRITE_FW(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
740 I915_WRITE_FW(DVSSCALE(pipe), dvsscale);
741 I915_WRITE_FW(DVSCNTR(pipe), dvscntr);
742 I915_WRITE_FW(DVSSURF(pipe),
743 intel_plane_ggtt_offset(plane_state) + dvssurf_offset);
744 POSTING_READ_FW(DVSSURF(pipe));
746 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
750 ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
752 struct drm_device *dev = plane->dev;
753 struct drm_i915_private *dev_priv = to_i915(dev);
754 struct intel_plane *intel_plane = to_intel_plane(plane);
755 int pipe = intel_plane->pipe;
756 unsigned long irqflags;
758 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
760 I915_WRITE_FW(DVSCNTR(pipe), 0);
761 /* Disable the scaler */
762 I915_WRITE_FW(DVSSCALE(pipe), 0);
764 I915_WRITE_FW(DVSSURF(pipe), 0);
765 POSTING_READ_FW(DVSSURF(pipe));
767 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
771 intel_check_sprite_plane(struct drm_plane *plane,
772 struct intel_crtc_state *crtc_state,
773 struct intel_plane_state *state)
775 struct drm_i915_private *dev_priv = to_i915(plane->dev);
776 struct drm_crtc *crtc = state->base.crtc;
777 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
778 struct intel_plane *intel_plane = to_intel_plane(plane);
779 struct drm_framebuffer *fb = state->base.fb;
781 unsigned int crtc_w, crtc_h;
782 uint32_t src_x, src_y, src_w, src_h;
783 struct drm_rect *src = &state->base.src;
784 struct drm_rect *dst = &state->base.dst;
785 const struct drm_rect *clip = &state->clip;
787 int max_scale, min_scale;
791 *src = drm_plane_state_src(&state->base);
792 *dst = drm_plane_state_dest(&state->base);
795 state->base.visible = false;
799 /* Don't modify another pipe's plane */
800 if (intel_plane->pipe != intel_crtc->pipe) {
801 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
805 /* FIXME check all gen limits */
806 if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) {
807 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
811 /* setup can_scale, min_scale, max_scale */
812 if (INTEL_GEN(dev_priv) >= 9) {
813 /* use scaler when colorkey is not required */
814 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
817 max_scale = skl_max_scale(intel_crtc, crtc_state);
820 min_scale = DRM_PLANE_HELPER_NO_SCALING;
821 max_scale = DRM_PLANE_HELPER_NO_SCALING;
824 can_scale = intel_plane->can_scale;
825 max_scale = intel_plane->max_downscale << 16;
826 min_scale = intel_plane->can_scale ? 1 : (1 << 16);
830 * FIXME the following code does a bunch of fuzzy adjustments to the
831 * coordinates and sizes. We probably need some way to decide whether
832 * more strict checking should be done instead.
834 drm_rect_rotate(src, fb->width << 16, fb->height << 16,
835 state->base.rotation);
837 hscale = drm_rect_calc_hscale_relaxed(src, dst, min_scale, max_scale);
840 vscale = drm_rect_calc_vscale_relaxed(src, dst, min_scale, max_scale);
843 state->base.visible = drm_rect_clip_scaled(src, dst, clip, hscale, vscale);
847 crtc_w = drm_rect_width(dst);
848 crtc_h = drm_rect_height(dst);
850 if (state->base.visible) {
851 /* check again in case clipping clamped the results */
852 hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
854 DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n");
855 drm_rect_debug_print("src: ", src, true);
856 drm_rect_debug_print("dst: ", dst, false);
861 vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
863 DRM_DEBUG_KMS("Vertical scaling factor out of limits\n");
864 drm_rect_debug_print("src: ", src, true);
865 drm_rect_debug_print("dst: ", dst, false);
870 /* Make the source viewport size an exact multiple of the scaling factors. */
871 drm_rect_adjust_size(src,
872 drm_rect_width(dst) * hscale - drm_rect_width(src),
873 drm_rect_height(dst) * vscale - drm_rect_height(src));
875 drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16,
876 state->base.rotation);
878 /* sanity check to make sure the src viewport wasn't enlarged */
879 WARN_ON(src->x1 < (int) state->base.src_x ||
880 src->y1 < (int) state->base.src_y ||
881 src->x2 > (int) state->base.src_x + state->base.src_w ||
882 src->y2 > (int) state->base.src_y + state->base.src_h);
885 * Hardware doesn't handle subpixel coordinates.
886 * Adjust to (macro)pixel boundary, but be careful not to
887 * increase the source viewport size, because that could
888 * push the downscaling factor out of bounds.
890 src_x = src->x1 >> 16;
891 src_w = drm_rect_width(src) >> 16;
892 src_y = src->y1 >> 16;
893 src_h = drm_rect_height(src) >> 16;
895 if (format_is_yuv(fb->format->format)) {
900 * Must keep src and dst the
901 * same if we can't scale.
907 state->base.visible = false;
911 /* Check size restrictions when scaling */
912 if (state->base.visible && (src_w != crtc_w || src_h != crtc_h)) {
913 unsigned int width_bytes;
914 int cpp = fb->format->cpp[0];
918 /* FIXME interlacing min height is 6 */
920 if (crtc_w < 3 || crtc_h < 3)
921 state->base.visible = false;
923 if (src_w < 3 || src_h < 3)
924 state->base.visible = false;
926 width_bytes = ((src_x * cpp) & 63) + src_w * cpp;
928 if (INTEL_GEN(dev_priv) < 9 && (src_w > 2048 || src_h > 2048 ||
929 width_bytes > 4096 || fb->pitches[0] > 4096)) {
930 DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
935 if (state->base.visible) {
936 src->x1 = src_x << 16;
937 src->x2 = (src_x + src_w) << 16;
938 src->y1 = src_y << 16;
939 src->y2 = (src_y + src_h) << 16;
943 dst->x2 = crtc_x + crtc_w;
945 dst->y2 = crtc_y + crtc_h;
947 if (INTEL_GEN(dev_priv) >= 9) {
948 ret = skl_check_plane_surface(state);
952 state->ctl = skl_plane_ctl(crtc_state, state);
953 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
954 ret = i9xx_check_plane_surface(state);
958 state->ctl = vlv_sprite_ctl(crtc_state, state);
959 } else if (INTEL_GEN(dev_priv) >= 7) {
960 ret = i9xx_check_plane_surface(state);
964 state->ctl = ivb_sprite_ctl(crtc_state, state);
966 ret = i9xx_check_plane_surface(state);
970 state->ctl = ilk_sprite_ctl(crtc_state, state);
976 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
977 struct drm_file *file_priv)
979 struct drm_i915_private *dev_priv = to_i915(dev);
980 struct drm_intel_sprite_colorkey *set = data;
981 struct drm_plane *plane;
982 struct drm_plane_state *plane_state;
983 struct drm_atomic_state *state;
984 struct drm_modeset_acquire_ctx ctx;
987 /* Make sure we don't try to enable both src & dest simultaneously */
988 if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
991 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
992 set->flags & I915_SET_COLORKEY_DESTINATION)
995 plane = drm_plane_find(dev, set->plane_id);
996 if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY)
999 drm_modeset_acquire_init(&ctx, 0);
1001 state = drm_atomic_state_alloc(plane->dev);
1006 state->acquire_ctx = &ctx;
1009 plane_state = drm_atomic_get_plane_state(state, plane);
1010 ret = PTR_ERR_OR_ZERO(plane_state);
1012 to_intel_plane_state(plane_state)->ckey = *set;
1013 ret = drm_atomic_commit(state);
1016 if (ret != -EDEADLK)
1019 drm_atomic_state_clear(state);
1020 drm_modeset_backoff(&ctx);
1023 drm_atomic_state_put(state);
1025 drm_modeset_drop_locks(&ctx);
1026 drm_modeset_acquire_fini(&ctx);
1030 static const uint32_t ilk_plane_formats[] = {
1031 DRM_FORMAT_XRGB8888,
1038 static const uint32_t snb_plane_formats[] = {
1039 DRM_FORMAT_XBGR8888,
1040 DRM_FORMAT_XRGB8888,
1047 static const uint32_t vlv_plane_formats[] = {
1049 DRM_FORMAT_ABGR8888,
1050 DRM_FORMAT_ARGB8888,
1051 DRM_FORMAT_XBGR8888,
1052 DRM_FORMAT_XRGB8888,
1053 DRM_FORMAT_XBGR2101010,
1054 DRM_FORMAT_ABGR2101010,
1061 static uint32_t skl_plane_formats[] = {
1063 DRM_FORMAT_ABGR8888,
1064 DRM_FORMAT_ARGB8888,
1065 DRM_FORMAT_XBGR8888,
1066 DRM_FORMAT_XRGB8888,
1073 struct intel_plane *
1074 intel_sprite_plane_create(struct drm_i915_private *dev_priv,
1075 enum pipe pipe, int plane)
1077 struct intel_plane *intel_plane = NULL;
1078 struct intel_plane_state *state = NULL;
1079 unsigned long possible_crtcs;
1080 const uint32_t *plane_formats;
1081 unsigned int supported_rotations;
1082 int num_plane_formats;
1085 intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL);
1091 state = intel_create_plane_state(&intel_plane->base);
1096 intel_plane->base.state = &state->base;
1098 if (INTEL_GEN(dev_priv) >= 9) {
1099 intel_plane->can_scale = true;
1100 state->scaler_id = -1;
1102 intel_plane->update_plane = skl_update_plane;
1103 intel_plane->disable_plane = skl_disable_plane;
1105 plane_formats = skl_plane_formats;
1106 num_plane_formats = ARRAY_SIZE(skl_plane_formats);
1107 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1108 intel_plane->can_scale = false;
1109 intel_plane->max_downscale = 1;
1111 intel_plane->update_plane = vlv_update_plane;
1112 intel_plane->disable_plane = vlv_disable_plane;
1114 plane_formats = vlv_plane_formats;
1115 num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
1116 } else if (INTEL_GEN(dev_priv) >= 7) {
1117 if (IS_IVYBRIDGE(dev_priv)) {
1118 intel_plane->can_scale = true;
1119 intel_plane->max_downscale = 2;
1121 intel_plane->can_scale = false;
1122 intel_plane->max_downscale = 1;
1125 intel_plane->update_plane = ivb_update_plane;
1126 intel_plane->disable_plane = ivb_disable_plane;
1128 plane_formats = snb_plane_formats;
1129 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1131 intel_plane->can_scale = true;
1132 intel_plane->max_downscale = 16;
1134 intel_plane->update_plane = ilk_update_plane;
1135 intel_plane->disable_plane = ilk_disable_plane;
1137 if (IS_GEN6(dev_priv)) {
1138 plane_formats = snb_plane_formats;
1139 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1141 plane_formats = ilk_plane_formats;
1142 num_plane_formats = ARRAY_SIZE(ilk_plane_formats);
1146 if (INTEL_GEN(dev_priv) >= 9) {
1147 supported_rotations =
1148 DRM_ROTATE_0 | DRM_ROTATE_90 |
1149 DRM_ROTATE_180 | DRM_ROTATE_270;
1150 } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
1151 supported_rotations =
1152 DRM_ROTATE_0 | DRM_ROTATE_180 |
1155 supported_rotations =
1156 DRM_ROTATE_0 | DRM_ROTATE_180;
1159 intel_plane->pipe = pipe;
1160 intel_plane->plane = plane;
1161 intel_plane->id = PLANE_SPRITE0 + plane;
1162 intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER_SPRITE(pipe, plane);
1163 intel_plane->check_plane = intel_check_sprite_plane;
1165 possible_crtcs = (1 << pipe);
1167 if (INTEL_GEN(dev_priv) >= 9)
1168 ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base,
1169 possible_crtcs, &intel_plane_funcs,
1170 plane_formats, num_plane_formats,
1171 DRM_PLANE_TYPE_OVERLAY,
1172 "plane %d%c", plane + 2, pipe_name(pipe));
1174 ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base,
1175 possible_crtcs, &intel_plane_funcs,
1176 plane_formats, num_plane_formats,
1177 DRM_PLANE_TYPE_OVERLAY,
1178 "sprite %c", sprite_name(pipe, plane));
1182 drm_plane_create_rotation_property(&intel_plane->base,
1184 supported_rotations);
1186 drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs);
1194 return ERR_PTR(ret);