drivers/gpu/drm/i915/intel_sprite.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *   Jesse Barnes <jbarnes@virtuousgeek.org>
  25  *
  26  * New plane/sprite handling.
  27  *
  28  * The older chips had a separate interface for programming plane related
  29  * registers; newer ones are much simpler and we can use the new DRM plane
  30  * support.
  31  */
  32 #include <drm/drmP.h>
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_fourcc.h>
  35 #include <drm/drm_rect.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39
  40 static void
  41 vlv_update_plane(struct drm_plane *dplane, struct drm_framebuffer *fb,
  42                  struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
  43                  unsigned int crtc_w, unsigned int crtc_h,
  44                  uint32_t x, uint32_t y,
  45                  uint32_t src_w, uint32_t src_h)
  46 {
  47         struct drm_device *dev = dplane->dev;
  48         struct drm_i915_private *dev_priv = dev->dev_private;
  49         struct intel_plane *intel_plane = to_intel_plane(dplane);
  50         int pipe = intel_plane->pipe;
  51         int plane = intel_plane->plane;
  52         u32 sprctl;
  53         unsigned long sprsurf_offset, linear_offset;
  54         int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
  55
  56         sprctl = I915_READ(SPCNTR(pipe, plane));
  57
  58         /* Mask out pixel format bits in case we change it */
  59         sprctl &= ~SP_PIXFORMAT_MASK;
  60         sprctl &= ~SP_YUV_BYTE_ORDER_MASK;
  61         sprctl &= ~SP_TILED;
  62
  63         switch (fb->pixel_format) {
  64         case DRM_FORMAT_YUYV:
  65                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
  66                 break;
  67         case DRM_FORMAT_YVYU:
  68                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
  69                 break;
  70         case DRM_FORMAT_UYVY:
  71                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
  72                 break;
  73         case DRM_FORMAT_VYUY:
  74                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
  75                 break;
  76         case DRM_FORMAT_RGB565:
  77                 sprctl |= SP_FORMAT_BGR565;
  78                 break;
  79         case DRM_FORMAT_XRGB8888:
  80                 sprctl |= SP_FORMAT_BGRX8888;
  81                 break;
  82         case DRM_FORMAT_ARGB8888:
  83                 sprctl |= SP_FORMAT_BGRA8888;
  84                 break;
  85         case DRM_FORMAT_XBGR2101010:
  86                 sprctl |= SP_FORMAT_RGBX1010102;
  87                 break;
  88         case DRM_FORMAT_ABGR2101010:
  89                 sprctl |= SP_FORMAT_RGBA1010102;
  90                 break;
  91         case DRM_FORMAT_XBGR8888:
  92                 sprctl |= SP_FORMAT_RGBX8888;
  93                 break;
  94         case DRM_FORMAT_ABGR8888:
  95                 sprctl |= SP_FORMAT_RGBA8888;
  96                 break;
  97         default:
  98                 /*
  99                  * If we get here one of the upper layers failed to filter
 100                  * out the unsupported plane formats
 101                  */
 102                 BUG();
 103                 break;
 104         }
 105
 106         if (obj->tiling_mode != I915_TILING_NONE)
 107                 sprctl |= SP_TILED;
 108
 109         sprctl |= SP_ENABLE;
 110
 111         intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size, true,
 112                                        src_w != crtc_w || src_h != crtc_h);
 113
 114         /* Sizes are 0 based */
 115         src_w--;
 116         src_h--;
 117         crtc_w--;
 118         crtc_h--;
 119
 120         I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
 121         I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);
 122
 123         linear_offset = y * fb->pitches[0] + x * pixel_size;
 124         sprsurf_offset = intel_gen4_compute_page_offset(&x, &y,
 125                                                         obj->tiling_mode,
 126                                                         pixel_size,
 127                                                         fb->pitches[0]);
 128         linear_offset -= sprsurf_offset;
 129
 130         if (obj->tiling_mode != I915_TILING_NONE)
 131                 I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x);
 132         else
 133                 I915_WRITE(SPLINOFF(pipe, plane), linear_offset);
 134
 135         I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w);
 136         I915_WRITE(SPCNTR(pipe, plane), sprctl);
 137         I915_MODIFY_DISPBASE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) +
 138                              sprsurf_offset);
 139         POSTING_READ(SPSURF(pipe, plane));
 140 }
 141
 142 static void
 143 vlv_disable_plane(struct drm_plane *dplane)
 144 {
 145         struct drm_device *dev = dplane->dev;
 146         struct drm_i915_private *dev_priv = dev->dev_private;
 147         struct intel_plane *intel_plane = to_intel_plane(dplane);
 148         int pipe = intel_plane->pipe;
 149         int plane = intel_plane->plane;
 150
 151         I915_WRITE(SPCNTR(pipe, plane), I915_READ(SPCNTR(pipe, plane)) &
 152                    ~SP_ENABLE);
 153         /* Activate double buffered register update */
 154         I915_MODIFY_DISPBASE(SPSURF(pipe, plane), 0);
 155         POSTING_READ(SPSURF(pipe, plane));
 156 }
 157
 158 static int
 159 vlv_update_colorkey(struct drm_plane *dplane,
 160                     struct drm_intel_sprite_colorkey *key)
 161 {
 162         struct drm_device *dev = dplane->dev;
 163         struct drm_i915_private *dev_priv = dev->dev_private;
 164         struct intel_plane *intel_plane = to_intel_plane(dplane);
 165         int pipe = intel_plane->pipe;
 166         int plane = intel_plane->plane;
 167         u32 sprctl;
 168
 169         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 170                 return -EINVAL;
 171
 172         I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value);
 173         I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value);
 174         I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask);
 175
 176         sprctl = I915_READ(SPCNTR(pipe, plane));
 177         sprctl &= ~SP_SOURCE_KEY;
 178         if (key->flags & I915_SET_COLORKEY_SOURCE)
 179                 sprctl |= SP_SOURCE_KEY;
 180         I915_WRITE(SPCNTR(pipe, plane), sprctl);
 181
 182         POSTING_READ(SPKEYMSK(pipe, plane));
 183
 184         return 0;
 185 }
 186
 187 static void
 188 vlv_get_colorkey(struct drm_plane *dplane,
 189                  struct drm_intel_sprite_colorkey *key)
 190 {
 191         struct drm_device *dev = dplane->dev;
 192         struct drm_i915_private *dev_priv = dev->dev_private;
 193         struct intel_plane *intel_plane = to_intel_plane(dplane);
 194         int pipe = intel_plane->pipe;
 195         int plane = intel_plane->plane;
 196         u32 sprctl;
 197
 198         key->min_value = I915_READ(SPKEYMINVAL(pipe, plane));
 199         key->max_value = I915_READ(SPKEYMAXVAL(pipe, plane));
 200         key->channel_mask = I915_READ(SPKEYMSK(pipe, plane));
 201
 202         sprctl = I915_READ(SPCNTR(pipe, plane));
 203         if (sprctl & SP_SOURCE_KEY)
 204                 key->flags = I915_SET_COLORKEY_SOURCE;
 205         else
 206                 key->flags = I915_SET_COLORKEY_NONE;
 207 }
 208
 209 static void
 210 ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,
 211                  struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
 212                  unsigned int crtc_w, unsigned int crtc_h,
 213                  uint32_t x, uint32_t y,
 214                  uint32_t src_w, uint32_t src_h)
 215 {
 216         struct drm_device *dev = plane->dev;
 217         struct drm_i915_private *dev_priv = dev->dev_private;
 218         struct intel_plane *intel_plane = to_intel_plane(plane);
 219         int pipe = intel_plane->pipe;
 220         u32 sprctl, sprscale = 0;
 221         unsigned long sprsurf_offset, linear_offset;
 222         int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
 223         bool scaling_was_enabled = dev_priv->sprite_scaling_enabled;
 224
 225         sprctl = I915_READ(SPRCTL(pipe));
 226
 227         /* Mask out pixel format bits in case we change it */
 228         sprctl &= ~SPRITE_PIXFORMAT_MASK;
 229         sprctl &= ~SPRITE_RGB_ORDER_RGBX;
 230         sprctl &= ~SPRITE_YUV_BYTE_ORDER_MASK;
 231         sprctl &= ~SPRITE_TILED;
 232
 233         switch (fb->pixel_format) {
 234         case DRM_FORMAT_XBGR8888:
 235                 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
 236                 break;
 237         case DRM_FORMAT_XRGB8888:
 238                 sprctl |= SPRITE_FORMAT_RGBX888;
 239                 break;
 240         case DRM_FORMAT_YUYV:
 241                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
 242                 break;
 243         case DRM_FORMAT_YVYU:
 244                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
 245                 break;
 246         case DRM_FORMAT_UYVY:
 247                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
 248                 break;
 249         case DRM_FORMAT_VYUY:
 250                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
 251                 break;
 252         default:
 253                 BUG();
 254         }
 255
 256         if (obj->tiling_mode != I915_TILING_NONE)
 257                 sprctl |= SPRITE_TILED;
 258
 259         /* must disable */
 260         sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
 261         sprctl |= SPRITE_ENABLE;
 262
 263         if (IS_HASWELL(dev))
 264                 sprctl |= SPRITE_PIPE_CSC_ENABLE;
 265
 266         intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size, true,
 267                                        src_w != crtc_w || src_h != crtc_h);
 268
 269         /* Sizes are 0 based */
 270         src_w--;
 271         src_h--;
 272         crtc_w--;
 273         crtc_h--;
 274
 275         /*
 276          * IVB workaround: must disable low power watermarks for at least
 277          * one frame before enabling scaling.  LP watermarks can be re-enabled
 278          * when scaling is disabled.
 279          */
 280         if (crtc_w != src_w || crtc_h != src_h) {
 281                 dev_priv->sprite_scaling_enabled |= 1 << pipe;
 282
 283                 if (!scaling_was_enabled) {
 284                         intel_update_watermarks(dev);
 285                         intel_wait_for_vblank(dev, pipe);
 286                 }
 287                 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
 288         } else
 289                 dev_priv->sprite_scaling_enabled &= ~(1 << pipe);
 290
 291         I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);
 292         I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
 293
 294         linear_offset = y * fb->pitches[0] + x * pixel_size;
 295         sprsurf_offset =
 296                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
 297                                                pixel_size, fb->pitches[0]);
 298         linear_offset -= sprsurf_offset;
 299
 300         /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
 301          * register */
 302         if (IS_HASWELL(dev))
 303                 I915_WRITE(SPROFFSET(pipe), (y << 16) | x);
 304         else if (obj->tiling_mode != I915_TILING_NONE)
 305                 I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
 306         else
 307                 I915_WRITE(SPRLINOFF(pipe), linear_offset);
 308
 309         I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
 310         if (intel_plane->can_scale)
 311                 I915_WRITE(SPRSCALE(pipe), sprscale);
 312         I915_WRITE(SPRCTL(pipe), sprctl);
 313         I915_MODIFY_DISPBASE(SPRSURF(pipe),
 314                              i915_gem_obj_ggtt_offset(obj) + sprsurf_offset);
 315         POSTING_READ(SPRSURF(pipe));
 316
 317         /* potentially re-enable LP watermarks */
 318         if (scaling_was_enabled && !dev_priv->sprite_scaling_enabled)
 319                 intel_update_watermarks(dev);
 320 }
 321
 322 static void
 323 ivb_disable_plane(struct drm_plane *plane)
 324 {
 325         struct drm_device *dev = plane->dev;
 326         struct drm_i915_private *dev_priv = dev->dev_private;
 327         struct intel_plane *intel_plane = to_intel_plane(plane);
 328         int pipe = intel_plane->pipe;
 329         bool scaling_was_enabled = dev_priv->sprite_scaling_enabled;
 330
 331         I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE);
 332         /* Can't leave the scaler enabled... */
 333         if (intel_plane->can_scale)
 334                 I915_WRITE(SPRSCALE(pipe), 0);
 335         /* Activate double buffered register update */
 336         I915_MODIFY_DISPBASE(SPRSURF(pipe), 0);
 337         POSTING_READ(SPRSURF(pipe));
 338
 339         dev_priv->sprite_scaling_enabled &= ~(1 << pipe);
 340
 341         intel_update_sprite_watermarks(dev, pipe, 0, 0, false, false);
 342
 343         /* potentially re-enable LP watermarks */
 344         if (scaling_was_enabled && !dev_priv->sprite_scaling_enabled)
 345                 intel_update_watermarks(dev);
 346 }
 347
 348 static int
 349 ivb_update_colorkey(struct drm_plane *plane,
 350                     struct drm_intel_sprite_colorkey *key)
 351 {
 352         struct drm_device *dev = plane->dev;
 353         struct drm_i915_private *dev_priv = dev->dev_private;
 354         struct intel_plane *intel_plane;
 355         u32 sprctl;
 356         int ret = 0;
 357
 358         intel_plane = to_intel_plane(plane);
 359
 360         I915_WRITE(SPRKEYVAL(intel_plane->pipe), key->min_value);
 361         I915_WRITE(SPRKEYMAX(intel_plane->pipe), key->max_value);
 362         I915_WRITE(SPRKEYMSK(intel_plane->pipe), key->channel_mask);
 363
 364         sprctl = I915_READ(SPRCTL(intel_plane->pipe));
 365         sprctl &= ~(SPRITE_SOURCE_KEY | SPRITE_DEST_KEY);
 366         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 367                 sprctl |= SPRITE_DEST_KEY;
 368         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 369                 sprctl |= SPRITE_SOURCE_KEY;
 370         I915_WRITE(SPRCTL(intel_plane->pipe), sprctl);
 371
 372         POSTING_READ(SPRKEYMSK(intel_plane->pipe));
 373
 374         return ret;
 375 }
 376
 377 static void
 378 ivb_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key)
 379 {
 380         struct drm_device *dev = plane->dev;
 381         struct drm_i915_private *dev_priv = dev->dev_private;
 382         struct intel_plane *intel_plane;
 383         u32 sprctl;
 384
 385         intel_plane = to_intel_plane(plane);
 386
 387         key->min_value = I915_READ(SPRKEYVAL(intel_plane->pipe));
 388         key->max_value = I915_READ(SPRKEYMAX(intel_plane->pipe));
 389         key->channel_mask = I915_READ(SPRKEYMSK(intel_plane->pipe));
 390         key->flags = 0;
 391
 392         sprctl = I915_READ(SPRCTL(intel_plane->pipe));
 393
 394         if (sprctl & SPRITE_DEST_KEY)
 395                 key->flags = I915_SET_COLORKEY_DESTINATION;
 396         else if (sprctl & SPRITE_SOURCE_KEY)
 397                 key->flags = I915_SET_COLORKEY_SOURCE;
 398         else
 399                 key->flags = I915_SET_COLORKEY_NONE;
 400 }
 401
 402 static void
 403 ilk_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,
 404                  struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
 405                  unsigned int crtc_w, unsigned int crtc_h,
 406                  uint32_t x, uint32_t y,
 407                  uint32_t src_w, uint32_t src_h)
 408 {
 409         struct drm_device *dev = plane->dev;
 410         struct drm_i915_private *dev_priv = dev->dev_private;
 411         struct intel_plane *intel_plane = to_intel_plane(plane);
 412         int pipe = intel_plane->pipe;
 413         unsigned long dvssurf_offset, linear_offset;
 414         u32 dvscntr, dvsscale;
 415         int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
 416
 417         dvscntr = I915_READ(DVSCNTR(pipe));
 418
 419         /* Mask out pixel format bits in case we change it */
 420         dvscntr &= ~DVS_PIXFORMAT_MASK;
 421         dvscntr &= ~DVS_RGB_ORDER_XBGR;
 422         dvscntr &= ~DVS_YUV_BYTE_ORDER_MASK;
 423         dvscntr &= ~DVS_TILED;
 424
 425         switch (fb->pixel_format) {
 426         case DRM_FORMAT_XBGR8888:
 427                 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
 428                 break;
 429         case DRM_FORMAT_XRGB8888:
 430                 dvscntr |= DVS_FORMAT_RGBX888;
 431                 break;
 432         case DRM_FORMAT_YUYV:
 433                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
 434                 break;
 435         case DRM_FORMAT_YVYU:
 436                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
 437                 break;
 438         case DRM_FORMAT_UYVY:
 439                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
 440                 break;
 441         case DRM_FORMAT_VYUY:
 442                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
 443                 break;
 444         default:
 445                 BUG();
 446         }
 447
 448         if (obj->tiling_mode != I915_TILING_NONE)
 449                 dvscntr |= DVS_TILED;
 450
 451         if (IS_GEN6(dev))
 452                 dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */
 453         dvscntr |= DVS_ENABLE;
 454
 455         intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size, true,
 456                                        src_w != crtc_w || src_h != crtc_h);
 457
 458         /* Sizes are 0 based */
 459         src_w--;
 460         src_h--;
 461         crtc_w--;
 462         crtc_h--;
 463
 464         dvsscale = 0;
 465         if (IS_GEN5(dev) || crtc_w != src_w || crtc_h != src_h)
 466                 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
 467
 468         I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);
 469         I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
 470
 471         linear_offset = y * fb->pitches[0] + x * pixel_size;
 472         dvssurf_offset =
 473                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
 474                                                pixel_size, fb->pitches[0]);
 475         linear_offset -= dvssurf_offset;
 476
 477         if (obj->tiling_mode != I915_TILING_NONE)
 478                 I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x);
 479         else
 480                 I915_WRITE(DVSLINOFF(pipe), linear_offset);
 481
 482         I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
 483         I915_WRITE(DVSSCALE(pipe), dvsscale);
 484         I915_WRITE(DVSCNTR(pipe), dvscntr);
 485         I915_MODIFY_DISPBASE(DVSSURF(pipe),
 486                              i915_gem_obj_ggtt_offset(obj) + dvssurf_offset);
 487         POSTING_READ(DVSSURF(pipe));
 488 }
 489
 490 static void
 491 ilk_disable_plane(struct drm_plane *plane)
 492 {
 493         struct drm_device *dev = plane->dev;
 494         struct drm_i915_private *dev_priv = dev->dev_private;
 495         struct intel_plane *intel_plane = to_intel_plane(plane);
 496         int pipe = intel_plane->pipe;
 497
 498         I915_WRITE(DVSCNTR(pipe), I915_READ(DVSCNTR(pipe)) & ~DVS_ENABLE);
 499         /* Disable the scaler */
 500         I915_WRITE(DVSSCALE(pipe), 0);
 501         /* Flush double buffered register updates */
 502         I915_MODIFY_DISPBASE(DVSSURF(pipe), 0);
 503         POSTING_READ(DVSSURF(pipe));
 504 }
 505
 506 static void
 507 intel_enable_primary(struct drm_crtc *crtc)
 508 {
 509         struct drm_device *dev = crtc->dev;
 510         struct drm_i915_private *dev_priv = dev->dev_private;
 511         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 512         int reg = DSPCNTR(intel_crtc->plane);
 513
 514         if (!intel_crtc->primary_disabled)
 515                 return;
 516
 517         intel_crtc->primary_disabled = false;
 518         intel_update_fbc(dev);
 519
 520         I915_WRITE(reg, I915_READ(reg) | DISPLAY_PLANE_ENABLE);
 521 }
 522
 523 static void
 524 intel_disable_primary(struct drm_crtc *crtc)
 525 {
 526         struct drm_device *dev = crtc->dev;
 527         struct drm_i915_private *dev_priv = dev->dev_private;
 528         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 529         int reg = DSPCNTR(intel_crtc->plane);
 530
 531         if (intel_crtc->primary_disabled)
 532                 return;
 533
 534         I915_WRITE(reg, I915_READ(reg) & ~DISPLAY_PLANE_ENABLE);
 535
 536         intel_crtc->primary_disabled = true;
 537         intel_update_fbc(dev);
 538 }
 539
 540 static int
 541 ilk_update_colorkey(struct drm_plane *plane,
 542                     struct drm_intel_sprite_colorkey *key)
 543 {
 544         struct drm_device *dev = plane->dev;
 545         struct drm_i915_private *dev_priv = dev->dev_private;
 546         struct intel_plane *intel_plane;
 547         u32 dvscntr;
 548         int ret = 0;
 549
 550         intel_plane = to_intel_plane(plane);
 551
 552         I915_WRITE(DVSKEYVAL(intel_plane->pipe), key->min_value);
 553         I915_WRITE(DVSKEYMAX(intel_plane->pipe), key->max_value);
 554         I915_WRITE(DVSKEYMSK(intel_plane->pipe), key->channel_mask);
 555
 556         dvscntr = I915_READ(DVSCNTR(intel_plane->pipe));
 557         dvscntr &= ~(DVS_SOURCE_KEY | DVS_DEST_KEY);
 558         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 559                 dvscntr |= DVS_DEST_KEY;
 560         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 561                 dvscntr |= DVS_SOURCE_KEY;
 562         I915_WRITE(DVSCNTR(intel_plane->pipe), dvscntr);
 563
 564         POSTING_READ(DVSKEYMSK(intel_plane->pipe));
 565
 566         return ret;
 567 }
 568
 569 static void
 570 ilk_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key)
 571 {
 572         struct drm_device *dev = plane->dev;
 573         struct drm_i915_private *dev_priv = dev->dev_private;
 574         struct intel_plane *intel_plane;
 575         u32 dvscntr;
 576
 577         intel_plane = to_intel_plane(plane);
 578
 579         key->min_value = I915_READ(DVSKEYVAL(intel_plane->pipe));
 580         key->max_value = I915_READ(DVSKEYMAX(intel_plane->pipe));
 581         key->channel_mask = I915_READ(DVSKEYMSK(intel_plane->pipe));
 582         key->flags = 0;
 583
 584         dvscntr = I915_READ(DVSCNTR(intel_plane->pipe));
 585
 586         if (dvscntr & DVS_DEST_KEY)
 587                 key->flags = I915_SET_COLORKEY_DESTINATION;
 588         else if (dvscntr & DVS_SOURCE_KEY)
 589                 key->flags = I915_SET_COLORKEY_SOURCE;
 590         else
 591                 key->flags = I915_SET_COLORKEY_NONE;
 592 }
 593
 594 static bool
 595 format_is_yuv(uint32_t format)
 596 {
 597         switch (format) {
 598         case DRM_FORMAT_YUYV:
 599         case DRM_FORMAT_UYVY:
 600         case DRM_FORMAT_VYUY:
 601         case DRM_FORMAT_YVYU:
 602                 return true;
 603         default:
 604                 return false;
 605         }
 606 }
 607
 608 static int
 609 intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 610                    struct drm_framebuffer *fb, int crtc_x, int crtc_y,
 611                    unsigned int crtc_w, unsigned int crtc_h,
 612                    uint32_t src_x, uint32_t src_y,
 613                    uint32_t src_w, uint32_t src_h)
 614 {
 615         struct drm_device *dev = plane->dev;
 616         struct drm_i915_private *dev_priv = dev->dev_private;
 617         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 618         struct intel_plane *intel_plane = to_intel_plane(plane);
 619         struct intel_framebuffer *intel_fb;
 620         struct drm_i915_gem_object *obj, *old_obj;
 621         int pipe = intel_plane->pipe;
 622         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 623                                                                       pipe);
 624         int ret = 0;
 625         bool disable_primary = false;
 626         bool visible;
 627         int hscale, vscale;
 628         int max_scale, min_scale;
 629         int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
 630         struct drm_rect src = {
 631                 /* sample coordinates in 16.16 fixed point */
 632                 .x1 = src_x,
 633                 .x2 = src_x + src_w,
 634                 .y1 = src_y,
 635                 .y2 = src_y + src_h,
 636         };
 637         struct drm_rect dst = {
 638                 /* integer pixels */
 639                 .x1 = crtc_x,
 640                 .x2 = crtc_x + crtc_w,
 641                 .y1 = crtc_y,
 642                 .y2 = crtc_y + crtc_h,
 643         };
 644         const struct drm_rect clip = {
 645                 .x2 = crtc->mode.hdisplay,
 646                 .y2 = crtc->mode.vdisplay,
 647         };
 648
 649         intel_fb = to_intel_framebuffer(fb);
 650         obj = intel_fb->obj;
 651
 652         old_obj = intel_plane->obj;
 653
 654         intel_plane->crtc_x = crtc_x;
 655         intel_plane->crtc_y = crtc_y;
 656         intel_plane->crtc_w = crtc_w;
 657         intel_plane->crtc_h = crtc_h;
 658         intel_plane->src_x = src_x;
 659         intel_plane->src_y = src_y;
 660         intel_plane->src_w = src_w;
 661         intel_plane->src_h = src_h;
 662
 663         /* Pipe must be running... */
 664         if (!(I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE)) {
 665                 DRM_DEBUG_KMS("Pipe disabled\n");
 666                 return -EINVAL;
 667         }
 668
 669         /* Don't modify another pipe's plane */
 670         if (intel_plane->pipe != intel_crtc->pipe) {
 671                 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
 672                 return -EINVAL;
 673         }
 674
 675         /* FIXME check all gen limits */
 676         if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) {
 677                 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
 678                 return -EINVAL;
 679         }
 680
 681         /* Sprite planes can be linear or x-tiled surfaces */
 682         switch (obj->tiling_mode) {
 683                 case I915_TILING_NONE:
 684                 case I915_TILING_X:
 685                         break;
 686                 default:
 687                         DRM_DEBUG_KMS("Unsupported tiling mode\n");
 688                         return -EINVAL;
 689         }
 690
 691         /*
 692          * FIXME the following code does a bunch of fuzzy adjustments to the
 693          * coordinates and sizes. We probably need some way to decide whether
 694          * more strict checking should be done instead.
 695          */
 696         max_scale = intel_plane->max_downscale << 16;
 697         min_scale = intel_plane->can_scale ? 1 : (1 << 16);
 698
 699         hscale = drm_rect_calc_hscale_relaxed(&src, &dst, min_scale, max_scale);
 700         BUG_ON(hscale < 0);
 701
 702         vscale = drm_rect_calc_vscale_relaxed(&src, &dst, min_scale, max_scale);
 703         BUG_ON(vscale < 0);
 704
 705         visible = drm_rect_clip_scaled(&src, &dst, &clip, hscale, vscale);
 706
 707         crtc_x = dst.x1;
 708         crtc_y = dst.y1;
 709         crtc_w = drm_rect_width(&dst);
 710         crtc_h = drm_rect_height(&dst);
 711
 712         if (visible) {
 713                 /* check again in case clipping clamped the results */
 714                 hscale = drm_rect_calc_hscale(&src, &dst, min_scale, max_scale);
 715                 if (hscale < 0) {
 716                         DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n");
 717                         drm_rect_debug_print(&src, true);
 718                         drm_rect_debug_print(&dst, false);
 719
 720                         return hscale;
 721                 }
 722
 723                 vscale = drm_rect_calc_vscale(&src, &dst, min_scale, max_scale);
 724                 if (vscale < 0) {
 725                         DRM_DEBUG_KMS("Vertical scaling factor out of limits\n");
 726                         drm_rect_debug_print(&src, true);
 727                         drm_rect_debug_print(&dst, false);
 728
 729                         return vscale;
 730                 }
 731
 732                 /* Make the source viewport size an exact multiple of the scaling factors. */
 733                 drm_rect_adjust_size(&src,
 734                                      drm_rect_width(&dst) * hscale - drm_rect_width(&src),
 735                                      drm_rect_height(&dst) * vscale - drm_rect_height(&src));
 736
 737                 /* sanity check to make sure the src viewport wasn't enlarged */
 738                 WARN_ON(src.x1 < (int) src_x ||
 739                         src.y1 < (int) src_y ||
 740                         src.x2 > (int) (src_x + src_w) ||
 741                         src.y2 > (int) (src_y + src_h));
 742
 743                 /*
 744                  * Hardware doesn't handle subpixel coordinates.
 745                  * Adjust to (macro)pixel boundary, but be careful not to
 746                  * increase the source viewport size, because that could
 747                  * push the downscaling factor out of bounds.
 748                  */
 749                 src_x = src.x1 >> 16;
 750                 src_w = drm_rect_width(&src) >> 16;
 751                 src_y = src.y1 >> 16;
 752                 src_h = drm_rect_height(&src) >> 16;
 753
 754                 if (format_is_yuv(fb->pixel_format)) {
 755                         src_x &= ~1;
 756                         src_w &= ~1;
 757
 758                         /*
 759                          * Must keep src and dst the
 760                          * same if we can't scale.
 761                          */
 762                         if (!intel_plane->can_scale)
 763                                 crtc_w &= ~1;
 764
 765                         if (crtc_w == 0)
 766                                 visible = false;
 767                 }
 768         }
 769
 770         /* Check size restrictions when scaling */
 771         if (visible && (src_w != crtc_w || src_h != crtc_h)) {
 772                 unsigned int width_bytes;
 773
 774                 WARN_ON(!intel_plane->can_scale);
 775
 776                 /* FIXME interlacing min height is 6 */
 777
 778                 if (crtc_w < 3 || crtc_h < 3)
 779                         visible = false;
 780
 781                 if (src_w < 3 || src_h < 3)
 782                         visible = false;
 783
 784                 width_bytes = ((src_x * pixel_size) & 63) + src_w * pixel_size;
 785
 786                 if (src_w > 2048 || src_h > 2048 ||
 787                     width_bytes > 4096 || fb->pitches[0] > 4096) {
 788                         DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
 789                         return -EINVAL;
 790                 }
 791         }
 792
 793         dst.x1 = crtc_x;
 794         dst.x2 = crtc_x + crtc_w;
 795         dst.y1 = crtc_y;
 796         dst.y2 = crtc_y + crtc_h;
 797
 798         /*
 799          * If the sprite is completely covering the primary plane,
 800          * we can disable the primary and save power.
 801          */
 802         disable_primary = drm_rect_equals(&dst, &clip);
 803         WARN_ON(disable_primary && !visible);
 804
 805         mutex_lock(&dev->struct_mutex);
 806
 807         /* Note that this will apply the VT-d workaround for scanouts,
 808          * which is more restrictive than required for sprites. (The
 809          * primary plane requires 256KiB alignment with 64 PTE padding,
 810          * the sprite planes only require 128KiB alignment and 32 PTE padding.
 811          */
 812         ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
 813         if (ret)
 814                 goto out_unlock;
 815
 816         intel_plane->obj = obj;
 817
 818         /*
 819          * Be sure to re-enable the primary before the sprite is no longer
 820          * covering it fully.
 821          */
 822         if (!disable_primary)
 823                 intel_enable_primary(crtc);
 824
 825         if (visible)
 826                 intel_plane->update_plane(plane, fb, obj,
 827                                           crtc_x, crtc_y, crtc_w, crtc_h,
 828                                           src_x, src_y, src_w, src_h);
 829         else
 830                 intel_plane->disable_plane(plane);
 831
 832         if (disable_primary)
 833                 intel_disable_primary(crtc);
 834
 835         /* Unpin old obj after new one is active to avoid ugliness */
 836         if (old_obj) {
 837                 /*
 838                  * It's fairly common to simply update the position of
 839                  * an existing object.  In that case, we don't need to
 840                  * wait for vblank to avoid ugliness, we only need to
 841                  * do the pin & ref bookkeeping.
 842                  */
 843                 if (old_obj != obj) {
 844                         mutex_unlock(&dev->struct_mutex);
 845                         intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
 846                         mutex_lock(&dev->struct_mutex);
 847                 }
 848                 intel_unpin_fb_obj(old_obj);
 849         }
 850
 851 out_unlock:
 852         mutex_unlock(&dev->struct_mutex);
 853         return ret;
 854 }
 855
 856 static int
 857 intel_disable_plane(struct drm_plane *plane)
 858 {
 859         struct drm_device *dev = plane->dev;
 860         struct intel_plane *intel_plane = to_intel_plane(plane);
 861         int ret = 0;
 862
 863         if (plane->crtc)
 864                 intel_enable_primary(plane->crtc);
 865         intel_plane->disable_plane(plane);
 866
 867         if (!intel_plane->obj)
 868                 goto out;
 869
 870         intel_wait_for_vblank(dev, intel_plane->pipe);
 871
 872         mutex_lock(&dev->struct_mutex);
 873         intel_unpin_fb_obj(intel_plane->obj);
 874         intel_plane->obj = NULL;
 875         mutex_unlock(&dev->struct_mutex);
 876 out:
 877
 878         return ret;
 879 }
 880
 881 static void intel_destroy_plane(struct drm_plane *plane)
 882 {
 883         struct intel_plane *intel_plane = to_intel_plane(plane);
 884         intel_disable_plane(plane);
 885         drm_plane_cleanup(plane);
 886         kfree(intel_plane);
 887 }
 888
 889 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
 890                               struct drm_file *file_priv)
 891 {
 892         struct drm_intel_sprite_colorkey *set = data;
 893         struct drm_mode_object *obj;
 894         struct drm_plane *plane;
 895         struct intel_plane *intel_plane;
 896         int ret = 0;
 897
 898         if (!drm_core_check_feature(dev, DRIVER_MODESET))
 899                 return -ENODEV;
 900
 901         /* Make sure we don't try to enable both src & dest simultaneously */
 902         if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
 903                 return -EINVAL;
 904
 905         drm_modeset_lock_all(dev);
 906
 907         obj = drm_mode_object_find(dev, set->plane_id, DRM_MODE_OBJECT_PLANE);
 908         if (!obj) {
 909                 ret = -EINVAL;
 910                 goto out_unlock;
 911         }
 912
 913         plane = obj_to_plane(obj);
 914         intel_plane = to_intel_plane(plane);
 915         ret = intel_plane->update_colorkey(plane, set);
 916
 917 out_unlock:
 918         drm_modeset_unlock_all(dev);
 919         return ret;
 920 }
 921
 922 int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
 923                               struct drm_file *file_priv)
 924 {
 925         struct drm_intel_sprite_colorkey *get = data;
 926         struct drm_mode_object *obj;
 927         struct drm_plane *plane;
 928         struct intel_plane *intel_plane;
 929         int ret = 0;
 930
 931         if (!drm_core_check_feature(dev, DRIVER_MODESET))
 932                 return -ENODEV;
 933
 934         drm_modeset_lock_all(dev);
 935
 936         obj = drm_mode_object_find(dev, get->plane_id, DRM_MODE_OBJECT_PLANE);
 937         if (!obj) {
 938                 ret = -EINVAL;
 939                 goto out_unlock;
 940         }
 941
 942         plane = obj_to_plane(obj);
 943         intel_plane = to_intel_plane(plane);
 944         intel_plane->get_colorkey(plane, get);
 945
 946 out_unlock:
 947         drm_modeset_unlock_all(dev);
 948         return ret;
 949 }
 950
 951 void intel_plane_restore(struct drm_plane *plane)
 952 {
 953         struct intel_plane *intel_plane = to_intel_plane(plane);
 954
 955         if (!plane->crtc || !plane->fb)
 956                 return;
 957
 958         intel_update_plane(plane, plane->crtc, plane->fb,
 959                            intel_plane->crtc_x, intel_plane->crtc_y,
 960                            intel_plane->crtc_w, intel_plane->crtc_h,
 961                            intel_plane->src_x, intel_plane->src_y,
 962                            intel_plane->src_w, intel_plane->src_h);
 963 }
 964
 965 void intel_plane_disable(struct drm_plane *plane)
 966 {
 967         if (!plane->crtc || !plane->fb)
 968                 return;
 969
 970         intel_disable_plane(plane);
 971 }
 972
 973 static const struct drm_plane_funcs intel_plane_funcs = {
 974         .update_plane = intel_update_plane,
 975         .disable_plane = intel_disable_plane,
 976         .destroy = intel_destroy_plane,
 977 };
 978
 979 static uint32_t ilk_plane_formats[] = {
 980         DRM_FORMAT_XRGB8888,
 981         DRM_FORMAT_YUYV,
 982         DRM_FORMAT_YVYU,
 983         DRM_FORMAT_UYVY,
 984         DRM_FORMAT_VYUY,
 985 };
 986
 987 static uint32_t snb_plane_formats[] = {
 988         DRM_FORMAT_XBGR8888,
 989         DRM_FORMAT_XRGB8888,
 990         DRM_FORMAT_YUYV,
 991         DRM_FORMAT_YVYU,
 992         DRM_FORMAT_UYVY,
 993         DRM_FORMAT_VYUY,
 994 };
 995
 996 static uint32_t vlv_plane_formats[] = {
 997         DRM_FORMAT_RGB565,
 998         DRM_FORMAT_ABGR8888,
 999         DRM_FORMAT_ARGB8888,
1000         DRM_FORMAT_XBGR8888,
1001         DRM_FORMAT_XRGB8888,
1002         DRM_FORMAT_XBGR2101010,
1003         DRM_FORMAT_ABGR2101010,
1004         DRM_FORMAT_YUYV,
1005         DRM_FORMAT_YVYU,
1006         DRM_FORMAT_UYVY,
1007         DRM_FORMAT_VYUY,
1008 };
1009
1010 int
1011 intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
1012 {
1013         struct intel_plane *intel_plane;
1014         unsigned long possible_crtcs;
1015         const uint32_t *plane_formats;
1016         int num_plane_formats;
1017         int ret;
1018
1019         if (INTEL_INFO(dev)->gen < 5)
1020                 return -ENODEV;
1021
1022         intel_plane = kzalloc(sizeof(struct intel_plane), GFP_KERNEL);
1023         if (!intel_plane)
1024                 return -ENOMEM;
1025
1026         switch (INTEL_INFO(dev)->gen) {
1027         case 5:
1028         case 6:
1029                 intel_plane->can_scale = true;
1030                 intel_plane->max_downscale = 16;
1031                 intel_plane->update_plane = ilk_update_plane;
1032                 intel_plane->disable_plane = ilk_disable_plane;
1033                 intel_plane->update_colorkey = ilk_update_colorkey;
1034                 intel_plane->get_colorkey = ilk_get_colorkey;
1035
1036                 if (IS_GEN6(dev)) {
1037                         plane_formats = snb_plane_formats;
1038                         num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1039                 } else {
1040                         plane_formats = ilk_plane_formats;
1041                         num_plane_formats = ARRAY_SIZE(ilk_plane_formats);
1042                 }
1043                 break;
1044
1045         case 7:
1046                 if (IS_IVYBRIDGE(dev)) {
1047                         intel_plane->can_scale = true;
1048                         intel_plane->max_downscale = 2;
1049                 } else {
1050                         intel_plane->can_scale = false;
1051                         intel_plane->max_downscale = 1;
1052                 }
1053
1054                 if (IS_VALLEYVIEW(dev)) {
1055                         intel_plane->update_plane = vlv_update_plane;
1056                         intel_plane->disable_plane = vlv_disable_plane;
1057                         intel_plane->update_colorkey = vlv_update_colorkey;
1058                         intel_plane->get_colorkey = vlv_get_colorkey;
1059
1060                         plane_formats = vlv_plane_formats;
1061                         num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
1062                 } else {
1063                         intel_plane->update_plane = ivb_update_plane;
1064                         intel_plane->disable_plane = ivb_disable_plane;
1065                         intel_plane->update_colorkey = ivb_update_colorkey;
1066                         intel_plane->get_colorkey = ivb_get_colorkey;
1067
1068                         plane_formats = snb_plane_formats;
1069                         num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1070                 }
1071                 break;
1072
1073         default:
1074                 kfree(intel_plane);
1075                 return -ENODEV;
1076         }
1077
1078         intel_plane->pipe = pipe;
1079         intel_plane->plane = plane;
1080         possible_crtcs = (1 << pipe);
1081         ret = drm_plane_init(dev, &intel_plane->base, possible_crtcs,
1082                              &intel_plane_funcs,
1083                              plane_formats, num_plane_formats,
1084                              false);
1085         if (ret)
1086                 kfree(intel_plane);
1087
1088         return ret;
1089 }