drivers/gpu/drm/i915/intel_sprite.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *   Jesse Barnes <jbarnes@virtuousgeek.org>
  25  *
  26  * New plane/sprite handling.
  27  *
  28  * The older chips had a separate interface for programming plane related
  29  * registers; newer ones are much simpler and we can use the new DRM plane
  30  * support.
  31  */
  32 #include <drm/drmP.h>
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_fourcc.h>
  35 #include <drm/drm_rect.h>
  36 #include <drm/drm_atomic.h>
  37 #include <drm/drm_plane_helper.h>
  38 #include "intel_drv.h"
  39 #include "intel_frontbuffer.h"
  40 #include <drm/i915_drm.h>
  41 #include "i915_drv.h"
  42
  43 static bool
  44 format_is_yuv(uint32_t format)
  45 {
  46         switch (format) {
  47         case DRM_FORMAT_YUYV:
  48         case DRM_FORMAT_UYVY:
  49         case DRM_FORMAT_VYUY:
  50         case DRM_FORMAT_YVYU:
  51                 return true;
  52         default:
  53                 return false;
  54         }
  55 }
  56
  57 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
  58                              int usecs)
  59 {
  60         /* paranoia */
  61         if (!adjusted_mode->crtc_htotal)
  62                 return 1;
  63
  64         return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock,
  65                             1000 * adjusted_mode->crtc_htotal);
  66 }
  67
  68 #define VBLANK_EVASION_TIME_US 100
  69
  70 /**
  71  * intel_pipe_update_start() - start update of a set of display registers
  72  * @crtc: the crtc of which the registers are going to be updated
  73  * @start_vbl_count: vblank counter return pointer used for error checking
  74  *
  75  * Mark the start of an update to pipe registers that should be updated
  76  * atomically regarding vblank. If the next vblank will happens within
  77  * the next 100 us, this function waits until the vblank passes.
  78  *
  79  * After a successful call to this function, interrupts will be disabled
  80  * until a subsequent call to intel_pipe_update_end(). That is done to
  81  * avoid random delays. The value written to @start_vbl_count should be
  82  * supplied to intel_pipe_update_end() for error checking.
  83  */
  84 void intel_pipe_update_start(struct intel_crtc *crtc)
  85 {
  86         const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
  87         long timeout = msecs_to_jiffies_timeout(1);
  88         int scanline, min, max, vblank_start;
  89         wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
  90         DEFINE_WAIT(wait);
  91
  92         vblank_start = adjusted_mode->crtc_vblank_start;
  93         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
  94                 vblank_start = DIV_ROUND_UP(vblank_start, 2);
  95
  96         /* FIXME needs to be calibrated sensibly */
  97         min = vblank_start - intel_usecs_to_scanlines(adjusted_mode,
  98                                                       VBLANK_EVASION_TIME_US);
  99         max = vblank_start - 1;
 100
 101         local_irq_disable();
 102
 103         if (min <= 0 || max <= 0)
 104                 return;
 105
 106         if (WARN_ON(drm_crtc_vblank_get(&crtc->base)))
 107                 return;
 108
 109         crtc->debug.min_vbl = min;
 110         crtc->debug.max_vbl = max;
 111         trace_i915_pipe_update_start(crtc);
 112
 113         for (;;) {
 114                 /*
 115                  * prepare_to_wait() has a memory barrier, which guarantees
 116                  * other CPUs can see the task state update by the time we
 117                  * read the scanline.
 118                  */
 119                 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
 120
 121                 scanline = intel_get_crtc_scanline(crtc);
 122                 if (scanline < min || scanline > max)
 123                         break;
 124
 125                 if (timeout <= 0) {
 126                         DRM_ERROR("Potential atomic update failure on pipe %c\n",
 127                                   pipe_name(crtc->pipe));
 128                         break;
 129                 }
 130
 131                 local_irq_enable();
 132
 133                 timeout = schedule_timeout(timeout);
 134
 135                 local_irq_disable();
 136         }
 137
 138         finish_wait(wq, &wait);
 139
 140         drm_crtc_vblank_put(&crtc->base);
 141
 142         crtc->debug.scanline_start = scanline;
 143         crtc->debug.start_vbl_time = ktime_get();
 144         crtc->debug.start_vbl_count = intel_crtc_get_vblank_counter(crtc);
 145
 146         trace_i915_pipe_update_vblank_evaded(crtc);
 147 }
 148
 149 /**
 150  * intel_pipe_update_end() - end update of a set of display registers
 151  * @crtc: the crtc of which the registers were updated
 152  * @start_vbl_count: start vblank counter (used for error checking)
 153  *
 154  * Mark the end of an update started with intel_pipe_update_start(). This
 155  * re-enables interrupts and verifies the update was actually completed
 156  * before a vblank using the value of @start_vbl_count.
 157  */
 158 void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work)
 159 {
 160         enum pipe pipe = crtc->pipe;
 161         int scanline_end = intel_get_crtc_scanline(crtc);
 162         u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);
 163         ktime_t end_vbl_time = ktime_get();
 164         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 165
 166         if (work) {
 167                 work->flip_queued_vblank = end_vbl_count;
 168                 smp_mb__before_atomic();
 169                 atomic_set(&work->pending, 1);
 170         }
 171
 172         trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end);
 173
 174         /* We're still in the vblank-evade critical section, this can't race.
 175          * Would be slightly nice to just grab the vblank count and arm the
 176          * event outside of the critical section - the spinlock might spin for a
 177          * while ... */
 178         if (crtc->base.state->event) {
 179                 WARN_ON(drm_crtc_vblank_get(&crtc->base) != 0);
 180
 181                 spin_lock(&crtc->base.dev->event_lock);
 182                 drm_crtc_arm_vblank_event(&crtc->base, crtc->base.state->event);
 183                 spin_unlock(&crtc->base.dev->event_lock);
 184
 185                 crtc->base.state->event = NULL;
 186         }
 187
 188         local_irq_enable();
 189
 190         if (intel_vgpu_active(dev_priv))
 191                 return;
 192
 193         if (crtc->debug.start_vbl_count &&
 194             crtc->debug.start_vbl_count != end_vbl_count) {
 195                 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n",
 196                           pipe_name(pipe), crtc->debug.start_vbl_count,
 197                           end_vbl_count,
 198                           ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
 199                           crtc->debug.min_vbl, crtc->debug.max_vbl,
 200                           crtc->debug.scanline_start, scanline_end);
 201         } else if (ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time) >
 202                    VBLANK_EVASION_TIME_US)
 203                 DRM_WARN("Atomic update on pipe (%c) took %lld us, max time under evasion is %u us\n",
 204                          pipe_name(pipe),
 205                          ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
 206                          VBLANK_EVASION_TIME_US);
 207 }
 208
 209 static void
 210 skl_update_plane(struct drm_plane *drm_plane,
 211                  const struct intel_crtc_state *crtc_state,
 212                  const struct intel_plane_state *plane_state)
 213 {
 214         struct drm_device *dev = drm_plane->dev;
 215         struct drm_i915_private *dev_priv = to_i915(dev);
 216         struct intel_plane *intel_plane = to_intel_plane(drm_plane);
 217         struct drm_framebuffer *fb = plane_state->base.fb;
 218         enum plane_id plane_id = intel_plane->id;
 219         enum pipe pipe = intel_plane->pipe;
 220         u32 plane_ctl = plane_state->ctl;
 221         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 222         u32 surf_addr = plane_state->main.offset;
 223         unsigned int rotation = plane_state->base.rotation;
 224         u32 stride = skl_plane_stride(fb, 0, rotation);
 225         int crtc_x = plane_state->base.dst.x1;
 226         int crtc_y = plane_state->base.dst.y1;
 227         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
 228         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
 229         uint32_t x = plane_state->main.x;
 230         uint32_t y = plane_state->main.y;
 231         uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
 232         uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
 233         unsigned long irqflags;
 234
 235         /* Sizes are 0 based */
 236         src_w--;
 237         src_h--;
 238         crtc_w--;
 239         crtc_h--;
 240
 241         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 242
 243         if (IS_GEMINILAKE(dev_priv)) {
 244                 I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
 245                               PLANE_COLOR_PIPE_GAMMA_ENABLE |
 246                               PLANE_COLOR_PIPE_CSC_ENABLE |
 247                               PLANE_COLOR_PLANE_GAMMA_DISABLE);
 248         }
 249
 250         if (key->flags) {
 251                 I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
 252                 I915_WRITE_FW(PLANE_KEYMAX(pipe, plane_id), key->max_value);
 253                 I915_WRITE_FW(PLANE_KEYMSK(pipe, plane_id), key->channel_mask);
 254         }
 255
 256         I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (y << 16) | x);
 257         I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
 258         I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
 259
 260         /* program plane scaler */
 261         if (plane_state->scaler_id >= 0) {
 262                 int scaler_id = plane_state->scaler_id;
 263                 const struct intel_scaler *scaler;
 264
 265                 scaler = &crtc_state->scaler_state.scalers[scaler_id];
 266
 267                 I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id),
 268                               PS_SCALER_EN | PS_PLANE_SEL(plane_id) | scaler->mode);
 269                 I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
 270                 I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);
 271                 I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id),
 272                               ((crtc_w + 1) << 16)|(crtc_h + 1));
 273
 274                 I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0);
 275         } else {
 276                 I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x);
 277         }
 278
 279         I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
 280         I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
 281                       intel_plane_ggtt_offset(plane_state) + surf_addr);
 282         POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
 283
 284         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 285 }
 286
 287 static void
 288 skl_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
 289 {
 290         struct drm_device *dev = dplane->dev;
 291         struct drm_i915_private *dev_priv = to_i915(dev);
 292         struct intel_plane *intel_plane = to_intel_plane(dplane);
 293         enum plane_id plane_id = intel_plane->id;
 294         enum pipe pipe = intel_plane->pipe;
 295         unsigned long irqflags;
 296
 297         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 298
 299         I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
 300
 301         I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);
 302         POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
 303
 304         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 305 }
 306
 307 static void
 308 chv_update_csc(struct intel_plane *intel_plane, uint32_t format)
 309 {
 310         struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
 311         enum plane_id plane_id = intel_plane->id;
 312
 313         /* Seems RGB data bypasses the CSC always */
 314         if (!format_is_yuv(format))
 315                 return;
 316
 317         /*
 318          * BT.601 limited range YCbCr -> full range RGB
 319          *
 320          * |r|   | 6537 4769     0|   |cr  |
 321          * |g| = |-3330 4769 -1605| x |y-64|
 322          * |b|   |    0 4769  8263|   |cb  |
 323          *
 324          * Cb and Cr apparently come in as signed already, so no
 325          * need for any offset. For Y we need to remove the offset.
 326          */
 327         I915_WRITE_FW(SPCSCYGOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(-64));
 328         I915_WRITE_FW(SPCSCCBOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
 329         I915_WRITE_FW(SPCSCCROFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
 330
 331         I915_WRITE_FW(SPCSCC01(plane_id), SPCSC_C1(4769) | SPCSC_C0(6537));
 332         I915_WRITE_FW(SPCSCC23(plane_id), SPCSC_C1(-3330) | SPCSC_C0(0));
 333         I915_WRITE_FW(SPCSCC45(plane_id), SPCSC_C1(-1605) | SPCSC_C0(4769));
 334         I915_WRITE_FW(SPCSCC67(plane_id), SPCSC_C1(4769) | SPCSC_C0(0));
 335         I915_WRITE_FW(SPCSCC8(plane_id), SPCSC_C0(8263));
 336
 337         I915_WRITE_FW(SPCSCYGICLAMP(plane_id), SPCSC_IMAX(940) | SPCSC_IMIN(64));
 338         I915_WRITE_FW(SPCSCCBICLAMP(plane_id), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
 339         I915_WRITE_FW(SPCSCCRICLAMP(plane_id), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
 340
 341         I915_WRITE_FW(SPCSCYGOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 342         I915_WRITE_FW(SPCSCCBOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 343         I915_WRITE_FW(SPCSCCROCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 344 }
 345
 346 static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,
 347                           const struct intel_plane_state *plane_state)
 348 {
 349         const struct drm_framebuffer *fb = plane_state->base.fb;
 350         unsigned int rotation = plane_state->base.rotation;
 351         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 352         u32 sprctl;
 353
 354         sprctl = SP_ENABLE | SP_GAMMA_ENABLE;
 355
 356         switch (fb->format->format) {
 357         case DRM_FORMAT_YUYV:
 358                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
 359                 break;
 360         case DRM_FORMAT_YVYU:
 361                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
 362                 break;
 363         case DRM_FORMAT_UYVY:
 364                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
 365                 break;
 366         case DRM_FORMAT_VYUY:
 367                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
 368                 break;
 369         case DRM_FORMAT_RGB565:
 370                 sprctl |= SP_FORMAT_BGR565;
 371                 break;
 372         case DRM_FORMAT_XRGB8888:
 373                 sprctl |= SP_FORMAT_BGRX8888;
 374                 break;
 375         case DRM_FORMAT_ARGB8888:
 376                 sprctl |= SP_FORMAT_BGRA8888;
 377                 break;
 378         case DRM_FORMAT_XBGR2101010:
 379                 sprctl |= SP_FORMAT_RGBX1010102;
 380                 break;
 381         case DRM_FORMAT_ABGR2101010:
 382                 sprctl |= SP_FORMAT_RGBA1010102;
 383                 break;
 384         case DRM_FORMAT_XBGR8888:
 385                 sprctl |= SP_FORMAT_RGBX8888;
 386                 break;
 387         case DRM_FORMAT_ABGR8888:
 388                 sprctl |= SP_FORMAT_RGBA8888;
 389                 break;
 390         default:
 391                 MISSING_CASE(fb->format->format);
 392                 return 0;
 393         }
 394
 395         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 396                 sprctl |= SP_TILED;
 397
 398         if (rotation & DRM_ROTATE_180)
 399                 sprctl |= SP_ROTATE_180;
 400
 401         if (rotation & DRM_REFLECT_X)
 402                 sprctl |= SP_MIRROR;
 403
 404         if (key->flags & I915_SET_COLORKEY_SOURCE)
 405                 sprctl |= SP_SOURCE_KEY;
 406
 407         return sprctl;
 408 }
 409
 410 static void
 411 vlv_update_plane(struct drm_plane *dplane,
 412                  const struct intel_crtc_state *crtc_state,
 413                  const struct intel_plane_state *plane_state)
 414 {
 415         struct drm_device *dev = dplane->dev;
 416         struct drm_i915_private *dev_priv = to_i915(dev);
 417         struct intel_plane *intel_plane = to_intel_plane(dplane);
 418         struct drm_framebuffer *fb = plane_state->base.fb;
 419         enum pipe pipe = intel_plane->pipe;
 420         enum plane_id plane_id = intel_plane->id;
 421         u32 sprctl = plane_state->ctl;
 422         u32 sprsurf_offset = plane_state->main.offset;
 423         u32 linear_offset;
 424         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 425         int crtc_x = plane_state->base.dst.x1;
 426         int crtc_y = plane_state->base.dst.y1;
 427         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
 428         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
 429         uint32_t x = plane_state->main.x;
 430         uint32_t y = plane_state->main.y;
 431         unsigned long irqflags;
 432
 433         /* Sizes are 0 based */
 434         crtc_w--;
 435         crtc_h--;
 436
 437         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 438
 439         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 440
 441         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B)
 442                 chv_update_csc(intel_plane, fb->format->format);
 443
 444         if (key->flags) {
 445                 I915_WRITE_FW(SPKEYMINVAL(pipe, plane_id), key->min_value);
 446                 I915_WRITE_FW(SPKEYMAXVAL(pipe, plane_id), key->max_value);
 447                 I915_WRITE_FW(SPKEYMSK(pipe, plane_id), key->channel_mask);
 448         }
 449         I915_WRITE_FW(SPSTRIDE(pipe, plane_id), fb->pitches[0]);
 450         I915_WRITE_FW(SPPOS(pipe, plane_id), (crtc_y << 16) | crtc_x);
 451
 452         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 453                 I915_WRITE_FW(SPTILEOFF(pipe, plane_id), (y << 16) | x);
 454         else
 455                 I915_WRITE_FW(SPLINOFF(pipe, plane_id), linear_offset);
 456
 457         I915_WRITE_FW(SPCONSTALPHA(pipe, plane_id), 0);
 458
 459         I915_WRITE_FW(SPSIZE(pipe, plane_id), (crtc_h << 16) | crtc_w);
 460         I915_WRITE_FW(SPCNTR(pipe, plane_id), sprctl);
 461         I915_WRITE_FW(SPSURF(pipe, plane_id),
 462                       intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
 463         POSTING_READ_FW(SPSURF(pipe, plane_id));
 464
 465         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 466 }
 467
 468 static void
 469 vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
 470 {
 471         struct drm_device *dev = dplane->dev;
 472         struct drm_i915_private *dev_priv = to_i915(dev);
 473         struct intel_plane *intel_plane = to_intel_plane(dplane);
 474         enum pipe pipe = intel_plane->pipe;
 475         enum plane_id plane_id = intel_plane->id;
 476         unsigned long irqflags;
 477
 478         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 479
 480         I915_WRITE_FW(SPCNTR(pipe, plane_id), 0);
 481
 482         I915_WRITE_FW(SPSURF(pipe, plane_id), 0);
 483         POSTING_READ_FW(SPSURF(pipe, plane_id));
 484
 485         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 486 }
 487
 488 static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state,
 489                           const struct intel_plane_state *plane_state)
 490 {
 491         struct drm_i915_private *dev_priv =
 492                 to_i915(plane_state->base.plane->dev);
 493         const struct drm_framebuffer *fb = plane_state->base.fb;
 494         unsigned int rotation = plane_state->base.rotation;
 495         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 496         u32 sprctl;
 497
 498         sprctl = SPRITE_ENABLE | SPRITE_GAMMA_ENABLE;
 499
 500         if (IS_IVYBRIDGE(dev_priv))
 501                 sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
 502
 503         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 504                 sprctl |= SPRITE_PIPE_CSC_ENABLE;
 505
 506         switch (fb->format->format) {
 507         case DRM_FORMAT_XBGR8888:
 508                 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
 509                 break;
 510         case DRM_FORMAT_XRGB8888:
 511                 sprctl |= SPRITE_FORMAT_RGBX888;
 512                 break;
 513         case DRM_FORMAT_YUYV:
 514                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
 515                 break;
 516         case DRM_FORMAT_YVYU:
 517                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
 518                 break;
 519         case DRM_FORMAT_UYVY:
 520                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
 521                 break;
 522         case DRM_FORMAT_VYUY:
 523                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
 524                 break;
 525         default:
 526                 MISSING_CASE(fb->format->format);
 527                 return 0;
 528         }
 529
 530         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 531                 sprctl |= SPRITE_TILED;
 532
 533         if (rotation & DRM_ROTATE_180)
 534                 sprctl |= SPRITE_ROTATE_180;
 535
 536         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 537                 sprctl |= SPRITE_DEST_KEY;
 538         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 539                 sprctl |= SPRITE_SOURCE_KEY;
 540
 541         return sprctl;
 542 }
 543
 544 static void
 545 ivb_update_plane(struct drm_plane *plane,
 546                  const struct intel_crtc_state *crtc_state,
 547                  const struct intel_plane_state *plane_state)
 548 {
 549         struct drm_device *dev = plane->dev;
 550         struct drm_i915_private *dev_priv = to_i915(dev);
 551         struct intel_plane *intel_plane = to_intel_plane(plane);
 552         struct drm_framebuffer *fb = plane_state->base.fb;
 553         enum pipe pipe = intel_plane->pipe;
 554         u32 sprctl = plane_state->ctl, sprscale = 0;
 555         u32 sprsurf_offset = plane_state->main.offset;
 556         u32 linear_offset;
 557         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 558         int crtc_x = plane_state->base.dst.x1;
 559         int crtc_y = plane_state->base.dst.y1;
 560         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
 561         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
 562         uint32_t x = plane_state->main.x;
 563         uint32_t y = plane_state->main.y;
 564         uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
 565         uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
 566         unsigned long irqflags;
 567
 568         /* Sizes are 0 based */
 569         src_w--;
 570         src_h--;
 571         crtc_w--;
 572         crtc_h--;
 573
 574         if (crtc_w != src_w || crtc_h != src_h)
 575                 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
 576
 577         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 578
 579         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 580
 581         if (key->flags) {
 582                 I915_WRITE_FW(SPRKEYVAL(pipe), key->min_value);
 583                 I915_WRITE_FW(SPRKEYMAX(pipe), key->max_value);
 584                 I915_WRITE_FW(SPRKEYMSK(pipe), key->channel_mask);
 585         }
 586
 587         I915_WRITE_FW(SPRSTRIDE(pipe), fb->pitches[0]);
 588         I915_WRITE_FW(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
 589
 590         /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
 591          * register */
 592         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 593                 I915_WRITE_FW(SPROFFSET(pipe), (y << 16) | x);
 594         else if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 595                 I915_WRITE_FW(SPRTILEOFF(pipe), (y << 16) | x);
 596         else
 597                 I915_WRITE_FW(SPRLINOFF(pipe), linear_offset);
 598
 599         I915_WRITE_FW(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
 600         if (intel_plane->can_scale)
 601                 I915_WRITE_FW(SPRSCALE(pipe), sprscale);
 602         I915_WRITE_FW(SPRCTL(pipe), sprctl);
 603         I915_WRITE_FW(SPRSURF(pipe),
 604                       intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
 605         POSTING_READ_FW(SPRSURF(pipe));
 606
 607         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 608 }
 609
 610 static void
 611 ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
 612 {
 613         struct drm_device *dev = plane->dev;
 614         struct drm_i915_private *dev_priv = to_i915(dev);
 615         struct intel_plane *intel_plane = to_intel_plane(plane);
 616         int pipe = intel_plane->pipe;
 617         unsigned long irqflags;
 618
 619         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 620
 621         I915_WRITE_FW(SPRCTL(pipe), 0);
 622         /* Can't leave the scaler enabled... */
 623         if (intel_plane->can_scale)
 624                 I915_WRITE_FW(SPRSCALE(pipe), 0);
 625
 626         I915_WRITE_FW(SPRSURF(pipe), 0);
 627         POSTING_READ_FW(SPRSURF(pipe));
 628
 629         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 630 }
 631
 632 static u32 ilk_sprite_ctl(const struct intel_crtc_state *crtc_state,
 633                           const struct intel_plane_state *plane_state)
 634 {
 635         struct drm_i915_private *dev_priv =
 636                 to_i915(plane_state->base.plane->dev);
 637         const struct drm_framebuffer *fb = plane_state->base.fb;
 638         unsigned int rotation = plane_state->base.rotation;
 639         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 640         u32 dvscntr;
 641
 642         dvscntr = DVS_ENABLE | DVS_GAMMA_ENABLE;
 643
 644         if (IS_GEN6(dev_priv))
 645                 dvscntr |= DVS_TRICKLE_FEED_DISABLE;
 646
 647         switch (fb->format->format) {
 648         case DRM_FORMAT_XBGR8888:
 649                 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
 650                 break;
 651         case DRM_FORMAT_XRGB8888:
 652                 dvscntr |= DVS_FORMAT_RGBX888;
 653                 break;
 654         case DRM_FORMAT_YUYV:
 655                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
 656                 break;
 657         case DRM_FORMAT_YVYU:
 658                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
 659                 break;
 660         case DRM_FORMAT_UYVY:
 661                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
 662                 break;
 663         case DRM_FORMAT_VYUY:
 664                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
 665                 break;
 666         default:
 667                 MISSING_CASE(fb->format->format);
 668                 return 0;
 669         }
 670
 671         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 672                 dvscntr |= DVS_TILED;
 673
 674         if (rotation & DRM_ROTATE_180)
 675                 dvscntr |= DVS_ROTATE_180;
 676
 677         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 678                 dvscntr |= DVS_DEST_KEY;
 679         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 680                 dvscntr |= DVS_SOURCE_KEY;
 681
 682         return dvscntr;
 683 }
 684
 685 static void
 686 ilk_update_plane(struct drm_plane *plane,
 687                  const struct intel_crtc_state *crtc_state,
 688                  const struct intel_plane_state *plane_state)
 689 {
 690         struct drm_device *dev = plane->dev;
 691         struct drm_i915_private *dev_priv = to_i915(dev);
 692         struct intel_plane *intel_plane = to_intel_plane(plane);
 693         struct drm_framebuffer *fb = plane_state->base.fb;
 694         int pipe = intel_plane->pipe;
 695         u32 dvscntr = plane_state->ctl, dvsscale = 0;
 696         u32 dvssurf_offset = plane_state->main.offset;
 697         u32 linear_offset;
 698         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 699         int crtc_x = plane_state->base.dst.x1;
 700         int crtc_y = plane_state->base.dst.y1;
 701         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
 702         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
 703         uint32_t x = plane_state->main.x;
 704         uint32_t y = plane_state->main.y;
 705         uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
 706         uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
 707         unsigned long irqflags;
 708
 709         /* Sizes are 0 based */
 710         src_w--;
 711         src_h--;
 712         crtc_w--;
 713         crtc_h--;
 714
 715         if (crtc_w != src_w || crtc_h != src_h)
 716                 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
 717
 718         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 719
 720         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 721
 722         if (key->flags) {
 723                 I915_WRITE_FW(DVSKEYVAL(pipe), key->min_value);
 724                 I915_WRITE_FW(DVSKEYMAX(pipe), key->max_value);
 725                 I915_WRITE_FW(DVSKEYMSK(pipe), key->channel_mask);
 726         }
 727
 728         I915_WRITE_FW(DVSSTRIDE(pipe), fb->pitches[0]);
 729         I915_WRITE_FW(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
 730
 731         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 732                 I915_WRITE_FW(DVSTILEOFF(pipe), (y << 16) | x);
 733         else
 734                 I915_WRITE_FW(DVSLINOFF(pipe), linear_offset);
 735
 736         I915_WRITE_FW(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
 737         I915_WRITE_FW(DVSSCALE(pipe), dvsscale);
 738         I915_WRITE_FW(DVSCNTR(pipe), dvscntr);
 739         I915_WRITE_FW(DVSSURF(pipe),
 740                       intel_plane_ggtt_offset(plane_state) + dvssurf_offset);
 741         POSTING_READ_FW(DVSSURF(pipe));
 742
 743         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 744 }
 745
 746 static void
 747 ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
 748 {
 749         struct drm_device *dev = plane->dev;
 750         struct drm_i915_private *dev_priv = to_i915(dev);
 751         struct intel_plane *intel_plane = to_intel_plane(plane);
 752         int pipe = intel_plane->pipe;
 753         unsigned long irqflags;
 754
 755         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 756
 757         I915_WRITE_FW(DVSCNTR(pipe), 0);
 758         /* Disable the scaler */
 759         I915_WRITE_FW(DVSSCALE(pipe), 0);
 760
 761         I915_WRITE_FW(DVSSURF(pipe), 0);
 762         POSTING_READ_FW(DVSSURF(pipe));
 763
 764         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 765 }
 766
 767 static int
 768 intel_check_sprite_plane(struct drm_plane *plane,
 769                          struct intel_crtc_state *crtc_state,
 770                          struct intel_plane_state *state)
 771 {
 772         struct drm_i915_private *dev_priv = to_i915(plane->dev);
 773         struct drm_crtc *crtc = state->base.crtc;
 774         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 775         struct intel_plane *intel_plane = to_intel_plane(plane);
 776         struct drm_framebuffer *fb = state->base.fb;
 777         int crtc_x, crtc_y;
 778         unsigned int crtc_w, crtc_h;
 779         uint32_t src_x, src_y, src_w, src_h;
 780         struct drm_rect *src = &state->base.src;
 781         struct drm_rect *dst = &state->base.dst;
 782         const struct drm_rect *clip = &state->clip;
 783         int hscale, vscale;
 784         int max_scale, min_scale;
 785         bool can_scale;
 786         int ret;
 787
 788         *src = drm_plane_state_src(&state->base);
 789         *dst = drm_plane_state_dest(&state->base);
 790
 791         if (!fb) {
 792                 state->base.visible = false;
 793                 return 0;
 794         }
 795
 796         /* Don't modify another pipe's plane */
 797         if (intel_plane->pipe != intel_crtc->pipe) {
 798                 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
 799                 return -EINVAL;
 800         }
 801
 802         /* FIXME check all gen limits */
 803         if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) {
 804                 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
 805                 return -EINVAL;
 806         }
 807
 808         /* setup can_scale, min_scale, max_scale */
 809         if (INTEL_GEN(dev_priv) >= 9) {
 810                 /* use scaler when colorkey is not required */
 811                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
 812                         can_scale = 1;
 813                         min_scale = 1;
 814                         max_scale = skl_max_scale(intel_crtc, crtc_state);
 815                 } else {
 816                         can_scale = 0;
 817                         min_scale = DRM_PLANE_HELPER_NO_SCALING;
 818                         max_scale = DRM_PLANE_HELPER_NO_SCALING;
 819                 }
 820         } else {
 821                 can_scale = intel_plane->can_scale;
 822                 max_scale = intel_plane->max_downscale << 16;
 823                 min_scale = intel_plane->can_scale ? 1 : (1 << 16);
 824         }
 825
 826         /*
 827          * FIXME the following code does a bunch of fuzzy adjustments to the
 828          * coordinates and sizes. We probably need some way to decide whether
 829          * more strict checking should be done instead.
 830          */
 831         drm_rect_rotate(src, fb->width << 16, fb->height << 16,
 832                         state->base.rotation);
 833
 834         hscale = drm_rect_calc_hscale_relaxed(src, dst, min_scale, max_scale);
 835         BUG_ON(hscale < 0);
 836
 837         vscale = drm_rect_calc_vscale_relaxed(src, dst, min_scale, max_scale);
 838         BUG_ON(vscale < 0);
 839
 840         state->base.visible = drm_rect_clip_scaled(src, dst, clip, hscale, vscale);
 841
 842         crtc_x = dst->x1;
 843         crtc_y = dst->y1;
 844         crtc_w = drm_rect_width(dst);
 845         crtc_h = drm_rect_height(dst);
 846
 847         if (state->base.visible) {
 848                 /* check again in case clipping clamped the results */
 849                 hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
 850                 if (hscale < 0) {
 851                         DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n");
 852                         drm_rect_debug_print("src: ", src, true);
 853                         drm_rect_debug_print("dst: ", dst, false);
 854
 855                         return hscale;
 856                 }
 857
 858                 vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
 859                 if (vscale < 0) {
 860                         DRM_DEBUG_KMS("Vertical scaling factor out of limits\n");
 861                         drm_rect_debug_print("src: ", src, true);
 862                         drm_rect_debug_print("dst: ", dst, false);
 863
 864                         return vscale;
 865                 }
 866
 867                 /* Make the source viewport size an exact multiple of the scaling factors. */
 868                 drm_rect_adjust_size(src,
 869                                      drm_rect_width(dst) * hscale - drm_rect_width(src),
 870                                      drm_rect_height(dst) * vscale - drm_rect_height(src));
 871
 872                 drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16,
 873                                     state->base.rotation);
 874
 875                 /* sanity check to make sure the src viewport wasn't enlarged */
 876                 WARN_ON(src->x1 < (int) state->base.src_x ||
 877                         src->y1 < (int) state->base.src_y ||
 878                         src->x2 > (int) state->base.src_x + state->base.src_w ||
 879                         src->y2 > (int) state->base.src_y + state->base.src_h);
 880
 881                 /*
 882                  * Hardware doesn't handle subpixel coordinates.
 883                  * Adjust to (macro)pixel boundary, but be careful not to
 884                  * increase the source viewport size, because that could
 885                  * push the downscaling factor out of bounds.
 886                  */
 887                 src_x = src->x1 >> 16;
 888                 src_w = drm_rect_width(src) >> 16;
 889                 src_y = src->y1 >> 16;
 890                 src_h = drm_rect_height(src) >> 16;
 891
 892                 if (format_is_yuv(fb->format->format)) {
 893                         src_x &= ~1;
 894                         src_w &= ~1;
 895
 896                         /*
 897                          * Must keep src and dst the
 898                          * same if we can't scale.
 899                          */
 900                         if (!can_scale)
 901                                 crtc_w &= ~1;
 902
 903                         if (crtc_w == 0)
 904                                 state->base.visible = false;
 905                 }
 906         }
 907
 908         /* Check size restrictions when scaling */
 909         if (state->base.visible && (src_w != crtc_w || src_h != crtc_h)) {
 910                 unsigned int width_bytes;
 911                 int cpp = fb->format->cpp[0];
 912
 913                 WARN_ON(!can_scale);
 914
 915                 /* FIXME interlacing min height is 6 */
 916
 917                 if (crtc_w < 3 || crtc_h < 3)
 918                         state->base.visible = false;
 919
 920                 if (src_w < 3 || src_h < 3)
 921                         state->base.visible = false;
 922
 923                 width_bytes = ((src_x * cpp) & 63) + src_w * cpp;
 924
 925                 if (INTEL_GEN(dev_priv) < 9 && (src_w > 2048 || src_h > 2048 ||
 926                     width_bytes > 4096 || fb->pitches[0] > 4096)) {
 927                         DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
 928                         return -EINVAL;
 929                 }
 930         }
 931
 932         if (state->base.visible) {
 933                 src->x1 = src_x << 16;
 934                 src->x2 = (src_x + src_w) << 16;
 935                 src->y1 = src_y << 16;
 936                 src->y2 = (src_y + src_h) << 16;
 937         }
 938
 939         dst->x1 = crtc_x;
 940         dst->x2 = crtc_x + crtc_w;
 941         dst->y1 = crtc_y;
 942         dst->y2 = crtc_y + crtc_h;
 943
 944         if (INTEL_GEN(dev_priv) >= 9) {
 945                 ret = skl_check_plane_surface(state);
 946                 if (ret)
 947                         return ret;
 948
 949                 state->ctl = skl_plane_ctl(crtc_state, state);
 950         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 951                 ret = i9xx_check_plane_surface(state);
 952                 if (ret)
 953                         return ret;
 954
 955                 state->ctl = vlv_sprite_ctl(crtc_state, state);
 956         } else if (INTEL_GEN(dev_priv) >= 7) {
 957                 ret = i9xx_check_plane_surface(state);
 958                 if (ret)
 959                         return ret;
 960
 961                 state->ctl = ivb_sprite_ctl(crtc_state, state);
 962         } else {
 963                 ret = i9xx_check_plane_surface(state);
 964                 if (ret)
 965                         return ret;
 966
 967                 state->ctl = ilk_sprite_ctl(crtc_state, state);
 968         }
 969
 970         return 0;
 971 }
 972
 973 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
 974                               struct drm_file *file_priv)
 975 {
 976         struct drm_i915_private *dev_priv = to_i915(dev);
 977         struct drm_intel_sprite_colorkey *set = data;
 978         struct drm_plane *plane;
 979         struct drm_plane_state *plane_state;
 980         struct drm_atomic_state *state;
 981         struct drm_modeset_acquire_ctx ctx;
 982         int ret = 0;
 983
 984         /* Make sure we don't try to enable both src & dest simultaneously */
 985         if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
 986                 return -EINVAL;
 987
 988         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
 989             set->flags & I915_SET_COLORKEY_DESTINATION)
 990                 return -EINVAL;
 991
 992         plane = drm_plane_find(dev, set->plane_id);
 993         if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY)
 994                 return -ENOENT;
 995
 996         drm_modeset_acquire_init(&ctx, 0);
 997
 998         state = drm_atomic_state_alloc(plane->dev);
 999         if (!state) {
1000                 ret = -ENOMEM;
1001                 goto out;
1002         }
1003         state->acquire_ctx = &ctx;
1004
1005         while (1) {
1006                 plane_state = drm_atomic_get_plane_state(state, plane);
1007                 ret = PTR_ERR_OR_ZERO(plane_state);
1008                 if (!ret) {
1009                         to_intel_plane_state(plane_state)->ckey = *set;
1010                         ret = drm_atomic_commit(state);
1011                 }
1012
1013                 if (ret != -EDEADLK)
1014                         break;
1015
1016                 drm_atomic_state_clear(state);
1017                 drm_modeset_backoff(&ctx);
1018         }
1019
1020         drm_atomic_state_put(state);
1021 out:
1022         drm_modeset_drop_locks(&ctx);
1023         drm_modeset_acquire_fini(&ctx);
1024         return ret;
1025 }
1026
1027 static const uint32_t ilk_plane_formats[] = {
1028         DRM_FORMAT_XRGB8888,
1029         DRM_FORMAT_YUYV,
1030         DRM_FORMAT_YVYU,
1031         DRM_FORMAT_UYVY,
1032         DRM_FORMAT_VYUY,
1033 };
1034
1035 static const uint32_t snb_plane_formats[] = {
1036         DRM_FORMAT_XBGR8888,
1037         DRM_FORMAT_XRGB8888,
1038         DRM_FORMAT_YUYV,
1039         DRM_FORMAT_YVYU,
1040         DRM_FORMAT_UYVY,
1041         DRM_FORMAT_VYUY,
1042 };
1043
1044 static const uint32_t vlv_plane_formats[] = {
1045         DRM_FORMAT_RGB565,
1046         DRM_FORMAT_ABGR8888,
1047         DRM_FORMAT_ARGB8888,
1048         DRM_FORMAT_XBGR8888,
1049         DRM_FORMAT_XRGB8888,
1050         DRM_FORMAT_XBGR2101010,
1051         DRM_FORMAT_ABGR2101010,
1052         DRM_FORMAT_YUYV,
1053         DRM_FORMAT_YVYU,
1054         DRM_FORMAT_UYVY,
1055         DRM_FORMAT_VYUY,
1056 };
1057
1058 static uint32_t skl_plane_formats[] = {
1059         DRM_FORMAT_RGB565,
1060         DRM_FORMAT_ABGR8888,
1061         DRM_FORMAT_ARGB8888,
1062         DRM_FORMAT_XBGR8888,
1063         DRM_FORMAT_XRGB8888,
1064         DRM_FORMAT_YUYV,
1065         DRM_FORMAT_YVYU,
1066         DRM_FORMAT_UYVY,
1067         DRM_FORMAT_VYUY,
1068 };
1069
1070 struct intel_plane *
1071 intel_sprite_plane_create(struct drm_i915_private *dev_priv,
1072                           enum pipe pipe, int plane)
1073 {
1074         struct intel_plane *intel_plane = NULL;
1075         struct intel_plane_state *state = NULL;
1076         unsigned long possible_crtcs;
1077         const uint32_t *plane_formats;
1078         unsigned int supported_rotations;
1079         int num_plane_formats;
1080         int ret;
1081
1082         intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL);
1083         if (!intel_plane) {
1084                 ret = -ENOMEM;
1085                 goto fail;
1086         }
1087
1088         state = intel_create_plane_state(&intel_plane->base);
1089         if (!state) {
1090                 ret = -ENOMEM;
1091                 goto fail;
1092         }
1093         intel_plane->base.state = &state->base;
1094
1095         if (INTEL_GEN(dev_priv) >= 9) {
1096                 intel_plane->can_scale = true;
1097                 state->scaler_id = -1;
1098
1099                 intel_plane->update_plane = skl_update_plane;
1100                 intel_plane->disable_plane = skl_disable_plane;
1101
1102                 plane_formats = skl_plane_formats;
1103                 num_plane_formats = ARRAY_SIZE(skl_plane_formats);
1104         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1105                 intel_plane->can_scale = false;
1106                 intel_plane->max_downscale = 1;
1107
1108                 intel_plane->update_plane = vlv_update_plane;
1109                 intel_plane->disable_plane = vlv_disable_plane;
1110
1111                 plane_formats = vlv_plane_formats;
1112                 num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
1113         } else if (INTEL_GEN(dev_priv) >= 7) {
1114                 if (IS_IVYBRIDGE(dev_priv)) {
1115                         intel_plane->can_scale = true;
1116                         intel_plane->max_downscale = 2;
1117                 } else {
1118                         intel_plane->can_scale = false;
1119                         intel_plane->max_downscale = 1;
1120                 }
1121
1122                 intel_plane->update_plane = ivb_update_plane;
1123                 intel_plane->disable_plane = ivb_disable_plane;
1124
1125                 plane_formats = snb_plane_formats;
1126                 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1127         } else {
1128                 intel_plane->can_scale = true;
1129                 intel_plane->max_downscale = 16;
1130
1131                 intel_plane->update_plane = ilk_update_plane;
1132                 intel_plane->disable_plane = ilk_disable_plane;
1133
1134                 if (IS_GEN6(dev_priv)) {
1135                         plane_formats = snb_plane_formats;
1136                         num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1137                 } else {
1138                         plane_formats = ilk_plane_formats;
1139                         num_plane_formats = ARRAY_SIZE(ilk_plane_formats);
1140                 }
1141         }
1142
1143         if (INTEL_GEN(dev_priv) >= 9) {
1144                 supported_rotations =
1145                         DRM_ROTATE_0 | DRM_ROTATE_90 |
1146                         DRM_ROTATE_180 | DRM_ROTATE_270;
1147         } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
1148                 supported_rotations =
1149                         DRM_ROTATE_0 | DRM_ROTATE_180 |
1150                         DRM_REFLECT_X;
1151         } else {
1152                 supported_rotations =
1153                         DRM_ROTATE_0 | DRM_ROTATE_180;
1154         }
1155
1156         intel_plane->pipe = pipe;
1157         intel_plane->plane = plane;
1158         intel_plane->id = PLANE_SPRITE0 + plane;
1159         intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER_SPRITE(pipe, plane);
1160         intel_plane->check_plane = intel_check_sprite_plane;
1161
1162         possible_crtcs = (1 << pipe);
1163
1164         if (INTEL_GEN(dev_priv) >= 9)
1165                 ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base,
1166                                                possible_crtcs, &intel_plane_funcs,
1167                                                plane_formats, num_plane_formats,
1168                                                DRM_PLANE_TYPE_OVERLAY,
1169                                                "plane %d%c", plane + 2, pipe_name(pipe));
1170         else
1171                 ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base,
1172                                                possible_crtcs, &intel_plane_funcs,
1173                                                plane_formats, num_plane_formats,
1174                                                DRM_PLANE_TYPE_OVERLAY,
1175                                                "sprite %c", sprite_name(pipe, plane));
1176         if (ret)
1177                 goto fail;
1178
1179         drm_plane_create_rotation_property(&intel_plane->base,
1180                                            DRM_ROTATE_0,
1181                                            supported_rotations);
1182
1183         drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs);
1184
1185         return intel_plane;
1186
1187 fail:
1188         kfree(state);
1189         kfree(intel_plane);
1190
1191         return ERR_PTR(ret);
1192 }