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27 #include "intel_guc_fwif.h"
28 #include "i915_guc_reg.h"
29 #include "intel_ringbuffer.h"
31 struct drm_i915_gem_request;
34 * This structure primarily describes the GEM object shared with the GuC.
35 * The GEM object is held for the entire lifetime of our interaction with
36 * the GuC, being allocated before the GuC is loaded with its firmware.
37 * Because there's no way to update the address used by the GuC after
38 * initialisation, the shared object must stay pinned into the GGTT as
39 * long as the GuC is in use. We also keep the first page (only) mapped
40 * into kernel address space, as it includes shared data that must be
41 * updated on every request submission.
43 * The single GEM object described here is actually made up of several
44 * separate areas, as far as the GuC is concerned. The first page (kept
45 * kmap'd) includes the "process decriptor" which holds sequence data for
46 * the doorbell, and one cacheline which actually *is* the doorbell; a
47 * write to this will "ring the doorbell" (i.e. send an interrupt to the
48 * GuC). The subsequent pages of the client object constitute the work
49 * queue (a circular array of work items), again described in the process
50 * descriptor. Work queue pages are mapped momentarily as required.
52 * We also keep a few statistics on failures. Ideally, these should all
54 * no_wq_space: times that the submission pre-check found no space was
55 * available in the work queue (note, the queue is shared,
56 * not per-engine). It is OK for this to be nonzero, but
57 * it should not be huge!
58 * q_fail: failed to enqueue a work item. This should never happen,
59 * because we check for space beforehand.
60 * b_fail: failed to ring the doorbell. This should never happen, unless
61 * somehow the hardware misbehaves, or maybe if the GuC firmware
62 * crashes? We probably need to reset the GPU to recover.
63 * retcode: errno from last guc_submit()
65 struct i915_guc_client {
68 struct i915_gem_context *owner;
69 struct intel_guc *guc;
71 uint32_t engines; /* bitmap of (host) engine ids */
74 uint32_t proc_desc_offset;
76 uint32_t doorbell_offset;
79 uint16_t padding[3]; /* Maintain alignment */
90 /* Per-engine counts of GuC submissions */
91 uint64_t submissions[I915_NUM_ENGINES];
94 enum intel_guc_fw_status {
95 GUC_FIRMWARE_FAIL = -1,
96 GUC_FIRMWARE_NONE = 0,
102 * This structure encapsulates all the data needed during the process
103 * of fetching, caching, and loading the firmware image into the GuC.
105 struct intel_guc_fw {
106 const char * guc_fw_path;
108 struct drm_i915_gem_object * guc_fw_obj;
109 enum intel_guc_fw_status guc_fw_fetch_status;
110 enum intel_guc_fw_status guc_fw_load_status;
112 uint16_t guc_fw_major_wanted;
113 uint16_t guc_fw_minor_wanted;
114 uint16_t guc_fw_major_found;
115 uint16_t guc_fw_minor_found;
117 uint32_t header_size;
118 uint32_t header_offset;
122 uint32_t ucode_offset;
125 struct intel_guc_log {
127 struct i915_vma *vma;
129 struct workqueue_struct *flush_wq;
130 struct work_struct flush_work;
131 struct rchan *relay_chan;
133 /* logging related stats */
134 u32 capture_miss_count;
135 u32 flush_interrupt_count;
136 u32 prev_overflow_count[GUC_MAX_LOG_BUFFER];
137 u32 total_overflow_count[GUC_MAX_LOG_BUFFER];
138 u32 flush_count[GUC_MAX_LOG_BUFFER];
142 struct intel_guc_fw guc_fw;
143 struct intel_guc_log log;
145 /* GuC2Host interrupt related state */
146 bool interrupts_enabled;
148 struct i915_vma *ads_vma;
149 struct i915_vma *ctx_pool_vma;
152 struct i915_guc_client *execbuf_client;
154 DECLARE_BITMAP(doorbell_bitmap, GUC_MAX_DOORBELLS);
155 uint32_t db_cacheline; /* Cyclic counter mod pagesize */
157 /* Action status & statistics */
158 uint64_t action_count; /* Total commands issued */
159 uint32_t action_cmd; /* Last command word */
160 uint32_t action_status; /* Last return status */
161 uint32_t action_fail; /* Total number of failures */
162 int32_t action_err; /* Last error code */
164 uint64_t submissions[I915_NUM_ENGINES];
165 uint32_t last_seqno[I915_NUM_ENGINES];
167 /* To serialize the Host2GuC actions */
168 struct mutex action_lock;
171 /* intel_guc_loader.c */
172 extern void intel_guc_init(struct drm_device *dev);
173 extern int intel_guc_setup(struct drm_device *dev);
174 extern void intel_guc_fini(struct drm_device *dev);
175 extern const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status);
176 extern int intel_guc_suspend(struct drm_device *dev);
177 extern int intel_guc_resume(struct drm_device *dev);
179 /* i915_guc_submission.c */
180 int i915_guc_submission_init(struct drm_i915_private *dev_priv);
181 int i915_guc_submission_enable(struct drm_i915_private *dev_priv);
182 int i915_guc_wq_reserve(struct drm_i915_gem_request *rq);
183 void i915_guc_wq_unreserve(struct drm_i915_gem_request *request);
184 void i915_guc_submission_disable(struct drm_i915_private *dev_priv);
185 void i915_guc_submission_fini(struct drm_i915_private *dev_priv);
186 void i915_guc_capture_logs(struct drm_i915_private *dev_priv);
187 void i915_guc_flush_logs(struct drm_i915_private *dev_priv);
188 void i915_guc_register(struct drm_i915_private *dev_priv);
189 void i915_guc_unregister(struct drm_i915_private *dev_priv);
190 int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val);