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27 #include "intel_guc_fwif.h"
28 #include "i915_guc_reg.h"
29 #include "intel_ringbuffer.h"
33 struct drm_i915_gem_request;
36 * This structure primarily describes the GEM object shared with the GuC.
37 * The specs sometimes refer to this object as a "GuC context", but we use
38 * the term "client" to avoid confusion with hardware contexts. This
39 * GEM object is held for the entire lifetime of our interaction with
40 * the GuC, being allocated before the GuC is loaded with its firmware.
41 * Because there's no way to update the address used by the GuC after
42 * initialisation, the shared object must stay pinned into the GGTT as
43 * long as the GuC is in use. We also keep the first page (only) mapped
44 * into kernel address space, as it includes shared data that must be
45 * updated on every request submission.
47 * The single GEM object described here is actually made up of several
48 * separate areas, as far as the GuC is concerned. The first page (kept
49 * kmap'd) includes the "process descriptor" which holds sequence data for
50 * the doorbell, and one cacheline which actually *is* the doorbell; a
51 * write to this will "ring the doorbell" (i.e. send an interrupt to the
52 * GuC). The subsequent pages of the client object constitute the work
53 * queue (a circular array of work items), again described in the process
54 * descriptor. Work queue pages are mapped momentarily as required.
56 * We also keep a few statistics on failures. Ideally, these should all
58 * no_wq_space: times that the submission pre-check found no space was
59 * available in the work queue (note, the queue is shared,
60 * not per-engine). It is OK for this to be nonzero, but
61 * it should not be huge!
62 * q_fail: failed to enqueue a work item. This should never happen,
63 * because we check for space beforehand.
64 * b_fail: failed to ring the doorbell. This should never happen, unless
65 * somehow the hardware misbehaves, or maybe if the GuC firmware
66 * crashes? We probably need to reset the GPU to recover.
67 * retcode: errno from last guc_submit()
69 struct i915_guc_client {
72 struct i915_gem_context *owner;
73 struct intel_guc *guc;
75 uint32_t engines; /* bitmap of (host) engine ids */
78 uint32_t proc_desc_offset;
81 unsigned long doorbell_offset;
93 /* Per-engine counts of GuC submissions */
94 uint64_t submissions[I915_NUM_ENGINES];
97 enum intel_uc_fw_status {
98 INTEL_UC_FIRMWARE_FAIL = -1,
99 INTEL_UC_FIRMWARE_NONE = 0,
100 INTEL_UC_FIRMWARE_PENDING,
101 INTEL_UC_FIRMWARE_SUCCESS
104 /* User-friendly representation of an enum */
106 const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status)
109 case INTEL_UC_FIRMWARE_FAIL:
111 case INTEL_UC_FIRMWARE_NONE:
113 case INTEL_UC_FIRMWARE_PENDING:
115 case INTEL_UC_FIRMWARE_SUCCESS:
121 enum intel_uc_fw_type {
122 INTEL_UC_FW_TYPE_GUC,
126 /* User-friendly representation of an enum */
127 static inline const char *intel_uc_fw_type_repr(enum intel_uc_fw_type type)
130 case INTEL_UC_FW_TYPE_GUC:
132 case INTEL_UC_FW_TYPE_HUC:
139 * This structure encapsulates all the data needed during the process
140 * of fetching, caching, and loading the firmware image into the GuC.
145 struct drm_i915_gem_object *obj;
146 enum intel_uc_fw_status fetch_status;
147 enum intel_uc_fw_status load_status;
149 uint16_t major_ver_wanted;
150 uint16_t minor_ver_wanted;
151 uint16_t major_ver_found;
152 uint16_t minor_ver_found;
154 enum intel_uc_fw_type type;
155 uint32_t header_size;
156 uint32_t header_offset;
160 uint32_t ucode_offset;
163 struct intel_guc_log {
165 struct i915_vma *vma;
166 /* The runtime stuff gets created only when GuC logging gets enabled */
169 struct workqueue_struct *flush_wq;
170 struct work_struct flush_work;
171 struct rchan *relay_chan;
173 /* logging related stats */
174 u32 capture_miss_count;
175 u32 flush_interrupt_count;
176 u32 prev_overflow_count[GUC_MAX_LOG_BUFFER];
177 u32 total_overflow_count[GUC_MAX_LOG_BUFFER];
178 u32 flush_count[GUC_MAX_LOG_BUFFER];
182 struct intel_uc_fw fw;
183 struct intel_guc_log log;
185 /* intel_guc_recv interrupt related state */
186 bool interrupts_enabled;
188 struct i915_vma *ads_vma;
189 struct i915_vma *stage_desc_pool;
190 void *stage_desc_pool_vaddr;
191 struct ida stage_ids;
193 struct i915_guc_client *execbuf_client;
195 DECLARE_BITMAP(doorbell_bitmap, GUC_NUM_DOORBELLS);
196 uint32_t db_cacheline; /* Cyclic counter mod pagesize */
198 /* Action status & statistics */
199 uint64_t action_count; /* Total commands issued */
200 uint32_t action_cmd; /* Last command word */
201 uint32_t action_status; /* Last return status */
202 uint32_t action_fail; /* Total number of failures */
203 int32_t action_err; /* Last error code */
205 uint64_t submissions[I915_NUM_ENGINES];
206 uint32_t last_seqno[I915_NUM_ENGINES];
208 /* To serialize the intel_guc_send actions */
209 struct mutex send_mutex;
211 /* GuC's FW specific send function */
212 int (*send)(struct intel_guc *guc, const u32 *data, u32 len);
216 /* Generic uC firmware management */
217 struct intel_uc_fw fw;
219 /* HuC-specific additions */
223 void intel_uc_sanitize_options(struct drm_i915_private *dev_priv);
224 void intel_uc_init_early(struct drm_i915_private *dev_priv);
225 void intel_uc_init_fw(struct drm_i915_private *dev_priv);
226 void intel_uc_fini_fw(struct drm_i915_private *dev_priv);
227 int intel_uc_init_hw(struct drm_i915_private *dev_priv);
228 void intel_uc_fini_hw(struct drm_i915_private *dev_priv);
229 int intel_guc_sample_forcewake(struct intel_guc *guc);
230 int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len);
231 static inline int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len)
233 return guc->send(guc, action, len);
236 /* intel_guc_loader.c */
237 int intel_guc_select_fw(struct intel_guc *guc);
238 int intel_guc_init_hw(struct intel_guc *guc);
239 int intel_guc_suspend(struct drm_i915_private *dev_priv);
240 int intel_guc_resume(struct drm_i915_private *dev_priv);
241 u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv);
243 /* i915_guc_submission.c */
244 int i915_guc_submission_init(struct drm_i915_private *dev_priv);
245 int i915_guc_submission_enable(struct drm_i915_private *dev_priv);
246 int i915_guc_wq_reserve(struct drm_i915_gem_request *rq);
247 void i915_guc_wq_unreserve(struct drm_i915_gem_request *request);
248 void i915_guc_submission_disable(struct drm_i915_private *dev_priv);
249 void i915_guc_submission_fini(struct drm_i915_private *dev_priv);
250 struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);
252 /* intel_guc_log.c */
253 int intel_guc_log_create(struct intel_guc *guc);
254 void intel_guc_log_destroy(struct intel_guc *guc);
255 int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val);
256 void i915_guc_log_register(struct drm_i915_private *dev_priv);
257 void i915_guc_log_unregister(struct drm_i915_private *dev_priv);
259 static inline u32 guc_ggtt_offset(struct i915_vma *vma)
261 u32 offset = i915_ggtt_offset(vma);
262 GEM_BUG_ON(offset < GUC_WOPCM_TOP);
263 GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, GUC_GGTT_TOP));
268 void intel_huc_select_fw(struct intel_huc *huc);
269 int intel_huc_init_hw(struct intel_huc *huc);
270 void intel_guc_auth_huc(struct drm_i915_private *dev_priv);