drivers/gpu/drm/i915/intel_uncore.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "i915_drv.h"
  25 #include "intel_drv.h"
  26 #include "i915_vgpu.h"
  27
  28 #include <linux/pm_runtime.h>
  29
  30 #define FORCEWAKE_ACK_TIMEOUT_MS 50
  31
  32 #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32((dev_priv__), (reg__))
  33
  34 static const char * const forcewake_domain_names[] = {
  35         "render",
  36         "blitter",
  37         "media",
  38 };
  39
  40 const char *
  41 intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id)
  42 {
  43         BUILD_BUG_ON(ARRAY_SIZE(forcewake_domain_names) != FW_DOMAIN_ID_COUNT);
  44
  45         if (id >= 0 && id < FW_DOMAIN_ID_COUNT)
  46                 return forcewake_domain_names[id];
  47
  48         WARN_ON(id);
  49
  50         return "unknown";
  51 }
  52
  53 static inline void
  54 fw_domain_reset(const struct intel_uncore_forcewake_domain *d)
  55 {
  56         WARN_ON(!i915_mmio_reg_valid(d->reg_set));
  57         __raw_i915_write32(d->i915, d->reg_set, d->val_reset);
  58 }
  59
  60 static inline void
  61 fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d)
  62 {
  63         d->wake_count++;
  64         hrtimer_start_range_ns(&d->timer,
  65                                ktime_set(0, NSEC_PER_MSEC),
  66                                NSEC_PER_MSEC,
  67                                HRTIMER_MODE_REL);
  68 }
  69
  70 static inline void
  71 fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d)
  72 {
  73         if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) &
  74                              FORCEWAKE_KERNEL) == 0,
  75                             FORCEWAKE_ACK_TIMEOUT_MS))
  76                 DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n",
  77                           intel_uncore_forcewake_domain_to_str(d->id));
  78 }
  79
  80 static inline void
  81 fw_domain_get(const struct intel_uncore_forcewake_domain *d)
  82 {
  83         __raw_i915_write32(d->i915, d->reg_set, d->val_set);
  84 }
  85
  86 static inline void
  87 fw_domain_wait_ack(const struct intel_uncore_forcewake_domain *d)
  88 {
  89         if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) &
  90                              FORCEWAKE_KERNEL),
  91                             FORCEWAKE_ACK_TIMEOUT_MS))
  92                 DRM_ERROR("%s: timed out waiting for forcewake ack request.\n",
  93                           intel_uncore_forcewake_domain_to_str(d->id));
  94 }
  95
  96 static inline void
  97 fw_domain_put(const struct intel_uncore_forcewake_domain *d)
  98 {
  99         __raw_i915_write32(d->i915, d->reg_set, d->val_clear);
 100 }
 101
 102 static inline void
 103 fw_domain_posting_read(const struct intel_uncore_forcewake_domain *d)
 104 {
 105         /* something from same cacheline, but not from the set register */
 106         if (i915_mmio_reg_valid(d->reg_post))
 107                 __raw_posting_read(d->i915, d->reg_post);
 108 }
 109
 110 static void
 111 fw_domains_get(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
 112 {
 113         struct intel_uncore_forcewake_domain *d;
 114
 115         for_each_fw_domain_masked(d, fw_domains, dev_priv) {
 116                 fw_domain_wait_ack_clear(d);
 117                 fw_domain_get(d);
 118         }
 119
 120         for_each_fw_domain_masked(d, fw_domains, dev_priv)
 121                 fw_domain_wait_ack(d);
 122 }
 123
 124 static void
 125 fw_domains_put(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
 126 {
 127         struct intel_uncore_forcewake_domain *d;
 128
 129         for_each_fw_domain_masked(d, fw_domains, dev_priv) {
 130                 fw_domain_put(d);
 131                 fw_domain_posting_read(d);
 132         }
 133 }
 134
 135 static void
 136 fw_domains_posting_read(struct drm_i915_private *dev_priv)
 137 {
 138         struct intel_uncore_forcewake_domain *d;
 139
 140         /* No need to do for all, just do for first found */
 141         for_each_fw_domain(d, dev_priv) {
 142                 fw_domain_posting_read(d);
 143                 break;
 144         }
 145 }
 146
 147 static void
 148 fw_domains_reset(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
 149 {
 150         struct intel_uncore_forcewake_domain *d;
 151
 152         if (dev_priv->uncore.fw_domains == 0)
 153                 return;
 154
 155         for_each_fw_domain_masked(d, fw_domains, dev_priv)
 156                 fw_domain_reset(d);
 157
 158         fw_domains_posting_read(dev_priv);
 159 }
 160
 161 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
 162 {
 163         /* w/a for a sporadic read returning 0 by waiting for the GT
 164          * thread to wake up.
 165          */
 166         if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) &
 167                                 GEN6_GT_THREAD_STATUS_CORE_MASK) == 0, 500))
 168                 DRM_ERROR("GT thread status wait timed out\n");
 169 }
 170
 171 static void fw_domains_get_with_thread_status(struct drm_i915_private *dev_priv,
 172                                               enum forcewake_domains fw_domains)
 173 {
 174         fw_domains_get(dev_priv, fw_domains);
 175
 176         /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */
 177         __gen6_gt_wait_for_thread_c0(dev_priv);
 178 }
 179
 180 static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
 181 {
 182         u32 gtfifodbg;
 183
 184         gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG);
 185         if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg))
 186                 __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg);
 187 }
 188
 189 static void fw_domains_put_with_fifo(struct drm_i915_private *dev_priv,
 190                                      enum forcewake_domains fw_domains)
 191 {
 192         fw_domains_put(dev_priv, fw_domains);
 193         gen6_gt_check_fifodbg(dev_priv);
 194 }
 195
 196 static inline u32 fifo_free_entries(struct drm_i915_private *dev_priv)
 197 {
 198         u32 count = __raw_i915_read32(dev_priv, GTFIFOCTL);
 199
 200         return count & GT_FIFO_FREE_ENTRIES_MASK;
 201 }
 202
 203 static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
 204 {
 205         int ret = 0;
 206
 207         /* On VLV, FIFO will be shared by both SW and HW.
 208          * So, we need to read the FREE_ENTRIES everytime */
 209         if (IS_VALLEYVIEW(dev_priv))
 210                 dev_priv->uncore.fifo_count = fifo_free_entries(dev_priv);
 211
 212         if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
 213                 int loop = 500;
 214                 u32 fifo = fifo_free_entries(dev_priv);
 215
 216                 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
 217                         udelay(10);
 218                         fifo = fifo_free_entries(dev_priv);
 219                 }
 220                 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
 221                         ++ret;
 222                 dev_priv->uncore.fifo_count = fifo;
 223         }
 224         dev_priv->uncore.fifo_count--;
 225
 226         return ret;
 227 }
 228
 229 static enum hrtimer_restart
 230 intel_uncore_fw_release_timer(struct hrtimer *timer)
 231 {
 232         struct intel_uncore_forcewake_domain *domain =
 233                container_of(timer, struct intel_uncore_forcewake_domain, timer);
 234         unsigned long irqflags;
 235
 236         assert_rpm_device_not_suspended(domain->i915);
 237
 238         spin_lock_irqsave(&domain->i915->uncore.lock, irqflags);
 239         if (WARN_ON(domain->wake_count == 0))
 240                 domain->wake_count++;
 241
 242         if (--domain->wake_count == 0)
 243                 domain->i915->uncore.funcs.force_wake_put(domain->i915,
 244                                                           1 << domain->id);
 245
 246         spin_unlock_irqrestore(&domain->i915->uncore.lock, irqflags);
 247
 248         return HRTIMER_NORESTART;
 249 }
 250
 251 void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore)
 252 {
 253         struct drm_i915_private *dev_priv = dev->dev_private;
 254         unsigned long irqflags;
 255         struct intel_uncore_forcewake_domain *domain;
 256         int retry_count = 100;
 257         enum forcewake_domains fw = 0, active_domains;
 258
 259         /* Hold uncore.lock across reset to prevent any register access
 260          * with forcewake not set correctly. Wait until all pending
 261          * timers are run before holding.
 262          */
 263         while (1) {
 264                 active_domains = 0;
 265
 266                 for_each_fw_domain(domain, dev_priv) {
 267                         if (hrtimer_cancel(&domain->timer) == 0)
 268                                 continue;
 269
 270                         intel_uncore_fw_release_timer(&domain->timer);
 271                 }
 272
 273                 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 274
 275                 for_each_fw_domain(domain, dev_priv) {
 276                         if (hrtimer_active(&domain->timer))
 277                                 active_domains |= domain->mask;
 278                 }
 279
 280                 if (active_domains == 0)
 281                         break;
 282
 283                 if (--retry_count == 0) {
 284                         DRM_ERROR("Timed out waiting for forcewake timers to finish\n");
 285                         break;
 286                 }
 287
 288                 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 289                 cond_resched();
 290         }
 291
 292         WARN_ON(active_domains);
 293
 294         for_each_fw_domain(domain, dev_priv)
 295                 if (domain->wake_count)
 296                         fw |= domain->mask;
 297
 298         if (fw)
 299                 dev_priv->uncore.funcs.force_wake_put(dev_priv, fw);
 300
 301         fw_domains_reset(dev_priv, FORCEWAKE_ALL);
 302
 303         if (restore) { /* If reset with a user forcewake, try to restore */
 304                 if (fw)
 305                         dev_priv->uncore.funcs.force_wake_get(dev_priv, fw);
 306
 307                 if (IS_GEN6(dev) || IS_GEN7(dev))
 308                         dev_priv->uncore.fifo_count =
 309                                 fifo_free_entries(dev_priv);
 310         }
 311
 312         if (!restore)
 313                 assert_forcewakes_inactive(dev_priv);
 314
 315         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 316 }
 317
 318 static void intel_uncore_ellc_detect(struct drm_device *dev)
 319 {
 320         struct drm_i915_private *dev_priv = dev->dev_private;
 321
 322         if ((IS_HASWELL(dev) || IS_BROADWELL(dev) ||
 323              INTEL_INFO(dev)->gen >= 9) &&
 324             (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) & EDRAM_ENABLED)) {
 325                 /* The docs do not explain exactly how the calculation can be
 326                  * made. It is somewhat guessable, but for now, it's always
 327                  * 128MB.
 328                  * NB: We can't write IDICR yet because we do not have gt funcs
 329                  * set up */
 330                 dev_priv->ellc_size = 128;
 331                 DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size);
 332         }
 333 }
 334
 335 static bool
 336 fpga_check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
 337 {
 338         u32 dbg;
 339
 340         dbg = __raw_i915_read32(dev_priv, FPGA_DBG);
 341         if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM)))
 342                 return false;
 343
 344         __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 345
 346         return true;
 347 }
 348
 349 static bool
 350 vlv_check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
 351 {
 352         u32 cer;
 353
 354         cer = __raw_i915_read32(dev_priv, CLAIM_ER);
 355         if (likely(!(cer & (CLAIM_ER_OVERFLOW | CLAIM_ER_CTR_MASK))))
 356                 return false;
 357
 358         __raw_i915_write32(dev_priv, CLAIM_ER, CLAIM_ER_CLR);
 359
 360         return true;
 361 }
 362
 363 static bool
 364 check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
 365 {
 366         if (HAS_FPGA_DBG_UNCLAIMED(dev_priv))
 367                 return fpga_check_for_unclaimed_mmio(dev_priv);
 368
 369         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 370                 return vlv_check_for_unclaimed_mmio(dev_priv);
 371
 372         return false;
 373 }
 374
 375 static void __intel_uncore_early_sanitize(struct drm_device *dev,
 376                                           bool restore_forcewake)
 377 {
 378         struct drm_i915_private *dev_priv = dev->dev_private;
 379
 380         /* clear out unclaimed reg detection bit */
 381         if (check_for_unclaimed_mmio(dev_priv))
 382                 DRM_DEBUG("unclaimed mmio detected on uncore init, clearing\n");
 383
 384         /* clear out old GT FIFO errors */
 385         if (IS_GEN6(dev) || IS_GEN7(dev))
 386                 __raw_i915_write32(dev_priv, GTFIFODBG,
 387                                    __raw_i915_read32(dev_priv, GTFIFODBG));
 388
 389         /* WaDisableShadowRegForCpd:chv */
 390         if (IS_CHERRYVIEW(dev)) {
 391                 __raw_i915_write32(dev_priv, GTFIFOCTL,
 392                                    __raw_i915_read32(dev_priv, GTFIFOCTL) |
 393                                    GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
 394                                    GT_FIFO_CTL_RC6_POLICY_STALL);
 395         }
 396
 397         intel_uncore_forcewake_reset(dev, restore_forcewake);
 398 }
 399
 400 void intel_uncore_early_sanitize(struct drm_device *dev, bool restore_forcewake)
 401 {
 402         __intel_uncore_early_sanitize(dev, restore_forcewake);
 403         i915_check_and_clear_faults(dev);
 404 }
 405
 406 void intel_uncore_sanitize(struct drm_device *dev)
 407 {
 408         i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
 409
 410         /* BIOS often leaves RC6 enabled, but disable it for hw init */
 411         intel_disable_gt_powersave(dev);
 412 }
 413
 414 static void __intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
 415                                          enum forcewake_domains fw_domains)
 416 {
 417         struct intel_uncore_forcewake_domain *domain;
 418
 419         if (!dev_priv->uncore.funcs.force_wake_get)
 420                 return;
 421
 422         fw_domains &= dev_priv->uncore.fw_domains;
 423
 424         for_each_fw_domain_masked(domain, fw_domains, dev_priv) {
 425                 if (domain->wake_count++)
 426                         fw_domains &= ~domain->mask;
 427         }
 428
 429         if (fw_domains)
 430                 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
 431 }
 432
 433 /**
 434  * intel_uncore_forcewake_get - grab forcewake domain references
 435  * @dev_priv: i915 device instance
 436  * @fw_domains: forcewake domains to get reference on
 437  *
 438  * This function can be used get GT's forcewake domain references.
 439  * Normal register access will handle the forcewake domains automatically.
 440  * However if some sequence requires the GT to not power down a particular
 441  * forcewake domains this function should be called at the beginning of the
 442  * sequence. And subsequently the reference should be dropped by symmetric
 443  * call to intel_unforce_forcewake_put(). Usually caller wants all the domains
 444  * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL.
 445  */
 446 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
 447                                 enum forcewake_domains fw_domains)
 448 {
 449         unsigned long irqflags;
 450
 451         if (!dev_priv->uncore.funcs.force_wake_get)
 452                 return;
 453
 454         assert_rpm_wakelock_held(dev_priv);
 455
 456         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 457         __intel_uncore_forcewake_get(dev_priv, fw_domains);
 458         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 459 }
 460
 461 /**
 462  * intel_uncore_forcewake_get__locked - grab forcewake domain references
 463  * @dev_priv: i915 device instance
 464  * @fw_domains: forcewake domains to get reference on
 465  *
 466  * See intel_uncore_forcewake_get(). This variant places the onus
 467  * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
 468  */
 469 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
 470                                         enum forcewake_domains fw_domains)
 471 {
 472         assert_spin_locked(&dev_priv->uncore.lock);
 473
 474         if (!dev_priv->uncore.funcs.force_wake_get)
 475                 return;
 476
 477         __intel_uncore_forcewake_get(dev_priv, fw_domains);
 478 }
 479
 480 static void __intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
 481                                          enum forcewake_domains fw_domains)
 482 {
 483         struct intel_uncore_forcewake_domain *domain;
 484
 485         if (!dev_priv->uncore.funcs.force_wake_put)
 486                 return;
 487
 488         fw_domains &= dev_priv->uncore.fw_domains;
 489
 490         for_each_fw_domain_masked(domain, fw_domains, dev_priv) {
 491                 if (WARN_ON(domain->wake_count == 0))
 492                         continue;
 493
 494                 if (--domain->wake_count)
 495                         continue;
 496
 497                 fw_domain_arm_timer(domain);
 498         }
 499 }
 500
 501 /**
 502  * intel_uncore_forcewake_put - release a forcewake domain reference
 503  * @dev_priv: i915 device instance
 504  * @fw_domains: forcewake domains to put references
 505  *
 506  * This function drops the device-level forcewakes for specified
 507  * domains obtained by intel_uncore_forcewake_get().
 508  */
 509 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
 510                                 enum forcewake_domains fw_domains)
 511 {
 512         unsigned long irqflags;
 513
 514         if (!dev_priv->uncore.funcs.force_wake_put)
 515                 return;
 516
 517         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 518         __intel_uncore_forcewake_put(dev_priv, fw_domains);
 519         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 520 }
 521
 522 /**
 523  * intel_uncore_forcewake_put__locked - grab forcewake domain references
 524  * @dev_priv: i915 device instance
 525  * @fw_domains: forcewake domains to get reference on
 526  *
 527  * See intel_uncore_forcewake_put(). This variant places the onus
 528  * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
 529  */
 530 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
 531                                         enum forcewake_domains fw_domains)
 532 {
 533         assert_spin_locked(&dev_priv->uncore.lock);
 534
 535         if (!dev_priv->uncore.funcs.force_wake_put)
 536                 return;
 537
 538         __intel_uncore_forcewake_put(dev_priv, fw_domains);
 539 }
 540
 541 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv)
 542 {
 543         struct intel_uncore_forcewake_domain *domain;
 544
 545         if (!dev_priv->uncore.funcs.force_wake_get)
 546                 return;
 547
 548         for_each_fw_domain(domain, dev_priv)
 549                 WARN_ON(domain->wake_count);
 550 }
 551
 552 /* We give fast paths for the really cool registers */
 553 #define NEEDS_FORCE_WAKE(reg) ((reg) < 0x40000)
 554
 555 #define __gen6_reg_read_fw_domains(offset) \
 556 ({ \
 557         enum forcewake_domains __fwd; \
 558         if (NEEDS_FORCE_WAKE(offset)) \
 559                 __fwd = FORCEWAKE_RENDER; \
 560         else \
 561                 __fwd = 0; \
 562         __fwd; \
 563 })
 564
 565 #define REG_RANGE(reg, start, end) ((reg) >= (start) && (reg) < (end))
 566
 567 #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \
 568         (REG_RANGE((reg), 0x2000, 0x4000) || \
 569          REG_RANGE((reg), 0x5000, 0x8000) || \
 570          REG_RANGE((reg), 0xB000, 0x12000) || \
 571          REG_RANGE((reg), 0x2E000, 0x30000))
 572
 573 #define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg) \
 574         (REG_RANGE((reg), 0x12000, 0x14000) || \
 575          REG_RANGE((reg), 0x22000, 0x24000) || \
 576          REG_RANGE((reg), 0x30000, 0x40000))
 577
 578 #define __vlv_reg_read_fw_domains(offset) \
 579 ({ \
 580         enum forcewake_domains __fwd = 0; \
 581         if (!NEEDS_FORCE_WAKE(offset)) \
 582                 __fwd = 0; \
 583         else if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(offset)) \
 584                 __fwd = FORCEWAKE_RENDER; \
 585         else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(offset)) \
 586                 __fwd = FORCEWAKE_MEDIA; \
 587         __fwd; \
 588 })
 589
 590 static const i915_reg_t gen8_shadowed_regs[] = {
 591         GEN6_RPNSWREQ,
 592         GEN6_RC_VIDEO_FREQ,
 593         RING_TAIL(RENDER_RING_BASE),
 594         RING_TAIL(GEN6_BSD_RING_BASE),
 595         RING_TAIL(VEBOX_RING_BASE),
 596         RING_TAIL(BLT_RING_BASE),
 597         /* TODO: Other registers are not yet used */
 598 };
 599
 600 static bool is_gen8_shadowed(u32 offset)
 601 {
 602         int i;
 603         for (i = 0; i < ARRAY_SIZE(gen8_shadowed_regs); i++)
 604                 if (offset == gen8_shadowed_regs[i].reg)
 605                         return true;
 606
 607         return false;
 608 }
 609
 610 #define __gen8_reg_write_fw_domains(offset) \
 611 ({ \
 612         enum forcewake_domains __fwd; \
 613         if (NEEDS_FORCE_WAKE(offset) && !is_gen8_shadowed(offset)) \
 614                 __fwd = FORCEWAKE_RENDER; \
 615         else \
 616                 __fwd = 0; \
 617         __fwd; \
 618 })
 619
 620 #define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \
 621         (REG_RANGE((reg), 0x2000, 0x4000) || \
 622          REG_RANGE((reg), 0x5200, 0x8000) || \
 623          REG_RANGE((reg), 0x8300, 0x8500) || \
 624          REG_RANGE((reg), 0xB000, 0xB480) || \
 625          REG_RANGE((reg), 0xE000, 0xE800))
 626
 627 #define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg) \
 628         (REG_RANGE((reg), 0x8800, 0x8900) || \
 629          REG_RANGE((reg), 0xD000, 0xD800) || \
 630          REG_RANGE((reg), 0x12000, 0x14000) || \
 631          REG_RANGE((reg), 0x1A000, 0x1C000) || \
 632          REG_RANGE((reg), 0x1E800, 0x1EA00) || \
 633          REG_RANGE((reg), 0x30000, 0x38000))
 634
 635 #define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg) \
 636         (REG_RANGE((reg), 0x4000, 0x5000) || \
 637          REG_RANGE((reg), 0x8000, 0x8300) || \
 638          REG_RANGE((reg), 0x8500, 0x8600) || \
 639          REG_RANGE((reg), 0x9000, 0xB000) || \
 640          REG_RANGE((reg), 0xF000, 0x10000))
 641
 642 #define __chv_reg_read_fw_domains(offset) \
 643 ({ \
 644         enum forcewake_domains __fwd = 0; \
 645         if (!NEEDS_FORCE_WAKE(offset)) \
 646                 __fwd = 0; \
 647         else if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(offset)) \
 648                 __fwd = FORCEWAKE_RENDER; \
 649         else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(offset)) \
 650                 __fwd = FORCEWAKE_MEDIA; \
 651         else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(offset)) \
 652                 __fwd = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
 653         __fwd; \
 654 })
 655
 656 #define __chv_reg_write_fw_domains(offset) \
 657 ({ \
 658         enum forcewake_domains __fwd = 0; \
 659         if (!NEEDS_FORCE_WAKE(offset) || is_gen8_shadowed(offset)) \
 660                 __fwd = 0; \
 661         else if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(offset)) \
 662                 __fwd = FORCEWAKE_RENDER; \
 663         else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(offset)) \
 664                 __fwd = FORCEWAKE_MEDIA; \
 665         else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(offset)) \
 666                 __fwd = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
 667         __fwd; \
 668 })
 669
 670 #define FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) \
 671         REG_RANGE((reg), 0xB00,  0x2000)
 672
 673 #define FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) \
 674         (REG_RANGE((reg), 0x2000, 0x2700) || \
 675          REG_RANGE((reg), 0x3000, 0x4000) || \
 676          REG_RANGE((reg), 0x5200, 0x8000) || \
 677          REG_RANGE((reg), 0x8140, 0x8160) || \
 678          REG_RANGE((reg), 0x8300, 0x8500) || \
 679          REG_RANGE((reg), 0x8C00, 0x8D00) || \
 680          REG_RANGE((reg), 0xB000, 0xB480) || \
 681          REG_RANGE((reg), 0xE000, 0xE900) || \
 682          REG_RANGE((reg), 0x24400, 0x24800))
 683
 684 #define FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) \
 685         (REG_RANGE((reg), 0x8130, 0x8140) || \
 686          REG_RANGE((reg), 0x8800, 0x8A00) || \
 687          REG_RANGE((reg), 0xD000, 0xD800) || \
 688          REG_RANGE((reg), 0x12000, 0x14000) || \
 689          REG_RANGE((reg), 0x1A000, 0x1EA00) || \
 690          REG_RANGE((reg), 0x30000, 0x40000))
 691
 692 #define FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg) \
 693         REG_RANGE((reg), 0x9400, 0x9800)
 694
 695 #define FORCEWAKE_GEN9_BLITTER_RANGE_OFFSET(reg) \
 696         ((reg) < 0x40000 && \
 697          !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) && \
 698          !FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) && \
 699          !FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) && \
 700          !FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg))
 701
 702 #define SKL_NEEDS_FORCE_WAKE(reg) \
 703         ((reg) < 0x40000 && !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg))
 704
 705 #define __gen9_reg_read_fw_domains(offset) \
 706 ({ \
 707         enum forcewake_domains __fwd; \
 708         if (!SKL_NEEDS_FORCE_WAKE(offset)) \
 709                 __fwd = 0; \
 710         else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(offset)) \
 711                 __fwd = FORCEWAKE_RENDER; \
 712         else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(offset)) \
 713                 __fwd = FORCEWAKE_MEDIA; \
 714         else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(offset)) \
 715                 __fwd = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
 716         else \
 717                 __fwd = FORCEWAKE_BLITTER; \
 718         __fwd; \
 719 })
 720
 721 static const i915_reg_t gen9_shadowed_regs[] = {
 722         RING_TAIL(RENDER_RING_BASE),
 723         RING_TAIL(GEN6_BSD_RING_BASE),
 724         RING_TAIL(VEBOX_RING_BASE),
 725         RING_TAIL(BLT_RING_BASE),
 726         GEN6_RPNSWREQ,
 727         GEN6_RC_VIDEO_FREQ,
 728         /* TODO: Other registers are not yet used */
 729 };
 730
 731 static bool is_gen9_shadowed(u32 offset)
 732 {
 733         int i;
 734         for (i = 0; i < ARRAY_SIZE(gen9_shadowed_regs); i++)
 735                 if (offset == gen9_shadowed_regs[i].reg)
 736                         return true;
 737
 738         return false;
 739 }
 740
 741 #define __gen9_reg_write_fw_domains(offset) \
 742 ({ \
 743         enum forcewake_domains __fwd; \
 744         if (!SKL_NEEDS_FORCE_WAKE(offset) || is_gen9_shadowed(offset)) \
 745                 __fwd = 0; \
 746         else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(offset)) \
 747                 __fwd = FORCEWAKE_RENDER; \
 748         else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(offset)) \
 749                 __fwd = FORCEWAKE_MEDIA; \
 750         else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(offset)) \
 751                 __fwd = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
 752         else \
 753                 __fwd = FORCEWAKE_BLITTER; \
 754         __fwd; \
 755 })
 756
 757 static void
 758 ilk_dummy_write(struct drm_i915_private *dev_priv)
 759 {
 760         /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
 761          * the chip from rc6 before touching it for real. MI_MODE is masked,
 762          * hence harmless to write 0 into. */
 763         __raw_i915_write32(dev_priv, MI_MODE, 0);
 764 }
 765
 766 static void
 767 __unclaimed_reg_debug(struct drm_i915_private *dev_priv,
 768                       const i915_reg_t reg,
 769                       const bool read,
 770                       const bool before)
 771 {
 772         /* XXX. We limit the auto arming traces for mmio
 773          * debugs on these platforms. There are just too many
 774          * revealed by these and CI/Bat suffers from the noise.
 775          * Please fix and then re-enable the automatic traces.
 776          */
 777         if (i915.mmio_debug < 2 &&
 778             (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 779                 return;
 780
 781         if (WARN(check_for_unclaimed_mmio(dev_priv),
 782                  "Unclaimed register detected %s %s register 0x%x\n",
 783                  before ? "before" : "after",
 784                  read ? "reading" : "writing to",
 785                  i915_mmio_reg_offset(reg)))
 786                 i915.mmio_debug--; /* Only report the first N failures */
 787 }
 788
 789 static inline void
 790 unclaimed_reg_debug(struct drm_i915_private *dev_priv,
 791                     const i915_reg_t reg,
 792                     const bool read,
 793                     const bool before)
 794 {
 795         if (likely(!i915.mmio_debug))
 796                 return;
 797
 798         __unclaimed_reg_debug(dev_priv, reg, read, before);
 799 }
 800
 801 #define GEN2_READ_HEADER(x) \
 802         u##x val = 0; \
 803         assert_rpm_wakelock_held(dev_priv);
 804
 805 #define GEN2_READ_FOOTER \
 806         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
 807         return val
 808
 809 #define __gen2_read(x) \
 810 static u##x \
 811 gen2_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 812         GEN2_READ_HEADER(x); \
 813         val = __raw_i915_read##x(dev_priv, reg); \
 814         GEN2_READ_FOOTER; \
 815 }
 816
 817 #define __gen5_read(x) \
 818 static u##x \
 819 gen5_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 820         GEN2_READ_HEADER(x); \
 821         ilk_dummy_write(dev_priv); \
 822         val = __raw_i915_read##x(dev_priv, reg); \
 823         GEN2_READ_FOOTER; \
 824 }
 825
 826 __gen5_read(8)
 827 __gen5_read(16)
 828 __gen5_read(32)
 829 __gen5_read(64)
 830 __gen2_read(8)
 831 __gen2_read(16)
 832 __gen2_read(32)
 833 __gen2_read(64)
 834
 835 #undef __gen5_read
 836 #undef __gen2_read
 837
 838 #undef GEN2_READ_FOOTER
 839 #undef GEN2_READ_HEADER
 840
 841 #define GEN6_READ_HEADER(x) \
 842         u32 offset = i915_mmio_reg_offset(reg); \
 843         unsigned long irqflags; \
 844         u##x val = 0; \
 845         assert_rpm_wakelock_held(dev_priv); \
 846         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \
 847         unclaimed_reg_debug(dev_priv, reg, true, true)
 848
 849 #define GEN6_READ_FOOTER \
 850         unclaimed_reg_debug(dev_priv, reg, true, false); \
 851         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
 852         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
 853         return val
 854
 855 static inline void __force_wake_auto(struct drm_i915_private *dev_priv,
 856                                      enum forcewake_domains fw_domains)
 857 {
 858         struct intel_uncore_forcewake_domain *domain;
 859
 860         if (WARN_ON(!fw_domains))
 861                 return;
 862
 863         /* Ideally GCC would be constant-fold and eliminate this loop */
 864         for_each_fw_domain_masked(domain, fw_domains, dev_priv) {
 865                 if (domain->wake_count) {
 866                         fw_domains &= ~domain->mask;
 867                         continue;
 868                 }
 869
 870                 fw_domain_arm_timer(domain);
 871         }
 872
 873         if (fw_domains)
 874                 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
 875 }
 876
 877 #define __gen6_read(x) \
 878 static u##x \
 879 gen6_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 880         enum forcewake_domains fw_engine; \
 881         GEN6_READ_HEADER(x); \
 882         fw_engine = __gen6_reg_read_fw_domains(offset); \
 883         if (fw_engine) \
 884                 __force_wake_auto(dev_priv, fw_engine); \
 885         val = __raw_i915_read##x(dev_priv, reg); \
 886         GEN6_READ_FOOTER; \
 887 }
 888
 889 #define __vlv_read(x) \
 890 static u##x \
 891 vlv_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 892         enum forcewake_domains fw_engine; \
 893         GEN6_READ_HEADER(x); \
 894         fw_engine = __vlv_reg_read_fw_domains(offset); \
 895         if (fw_engine) \
 896                 __force_wake_auto(dev_priv, fw_engine); \
 897         val = __raw_i915_read##x(dev_priv, reg); \
 898         GEN6_READ_FOOTER; \
 899 }
 900
 901 #define __chv_read(x) \
 902 static u##x \
 903 chv_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 904         enum forcewake_domains fw_engine; \
 905         GEN6_READ_HEADER(x); \
 906         fw_engine = __chv_reg_read_fw_domains(offset); \
 907         if (fw_engine) \
 908                 __force_wake_auto(dev_priv, fw_engine); \
 909         val = __raw_i915_read##x(dev_priv, reg); \
 910         GEN6_READ_FOOTER; \
 911 }
 912
 913 #define __gen9_read(x) \
 914 static u##x \
 915 gen9_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 916         enum forcewake_domains fw_engine; \
 917         GEN6_READ_HEADER(x); \
 918         fw_engine = __gen9_reg_read_fw_domains(offset); \
 919         if (fw_engine) \
 920                 __force_wake_auto(dev_priv, fw_engine); \
 921         val = __raw_i915_read##x(dev_priv, reg); \
 922         GEN6_READ_FOOTER; \
 923 }
 924
 925 __gen9_read(8)
 926 __gen9_read(16)
 927 __gen9_read(32)
 928 __gen9_read(64)
 929 __chv_read(8)
 930 __chv_read(16)
 931 __chv_read(32)
 932 __chv_read(64)
 933 __vlv_read(8)
 934 __vlv_read(16)
 935 __vlv_read(32)
 936 __vlv_read(64)
 937 __gen6_read(8)
 938 __gen6_read(16)
 939 __gen6_read(32)
 940 __gen6_read(64)
 941
 942 #undef __gen9_read
 943 #undef __chv_read
 944 #undef __vlv_read
 945 #undef __gen6_read
 946 #undef GEN6_READ_FOOTER
 947 #undef GEN6_READ_HEADER
 948
 949 #define VGPU_READ_HEADER(x) \
 950         unsigned long irqflags; \
 951         u##x val = 0; \
 952         assert_rpm_device_not_suspended(dev_priv); \
 953         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
 954
 955 #define VGPU_READ_FOOTER \
 956         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
 957         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
 958         return val
 959
 960 #define __vgpu_read(x) \
 961 static u##x \
 962 vgpu_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 963         VGPU_READ_HEADER(x); \
 964         val = __raw_i915_read##x(dev_priv, reg); \
 965         VGPU_READ_FOOTER; \
 966 }
 967
 968 __vgpu_read(8)
 969 __vgpu_read(16)
 970 __vgpu_read(32)
 971 __vgpu_read(64)
 972
 973 #undef __vgpu_read
 974 #undef VGPU_READ_FOOTER
 975 #undef VGPU_READ_HEADER
 976
 977 #define GEN2_WRITE_HEADER \
 978         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
 979         assert_rpm_wakelock_held(dev_priv); \
 980
 981 #define GEN2_WRITE_FOOTER
 982
 983 #define __gen2_write(x) \
 984 static void \
 985 gen2_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
 986         GEN2_WRITE_HEADER; \
 987         __raw_i915_write##x(dev_priv, reg, val); \
 988         GEN2_WRITE_FOOTER; \
 989 }
 990
 991 #define __gen5_write(x) \
 992 static void \
 993 gen5_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
 994         GEN2_WRITE_HEADER; \
 995         ilk_dummy_write(dev_priv); \
 996         __raw_i915_write##x(dev_priv, reg, val); \
 997         GEN2_WRITE_FOOTER; \
 998 }
 999
1000 __gen5_write(8)
1001 __gen5_write(16)
1002 __gen5_write(32)
1003 __gen5_write(64)
1004 __gen2_write(8)
1005 __gen2_write(16)
1006 __gen2_write(32)
1007 __gen2_write(64)
1008
1009 #undef __gen5_write
1010 #undef __gen2_write
1011
1012 #undef GEN2_WRITE_FOOTER
1013 #undef GEN2_WRITE_HEADER
1014
1015 #define GEN6_WRITE_HEADER \
1016         u32 offset = i915_mmio_reg_offset(reg); \
1017         unsigned long irqflags; \
1018         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1019         assert_rpm_wakelock_held(dev_priv); \
1020         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \
1021         unclaimed_reg_debug(dev_priv, reg, false, true)
1022
1023 #define GEN6_WRITE_FOOTER \
1024         unclaimed_reg_debug(dev_priv, reg, false, false); \
1025         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
1026
1027 #define __gen6_write(x) \
1028 static void \
1029 gen6_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1030         u32 __fifo_ret = 0; \
1031         GEN6_WRITE_HEADER; \
1032         if (NEEDS_FORCE_WAKE(offset)) { \
1033                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1034         } \
1035         __raw_i915_write##x(dev_priv, reg, val); \
1036         if (unlikely(__fifo_ret)) { \
1037                 gen6_gt_check_fifodbg(dev_priv); \
1038         } \
1039         GEN6_WRITE_FOOTER; \
1040 }
1041
1042 #define __hsw_write(x) \
1043 static void \
1044 hsw_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1045         u32 __fifo_ret = 0; \
1046         GEN6_WRITE_HEADER; \
1047         if (NEEDS_FORCE_WAKE(offset)) { \
1048                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1049         } \
1050         __raw_i915_write##x(dev_priv, reg, val); \
1051         if (unlikely(__fifo_ret)) { \
1052                 gen6_gt_check_fifodbg(dev_priv); \
1053         } \
1054         GEN6_WRITE_FOOTER; \
1055 }
1056
1057 #define __gen8_write(x) \
1058 static void \
1059 gen8_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1060         enum forcewake_domains fw_engine; \
1061         GEN6_WRITE_HEADER; \
1062         fw_engine = __gen8_reg_write_fw_domains(offset); \
1063         if (fw_engine) \
1064                 __force_wake_auto(dev_priv, fw_engine); \
1065         __raw_i915_write##x(dev_priv, reg, val); \
1066         GEN6_WRITE_FOOTER; \
1067 }
1068
1069 #define __chv_write(x) \
1070 static void \
1071 chv_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1072         enum forcewake_domains fw_engine; \
1073         GEN6_WRITE_HEADER; \
1074         fw_engine = __chv_reg_write_fw_domains(offset); \
1075         if (fw_engine) \
1076                 __force_wake_auto(dev_priv, fw_engine); \
1077         __raw_i915_write##x(dev_priv, reg, val); \
1078         GEN6_WRITE_FOOTER; \
1079 }
1080
1081 #define __gen9_write(x) \
1082 static void \
1083 gen9_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, \
1084                 bool trace) { \
1085         enum forcewake_domains fw_engine; \
1086         GEN6_WRITE_HEADER; \
1087         fw_engine = __gen9_reg_write_fw_domains(offset); \
1088         if (fw_engine) \
1089                 __force_wake_auto(dev_priv, fw_engine); \
1090         __raw_i915_write##x(dev_priv, reg, val); \
1091         GEN6_WRITE_FOOTER; \
1092 }
1093
1094 __gen9_write(8)
1095 __gen9_write(16)
1096 __gen9_write(32)
1097 __gen9_write(64)
1098 __chv_write(8)
1099 __chv_write(16)
1100 __chv_write(32)
1101 __chv_write(64)
1102 __gen8_write(8)
1103 __gen8_write(16)
1104 __gen8_write(32)
1105 __gen8_write(64)
1106 __hsw_write(8)
1107 __hsw_write(16)
1108 __hsw_write(32)
1109 __hsw_write(64)
1110 __gen6_write(8)
1111 __gen6_write(16)
1112 __gen6_write(32)
1113 __gen6_write(64)
1114
1115 #undef __gen9_write
1116 #undef __chv_write
1117 #undef __gen8_write
1118 #undef __hsw_write
1119 #undef __gen6_write
1120 #undef GEN6_WRITE_FOOTER
1121 #undef GEN6_WRITE_HEADER
1122
1123 #define VGPU_WRITE_HEADER \
1124         unsigned long irqflags; \
1125         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1126         assert_rpm_device_not_suspended(dev_priv); \
1127         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
1128
1129 #define VGPU_WRITE_FOOTER \
1130         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
1131
1132 #define __vgpu_write(x) \
1133 static void vgpu_write##x(struct drm_i915_private *dev_priv, \
1134                           i915_reg_t reg, u##x val, bool trace) { \
1135         VGPU_WRITE_HEADER; \
1136         __raw_i915_write##x(dev_priv, reg, val); \
1137         VGPU_WRITE_FOOTER; \
1138 }
1139
1140 __vgpu_write(8)
1141 __vgpu_write(16)
1142 __vgpu_write(32)
1143 __vgpu_write(64)
1144
1145 #undef __vgpu_write
1146 #undef VGPU_WRITE_FOOTER
1147 #undef VGPU_WRITE_HEADER
1148
1149 #define ASSIGN_WRITE_MMIO_VFUNCS(x) \
1150 do { \
1151         dev_priv->uncore.funcs.mmio_writeb = x##_write8; \
1152         dev_priv->uncore.funcs.mmio_writew = x##_write16; \
1153         dev_priv->uncore.funcs.mmio_writel = x##_write32; \
1154         dev_priv->uncore.funcs.mmio_writeq = x##_write64; \
1155 } while (0)
1156
1157 #define ASSIGN_READ_MMIO_VFUNCS(x) \
1158 do { \
1159         dev_priv->uncore.funcs.mmio_readb = x##_read8; \
1160         dev_priv->uncore.funcs.mmio_readw = x##_read16; \
1161         dev_priv->uncore.funcs.mmio_readl = x##_read32; \
1162         dev_priv->uncore.funcs.mmio_readq = x##_read64; \
1163 } while (0)
1164
1165
1166 static void fw_domain_init(struct drm_i915_private *dev_priv,
1167                            enum forcewake_domain_id domain_id,
1168                            i915_reg_t reg_set,
1169                            i915_reg_t reg_ack)
1170 {
1171         struct intel_uncore_forcewake_domain *d;
1172
1173         if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT))
1174                 return;
1175
1176         d = &dev_priv->uncore.fw_domain[domain_id];
1177
1178         WARN_ON(d->wake_count);
1179
1180         d->wake_count = 0;
1181         d->reg_set = reg_set;
1182         d->reg_ack = reg_ack;
1183
1184         if (IS_GEN6(dev_priv)) {
1185                 d->val_reset = 0;
1186                 d->val_set = FORCEWAKE_KERNEL;
1187                 d->val_clear = 0;
1188         } else {
1189                 /* WaRsClearFWBitsAtReset:bdw,skl */
1190                 d->val_reset = _MASKED_BIT_DISABLE(0xffff);
1191                 d->val_set = _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL);
1192                 d->val_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL);
1193         }
1194
1195         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1196                 d->reg_post = FORCEWAKE_ACK_VLV;
1197         else if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv) || IS_GEN8(dev_priv))
1198                 d->reg_post = ECOBUS;
1199
1200         d->i915 = dev_priv;
1201         d->id = domain_id;
1202
1203         BUILD_BUG_ON(FORCEWAKE_RENDER != (1 << FW_DOMAIN_ID_RENDER));
1204         BUILD_BUG_ON(FORCEWAKE_BLITTER != (1 << FW_DOMAIN_ID_BLITTER));
1205         BUILD_BUG_ON(FORCEWAKE_MEDIA != (1 << FW_DOMAIN_ID_MEDIA));
1206
1207         d->mask = 1 << domain_id;
1208
1209         hrtimer_init(&d->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1210         d->timer.function = intel_uncore_fw_release_timer;
1211
1212         dev_priv->uncore.fw_domains |= (1 << domain_id);
1213
1214         fw_domain_reset(d);
1215 }
1216
1217 static void intel_uncore_fw_domains_init(struct drm_device *dev)
1218 {
1219         struct drm_i915_private *dev_priv = dev->dev_private;
1220
1221         if (INTEL_INFO(dev_priv)->gen <= 5)
1222                 return;
1223
1224         if (IS_GEN9(dev)) {
1225                 dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
1226                 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1227                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1228                                FORCEWAKE_RENDER_GEN9,
1229                                FORCEWAKE_ACK_RENDER_GEN9);
1230                 fw_domain_init(dev_priv, FW_DOMAIN_ID_BLITTER,
1231                                FORCEWAKE_BLITTER_GEN9,
1232                                FORCEWAKE_ACK_BLITTER_GEN9);
1233                 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
1234                                FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
1235         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1236                 dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
1237                 if (!IS_CHERRYVIEW(dev))
1238                         dev_priv->uncore.funcs.force_wake_put =
1239                                 fw_domains_put_with_fifo;
1240                 else
1241                         dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1242                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1243                                FORCEWAKE_VLV, FORCEWAKE_ACK_VLV);
1244                 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
1245                                FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV);
1246         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1247                 dev_priv->uncore.funcs.force_wake_get =
1248                         fw_domains_get_with_thread_status;
1249                 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1250                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1251                                FORCEWAKE_MT, FORCEWAKE_ACK_HSW);
1252         } else if (IS_IVYBRIDGE(dev)) {
1253                 u32 ecobus;
1254
1255                 /* IVB configs may use multi-threaded forcewake */
1256
1257                 /* A small trick here - if the bios hasn't configured
1258                  * MT forcewake, and if the device is in RC6, then
1259                  * force_wake_mt_get will not wake the device and the
1260                  * ECOBUS read will return zero. Which will be
1261                  * (correctly) interpreted by the test below as MT
1262                  * forcewake being disabled.
1263                  */
1264                 dev_priv->uncore.funcs.force_wake_get =
1265                         fw_domains_get_with_thread_status;
1266                 dev_priv->uncore.funcs.force_wake_put =
1267                         fw_domains_put_with_fifo;
1268
1269                 /* We need to init first for ECOBUS access and then
1270                  * determine later if we want to reinit, in case of MT access is
1271                  * not working. In this stage we don't know which flavour this
1272                  * ivb is, so it is better to reset also the gen6 fw registers
1273                  * before the ecobus check.
1274                  */
1275
1276                 __raw_i915_write32(dev_priv, FORCEWAKE, 0);
1277                 __raw_posting_read(dev_priv, ECOBUS);
1278
1279                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1280                                FORCEWAKE_MT, FORCEWAKE_MT_ACK);
1281
1282                 mutex_lock(&dev->struct_mutex);
1283                 fw_domains_get_with_thread_status(dev_priv, FORCEWAKE_ALL);
1284                 ecobus = __raw_i915_read32(dev_priv, ECOBUS);
1285                 fw_domains_put_with_fifo(dev_priv, FORCEWAKE_ALL);
1286                 mutex_unlock(&dev->struct_mutex);
1287
1288                 if (!(ecobus & FORCEWAKE_MT_ENABLE)) {
1289                         DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
1290                         DRM_INFO("when using vblank-synced partial screen updates.\n");
1291                         fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1292                                        FORCEWAKE, FORCEWAKE_ACK);
1293                 }
1294         } else if (IS_GEN6(dev)) {
1295                 dev_priv->uncore.funcs.force_wake_get =
1296                         fw_domains_get_with_thread_status;
1297                 dev_priv->uncore.funcs.force_wake_put =
1298                         fw_domains_put_with_fifo;
1299                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1300                                FORCEWAKE, FORCEWAKE_ACK);
1301         }
1302
1303         /* All future platforms are expected to require complex power gating */
1304         WARN_ON(dev_priv->uncore.fw_domains == 0);
1305 }
1306
1307 void intel_uncore_init(struct drm_device *dev)
1308 {
1309         struct drm_i915_private *dev_priv = dev->dev_private;
1310
1311         i915_check_vgpu(dev);
1312
1313         intel_uncore_ellc_detect(dev);
1314         intel_uncore_fw_domains_init(dev);
1315         __intel_uncore_early_sanitize(dev, false);
1316
1317         dev_priv->uncore.unclaimed_mmio_check = 1;
1318
1319         switch (INTEL_INFO(dev)->gen) {
1320         default:
1321         case 9:
1322                 ASSIGN_WRITE_MMIO_VFUNCS(gen9);
1323                 ASSIGN_READ_MMIO_VFUNCS(gen9);
1324                 break;
1325         case 8:
1326                 if (IS_CHERRYVIEW(dev)) {
1327                         ASSIGN_WRITE_MMIO_VFUNCS(chv);
1328                         ASSIGN_READ_MMIO_VFUNCS(chv);
1329
1330                 } else {
1331                         ASSIGN_WRITE_MMIO_VFUNCS(gen8);
1332                         ASSIGN_READ_MMIO_VFUNCS(gen6);
1333                 }
1334                 break;
1335         case 7:
1336         case 6:
1337                 if (IS_HASWELL(dev)) {
1338                         ASSIGN_WRITE_MMIO_VFUNCS(hsw);
1339                 } else {
1340                         ASSIGN_WRITE_MMIO_VFUNCS(gen6);
1341                 }
1342
1343                 if (IS_VALLEYVIEW(dev)) {
1344                         ASSIGN_READ_MMIO_VFUNCS(vlv);
1345                 } else {
1346                         ASSIGN_READ_MMIO_VFUNCS(gen6);
1347                 }
1348                 break;
1349         case 5:
1350                 ASSIGN_WRITE_MMIO_VFUNCS(gen5);
1351                 ASSIGN_READ_MMIO_VFUNCS(gen5);
1352                 break;
1353         case 4:
1354         case 3:
1355         case 2:
1356                 ASSIGN_WRITE_MMIO_VFUNCS(gen2);
1357                 ASSIGN_READ_MMIO_VFUNCS(gen2);
1358                 break;
1359         }
1360
1361         if (intel_vgpu_active(dev)) {
1362                 ASSIGN_WRITE_MMIO_VFUNCS(vgpu);
1363                 ASSIGN_READ_MMIO_VFUNCS(vgpu);
1364         }
1365
1366         i915_check_and_clear_faults(dev);
1367 }
1368 #undef ASSIGN_WRITE_MMIO_VFUNCS
1369 #undef ASSIGN_READ_MMIO_VFUNCS
1370
1371 void intel_uncore_fini(struct drm_device *dev)
1372 {
1373         /* Paranoia: make sure we have disabled everything before we exit. */
1374         intel_uncore_sanitize(dev);
1375         intel_uncore_forcewake_reset(dev, false);
1376 }
1377
1378 #define GEN_RANGE(l, h) GENMASK(h, l)
1379
1380 static const struct register_whitelist {
1381         i915_reg_t offset_ldw, offset_udw;
1382         uint32_t size;
1383         /* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
1384         uint32_t gen_bitmask;
1385 } whitelist[] = {
1386         { .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
1387           .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
1388           .size = 8, .gen_bitmask = GEN_RANGE(4, 9) },
1389 };
1390
1391 int i915_reg_read_ioctl(struct drm_device *dev,
1392                         void *data, struct drm_file *file)
1393 {
1394         struct drm_i915_private *dev_priv = dev->dev_private;
1395         struct drm_i915_reg_read *reg = data;
1396         struct register_whitelist const *entry = whitelist;
1397         unsigned size;
1398         i915_reg_t offset_ldw, offset_udw;
1399         int i, ret = 0;
1400
1401         for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
1402                 if (i915_mmio_reg_offset(entry->offset_ldw) == (reg->offset & -entry->size) &&
1403                     (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
1404                         break;
1405         }
1406
1407         if (i == ARRAY_SIZE(whitelist))
1408                 return -EINVAL;
1409
1410         /* We use the low bits to encode extra flags as the register should
1411          * be naturally aligned (and those that are not so aligned merely
1412          * limit the available flags for that register).
1413          */
1414         offset_ldw = entry->offset_ldw;
1415         offset_udw = entry->offset_udw;
1416         size = entry->size;
1417         size |= reg->offset ^ i915_mmio_reg_offset(offset_ldw);
1418
1419         intel_runtime_pm_get(dev_priv);
1420
1421         switch (size) {
1422         case 8 | 1:
1423                 reg->val = I915_READ64_2x32(offset_ldw, offset_udw);
1424                 break;
1425         case 8:
1426                 reg->val = I915_READ64(offset_ldw);
1427                 break;
1428         case 4:
1429                 reg->val = I915_READ(offset_ldw);
1430                 break;
1431         case 2:
1432                 reg->val = I915_READ16(offset_ldw);
1433                 break;
1434         case 1:
1435                 reg->val = I915_READ8(offset_ldw);
1436                 break;
1437         default:
1438                 ret = -EINVAL;
1439                 goto out;
1440         }
1441
1442 out:
1443         intel_runtime_pm_put(dev_priv);
1444         return ret;
1445 }
1446
1447 int i915_get_reset_stats_ioctl(struct drm_device *dev,
1448                                void *data, struct drm_file *file)
1449 {
1450         struct drm_i915_private *dev_priv = dev->dev_private;
1451         struct drm_i915_reset_stats *args = data;
1452         struct i915_ctx_hang_stats *hs;
1453         struct intel_context *ctx;
1454         int ret;
1455
1456         if (args->flags || args->pad)
1457                 return -EINVAL;
1458
1459         if (args->ctx_id == DEFAULT_CONTEXT_HANDLE && !capable(CAP_SYS_ADMIN))
1460                 return -EPERM;
1461
1462         ret = mutex_lock_interruptible(&dev->struct_mutex);
1463         if (ret)
1464                 return ret;
1465
1466         ctx = i915_gem_context_get(file->driver_priv, args->ctx_id);
1467         if (IS_ERR(ctx)) {
1468                 mutex_unlock(&dev->struct_mutex);
1469                 return PTR_ERR(ctx);
1470         }
1471         hs = &ctx->hang_stats;
1472
1473         if (capable(CAP_SYS_ADMIN))
1474                 args->reset_count = i915_reset_count(&dev_priv->gpu_error);
1475         else
1476                 args->reset_count = 0;
1477
1478         args->batch_active = hs->batch_active;
1479         args->batch_pending = hs->batch_pending;
1480
1481         mutex_unlock(&dev->struct_mutex);
1482
1483         return 0;
1484 }
1485
1486 static int i915_reset_complete(struct drm_device *dev)
1487 {
1488         u8 gdrst;
1489         pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst);
1490         return (gdrst & GRDOM_RESET_STATUS) == 0;
1491 }
1492
1493 static int i915_do_reset(struct drm_device *dev, unsigned engine_mask)
1494 {
1495         /* assert reset for at least 20 usec */
1496         pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1497         udelay(20);
1498         pci_write_config_byte(dev->pdev, I915_GDRST, 0);
1499
1500         return wait_for(i915_reset_complete(dev), 500);
1501 }
1502
1503 static int g4x_reset_complete(struct drm_device *dev)
1504 {
1505         u8 gdrst;
1506         pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst);
1507         return (gdrst & GRDOM_RESET_ENABLE) == 0;
1508 }
1509
1510 static int g33_do_reset(struct drm_device *dev, unsigned engine_mask)
1511 {
1512         pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1513         return wait_for(g4x_reset_complete(dev), 500);
1514 }
1515
1516 static int g4x_do_reset(struct drm_device *dev, unsigned engine_mask)
1517 {
1518         struct drm_i915_private *dev_priv = dev->dev_private;
1519         int ret;
1520
1521         pci_write_config_byte(dev->pdev, I915_GDRST,
1522                               GRDOM_RENDER | GRDOM_RESET_ENABLE);
1523         ret =  wait_for(g4x_reset_complete(dev), 500);
1524         if (ret)
1525                 return ret;
1526
1527         /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1528         I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE);
1529         POSTING_READ(VDECCLK_GATE_D);
1530
1531         pci_write_config_byte(dev->pdev, I915_GDRST,
1532                               GRDOM_MEDIA | GRDOM_RESET_ENABLE);
1533         ret =  wait_for(g4x_reset_complete(dev), 500);
1534         if (ret)
1535                 return ret;
1536
1537         /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1538         I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE);
1539         POSTING_READ(VDECCLK_GATE_D);
1540
1541         pci_write_config_byte(dev->pdev, I915_GDRST, 0);
1542
1543         return 0;
1544 }
1545
1546 static int ironlake_do_reset(struct drm_device *dev, unsigned engine_mask)
1547 {
1548         struct drm_i915_private *dev_priv = dev->dev_private;
1549         int ret;
1550
1551         I915_WRITE(ILK_GDSR,
1552                    ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
1553         ret = wait_for((I915_READ(ILK_GDSR) &
1554                         ILK_GRDOM_RESET_ENABLE) == 0, 500);
1555         if (ret)
1556                 return ret;
1557
1558         I915_WRITE(ILK_GDSR,
1559                    ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
1560         ret = wait_for((I915_READ(ILK_GDSR) &
1561                         ILK_GRDOM_RESET_ENABLE) == 0, 500);
1562         if (ret)
1563                 return ret;
1564
1565         I915_WRITE(ILK_GDSR, 0);
1566
1567         return 0;
1568 }
1569
1570 /* Reset the hardware domains (GENX_GRDOM_*) specified by mask */
1571 static int gen6_hw_domain_reset(struct drm_i915_private *dev_priv,
1572                                 u32 hw_domain_mask)
1573 {
1574         int ret;
1575
1576         /* GEN6_GDRST is not in the gt power well, no need to check
1577          * for fifo space for the write or forcewake the chip for
1578          * the read
1579          */
1580         __raw_i915_write32(dev_priv, GEN6_GDRST, hw_domain_mask);
1581
1582 #define ACKED ((__raw_i915_read32(dev_priv, GEN6_GDRST) & hw_domain_mask) == 0)
1583         /* Spin waiting for the device to ack the reset requests */
1584         ret = wait_for(ACKED, 500);
1585 #undef ACKED
1586
1587         return ret;
1588 }
1589
1590 /**
1591  * gen6_reset_engines - reset individual engines
1592  * @dev: DRM device
1593  * @engine_mask: mask of intel_ring_flag() engines or ALL_ENGINES for full reset
1594  *
1595  * This function will reset the individual engines that are set in engine_mask.
1596  * If you provide ALL_ENGINES as mask, full global domain reset will be issued.
1597  *
1598  * Note: It is responsibility of the caller to handle the difference between
1599  * asking full domain reset versus reset for all available individual engines.
1600  *
1601  * Returns 0 on success, nonzero on error.
1602  */
1603 static int gen6_reset_engines(struct drm_device *dev, unsigned engine_mask)
1604 {
1605         struct drm_i915_private *dev_priv = dev->dev_private;
1606         struct intel_engine_cs *engine;
1607         const u32 hw_engine_mask[I915_NUM_ENGINES] = {
1608                 [RCS] = GEN6_GRDOM_RENDER,
1609                 [BCS] = GEN6_GRDOM_BLT,
1610                 [VCS] = GEN6_GRDOM_MEDIA,
1611                 [VCS2] = GEN8_GRDOM_MEDIA2,
1612                 [VECS] = GEN6_GRDOM_VECS,
1613         };
1614         u32 hw_mask;
1615         int ret;
1616
1617         if (engine_mask == ALL_ENGINES) {
1618                 hw_mask = GEN6_GRDOM_FULL;
1619         } else {
1620                 hw_mask = 0;
1621                 for_each_engine_masked(engine, dev_priv, engine_mask)
1622                         hw_mask |= hw_engine_mask[engine->id];
1623         }
1624
1625         ret = gen6_hw_domain_reset(dev_priv, hw_mask);
1626
1627         intel_uncore_forcewake_reset(dev, true);
1628
1629         return ret;
1630 }
1631
1632 static int wait_for_register_fw(struct drm_i915_private *dev_priv,
1633                                 i915_reg_t reg,
1634                                 const u32 mask,
1635                                 const u32 value,
1636                                 const unsigned long timeout_ms)
1637 {
1638         return wait_for((I915_READ_FW(reg) & mask) == value, timeout_ms);
1639 }
1640
1641 static int gen8_request_engine_reset(struct intel_engine_cs *engine)
1642 {
1643         int ret;
1644         struct drm_i915_private *dev_priv = engine->dev->dev_private;
1645
1646         I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base),
1647                       _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET));
1648
1649         ret = wait_for_register_fw(dev_priv,
1650                                    RING_RESET_CTL(engine->mmio_base),
1651                                    RESET_CTL_READY_TO_RESET,
1652                                    RESET_CTL_READY_TO_RESET,
1653                                    700);
1654         if (ret)
1655                 DRM_ERROR("%s: reset request timeout\n", engine->name);
1656
1657         return ret;
1658 }
1659
1660 static void gen8_unrequest_engine_reset(struct intel_engine_cs *engine)
1661 {
1662         struct drm_i915_private *dev_priv = engine->dev->dev_private;
1663
1664         I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base),
1665                       _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET));
1666 }
1667
1668 static int gen8_reset_engines(struct drm_device *dev, unsigned engine_mask)
1669 {
1670         struct drm_i915_private *dev_priv = dev->dev_private;
1671         struct intel_engine_cs *engine;
1672
1673         for_each_engine_masked(engine, dev_priv, engine_mask)
1674                 if (gen8_request_engine_reset(engine))
1675                         goto not_ready;
1676
1677         return gen6_reset_engines(dev, engine_mask);
1678
1679 not_ready:
1680         for_each_engine_masked(engine, dev_priv, engine_mask)
1681                 gen8_unrequest_engine_reset(engine);
1682
1683         return -EIO;
1684 }
1685
1686 static int (*intel_get_gpu_reset(struct drm_device *dev))(struct drm_device *,
1687                                                           unsigned engine_mask)
1688 {
1689         if (!i915.reset)
1690                 return NULL;
1691
1692         if (INTEL_INFO(dev)->gen >= 8)
1693                 return gen8_reset_engines;
1694         else if (INTEL_INFO(dev)->gen >= 6)
1695                 return gen6_reset_engines;
1696         else if (IS_GEN5(dev))
1697                 return ironlake_do_reset;
1698         else if (IS_G4X(dev))
1699                 return g4x_do_reset;
1700         else if (IS_G33(dev))
1701                 return g33_do_reset;
1702         else if (INTEL_INFO(dev)->gen >= 3)
1703                 return i915_do_reset;
1704         else
1705                 return NULL;
1706 }
1707
1708 int intel_gpu_reset(struct drm_device *dev, unsigned engine_mask)
1709 {
1710         struct drm_i915_private *dev_priv = to_i915(dev);
1711         int (*reset)(struct drm_device *, unsigned);
1712         int ret;
1713
1714         reset = intel_get_gpu_reset(dev);
1715         if (reset == NULL)
1716                 return -ENODEV;
1717
1718         /* If the power well sleeps during the reset, the reset
1719          * request may be dropped and never completes (causing -EIO).
1720          */
1721         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1722         ret = reset(dev, engine_mask);
1723         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1724
1725         return ret;
1726 }
1727
1728 bool intel_has_gpu_reset(struct drm_device *dev)
1729 {
1730         return intel_get_gpu_reset(dev) != NULL;
1731 }
1732
1733 int intel_guc_reset(struct drm_i915_private *dev_priv)
1734 {
1735         int ret;
1736         unsigned long irqflags;
1737
1738         if (!i915.enable_guc_submission)
1739                 return -EINVAL;
1740
1741         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1742         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1743
1744         ret = gen6_hw_domain_reset(dev_priv, GEN9_GRDOM_GUC);
1745
1746         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1747         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1748
1749         return ret;
1750 }
1751
1752 bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv)
1753 {
1754         return check_for_unclaimed_mmio(dev_priv);
1755 }
1756
1757 bool
1758 intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv)
1759 {
1760         if (unlikely(i915.mmio_debug ||
1761                      dev_priv->uncore.unclaimed_mmio_check <= 0))
1762                 return false;
1763
1764         if (unlikely(intel_uncore_unclaimed_mmio(dev_priv))) {
1765                 DRM_DEBUG("Unclaimed register detected, "
1766                           "enabling oneshot unclaimed register reporting. "
1767                           "Please use i915.mmio_debug=N for more information.\n");
1768                 i915.mmio_debug++;
1769                 dev_priv->uncore.unclaimed_mmio_check--;
1770                 return true;
1771         }
1772
1773         return false;
1774 }
1775
1776 static enum forcewake_domains
1777 intel_uncore_forcewake_for_read(struct drm_i915_private *dev_priv,
1778                                 i915_reg_t reg)
1779 {
1780         enum forcewake_domains fw_domains;
1781
1782         if (intel_vgpu_active(dev_priv->dev))
1783                 return 0;
1784
1785         switch (INTEL_INFO(dev_priv)->gen) {
1786         case 9:
1787                 fw_domains = __gen9_reg_read_fw_domains(i915_mmio_reg_offset(reg));
1788                 break;
1789         case 8:
1790                 if (IS_CHERRYVIEW(dev_priv))
1791                         fw_domains = __chv_reg_read_fw_domains(i915_mmio_reg_offset(reg));
1792                 else
1793                         fw_domains = __gen6_reg_read_fw_domains(i915_mmio_reg_offset(reg));
1794                 break;
1795         case 7:
1796         case 6:
1797                 if (IS_VALLEYVIEW(dev_priv))
1798                         fw_domains = __vlv_reg_read_fw_domains(i915_mmio_reg_offset(reg));
1799                 else
1800                         fw_domains = __gen6_reg_read_fw_domains(i915_mmio_reg_offset(reg));
1801                 break;
1802         default:
1803                 MISSING_CASE(INTEL_INFO(dev_priv)->gen);
1804         case 5: /* forcewake was introduced with gen6 */
1805         case 4:
1806         case 3:
1807         case 2:
1808                 return 0;
1809         }
1810
1811         WARN_ON(fw_domains & ~dev_priv->uncore.fw_domains);
1812
1813         return fw_domains;
1814 }
1815
1816 static enum forcewake_domains
1817 intel_uncore_forcewake_for_write(struct drm_i915_private *dev_priv,
1818                                  i915_reg_t reg)
1819 {
1820         enum forcewake_domains fw_domains;
1821
1822         if (intel_vgpu_active(dev_priv->dev))
1823                 return 0;
1824
1825         switch (INTEL_INFO(dev_priv)->gen) {
1826         case 9:
1827                 fw_domains = __gen9_reg_write_fw_domains(i915_mmio_reg_offset(reg));
1828                 break;
1829         case 8:
1830                 if (IS_CHERRYVIEW(dev_priv))
1831                         fw_domains = __chv_reg_write_fw_domains(i915_mmio_reg_offset(reg));
1832                 else
1833                         fw_domains = __gen8_reg_write_fw_domains(i915_mmio_reg_offset(reg));
1834                 break;
1835         case 7:
1836         case 6:
1837                 fw_domains = FORCEWAKE_RENDER;
1838                 break;
1839         default:
1840                 MISSING_CASE(INTEL_INFO(dev_priv)->gen);
1841         case 5:
1842         case 4:
1843         case 3:
1844         case 2:
1845                 return 0;
1846         }
1847
1848         WARN_ON(fw_domains & ~dev_priv->uncore.fw_domains);
1849
1850         return fw_domains;
1851 }
1852
1853 /**
1854  * intel_uncore_forcewake_for_reg - which forcewake domains are needed to access
1855  *                                  a register
1856  * @dev_priv: pointer to struct drm_i915_private
1857  * @reg: register in question
1858  * @op: operation bitmask of FW_REG_READ and/or FW_REG_WRITE
1859  *
1860  * Returns a set of forcewake domains required to be taken with for example
1861  * intel_uncore_forcewake_get for the specified register to be accessible in the
1862  * specified mode (read, write or read/write) with raw mmio accessors.
1863  *
1864  * NOTE: On Gen6 and Gen7 write forcewake domain (FORCEWAKE_RENDER) requires the
1865  * callers to do FIFO management on their own or risk losing writes.
1866  */
1867 enum forcewake_domains
1868 intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
1869                                i915_reg_t reg, unsigned int op)
1870 {
1871         enum forcewake_domains fw_domains = 0;
1872
1873         WARN_ON(!op);
1874
1875         if (op & FW_REG_READ)
1876                 fw_domains = intel_uncore_forcewake_for_read(dev_priv, reg);
1877
1878         if (op & FW_REG_WRITE)
1879                 fw_domains |= intel_uncore_forcewake_for_write(dev_priv, reg);
1880
1881         return fw_domains;
1882 }