2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "intel_drv.h"
26 #include "i915_vgpu.h"
28 #include <linux/pm_runtime.h>
30 #define FORCEWAKE_ACK_TIMEOUT_MS 50
32 #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32((dev_priv__), (reg__))
34 static const char * const forcewake_domain_names[] = {
41 intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id)
43 BUILD_BUG_ON(ARRAY_SIZE(forcewake_domain_names) != FW_DOMAIN_ID_COUNT);
45 if (id >= 0 && id < FW_DOMAIN_ID_COUNT)
46 return forcewake_domain_names[id];
54 fw_domain_reset(const struct intel_uncore_forcewake_domain *d)
56 WARN_ON(!i915_mmio_reg_valid(d->reg_set));
57 __raw_i915_write32(d->i915, d->reg_set, d->val_reset);
61 fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d)
64 hrtimer_start_range_ns(&d->timer,
65 ktime_set(0, NSEC_PER_MSEC),
71 fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d)
73 if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) &
74 FORCEWAKE_KERNEL) == 0,
75 FORCEWAKE_ACK_TIMEOUT_MS))
76 DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n",
77 intel_uncore_forcewake_domain_to_str(d->id));
81 fw_domain_get(const struct intel_uncore_forcewake_domain *d)
83 __raw_i915_write32(d->i915, d->reg_set, d->val_set);
87 fw_domain_wait_ack(const struct intel_uncore_forcewake_domain *d)
89 if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) &
91 FORCEWAKE_ACK_TIMEOUT_MS))
92 DRM_ERROR("%s: timed out waiting for forcewake ack request.\n",
93 intel_uncore_forcewake_domain_to_str(d->id));
97 fw_domain_put(const struct intel_uncore_forcewake_domain *d)
99 __raw_i915_write32(d->i915, d->reg_set, d->val_clear);
103 fw_domain_posting_read(const struct intel_uncore_forcewake_domain *d)
105 /* something from same cacheline, but not from the set register */
106 if (i915_mmio_reg_valid(d->reg_post))
107 __raw_posting_read(d->i915, d->reg_post);
111 fw_domains_get(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
113 struct intel_uncore_forcewake_domain *d;
115 for_each_fw_domain_masked(d, fw_domains, dev_priv) {
116 fw_domain_wait_ack_clear(d);
120 for_each_fw_domain_masked(d, fw_domains, dev_priv)
121 fw_domain_wait_ack(d);
125 fw_domains_put(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
127 struct intel_uncore_forcewake_domain *d;
129 for_each_fw_domain_masked(d, fw_domains, dev_priv) {
131 fw_domain_posting_read(d);
136 fw_domains_posting_read(struct drm_i915_private *dev_priv)
138 struct intel_uncore_forcewake_domain *d;
140 /* No need to do for all, just do for first found */
141 for_each_fw_domain(d, dev_priv) {
142 fw_domain_posting_read(d);
148 fw_domains_reset(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
150 struct intel_uncore_forcewake_domain *d;
152 if (dev_priv->uncore.fw_domains == 0)
155 for_each_fw_domain_masked(d, fw_domains, dev_priv)
158 fw_domains_posting_read(dev_priv);
161 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
163 /* w/a for a sporadic read returning 0 by waiting for the GT
166 if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) &
167 GEN6_GT_THREAD_STATUS_CORE_MASK) == 0, 500))
168 DRM_ERROR("GT thread status wait timed out\n");
171 static void fw_domains_get_with_thread_status(struct drm_i915_private *dev_priv,
172 enum forcewake_domains fw_domains)
174 fw_domains_get(dev_priv, fw_domains);
176 /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */
177 __gen6_gt_wait_for_thread_c0(dev_priv);
180 static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
184 gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG);
185 if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg))
186 __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg);
189 static void fw_domains_put_with_fifo(struct drm_i915_private *dev_priv,
190 enum forcewake_domains fw_domains)
192 fw_domains_put(dev_priv, fw_domains);
193 gen6_gt_check_fifodbg(dev_priv);
196 static inline u32 fifo_free_entries(struct drm_i915_private *dev_priv)
198 u32 count = __raw_i915_read32(dev_priv, GTFIFOCTL);
200 return count & GT_FIFO_FREE_ENTRIES_MASK;
203 static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
207 /* On VLV, FIFO will be shared by both SW and HW.
208 * So, we need to read the FREE_ENTRIES everytime */
209 if (IS_VALLEYVIEW(dev_priv))
210 dev_priv->uncore.fifo_count = fifo_free_entries(dev_priv);
212 if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
214 u32 fifo = fifo_free_entries(dev_priv);
216 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
218 fifo = fifo_free_entries(dev_priv);
220 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
222 dev_priv->uncore.fifo_count = fifo;
224 dev_priv->uncore.fifo_count--;
229 static enum hrtimer_restart
230 intel_uncore_fw_release_timer(struct hrtimer *timer)
232 struct intel_uncore_forcewake_domain *domain =
233 container_of(timer, struct intel_uncore_forcewake_domain, timer);
234 unsigned long irqflags;
236 assert_rpm_device_not_suspended(domain->i915);
238 spin_lock_irqsave(&domain->i915->uncore.lock, irqflags);
239 if (WARN_ON(domain->wake_count == 0))
240 domain->wake_count++;
242 if (--domain->wake_count == 0)
243 domain->i915->uncore.funcs.force_wake_put(domain->i915,
246 spin_unlock_irqrestore(&domain->i915->uncore.lock, irqflags);
248 return HRTIMER_NORESTART;
251 void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore)
253 struct drm_i915_private *dev_priv = dev->dev_private;
254 unsigned long irqflags;
255 struct intel_uncore_forcewake_domain *domain;
256 int retry_count = 100;
257 enum forcewake_domains fw = 0, active_domains;
259 /* Hold uncore.lock across reset to prevent any register access
260 * with forcewake not set correctly. Wait until all pending
261 * timers are run before holding.
266 for_each_fw_domain(domain, dev_priv) {
267 if (hrtimer_cancel(&domain->timer) == 0)
270 intel_uncore_fw_release_timer(&domain->timer);
273 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
275 for_each_fw_domain(domain, dev_priv) {
276 if (hrtimer_active(&domain->timer))
277 active_domains |= domain->mask;
280 if (active_domains == 0)
283 if (--retry_count == 0) {
284 DRM_ERROR("Timed out waiting for forcewake timers to finish\n");
288 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
292 WARN_ON(active_domains);
294 for_each_fw_domain(domain, dev_priv)
295 if (domain->wake_count)
299 dev_priv->uncore.funcs.force_wake_put(dev_priv, fw);
301 fw_domains_reset(dev_priv, FORCEWAKE_ALL);
303 if (restore) { /* If reset with a user forcewake, try to restore */
305 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw);
307 if (IS_GEN6(dev) || IS_GEN7(dev))
308 dev_priv->uncore.fifo_count =
309 fifo_free_entries(dev_priv);
313 assert_forcewakes_inactive(dev_priv);
315 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
318 static void intel_uncore_ellc_detect(struct drm_device *dev)
320 struct drm_i915_private *dev_priv = dev->dev_private;
322 if ((IS_HASWELL(dev) || IS_BROADWELL(dev) ||
323 INTEL_INFO(dev)->gen >= 9) &&
324 (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) & EDRAM_ENABLED)) {
325 /* The docs do not explain exactly how the calculation can be
326 * made. It is somewhat guessable, but for now, it's always
328 * NB: We can't write IDICR yet because we do not have gt funcs
330 dev_priv->ellc_size = 128;
331 DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size);
336 fpga_check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
340 dbg = __raw_i915_read32(dev_priv, FPGA_DBG);
341 if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM)))
344 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
350 vlv_check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
354 cer = __raw_i915_read32(dev_priv, CLAIM_ER);
355 if (likely(!(cer & (CLAIM_ER_OVERFLOW | CLAIM_ER_CTR_MASK))))
358 __raw_i915_write32(dev_priv, CLAIM_ER, CLAIM_ER_CLR);
364 check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
366 if (HAS_FPGA_DBG_UNCLAIMED(dev_priv))
367 return fpga_check_for_unclaimed_mmio(dev_priv);
369 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
370 return vlv_check_for_unclaimed_mmio(dev_priv);
375 static void __intel_uncore_early_sanitize(struct drm_device *dev,
376 bool restore_forcewake)
378 struct drm_i915_private *dev_priv = dev->dev_private;
380 /* clear out unclaimed reg detection bit */
381 if (check_for_unclaimed_mmio(dev_priv))
382 DRM_DEBUG("unclaimed mmio detected on uncore init, clearing\n");
384 /* clear out old GT FIFO errors */
385 if (IS_GEN6(dev) || IS_GEN7(dev))
386 __raw_i915_write32(dev_priv, GTFIFODBG,
387 __raw_i915_read32(dev_priv, GTFIFODBG));
389 /* WaDisableShadowRegForCpd:chv */
390 if (IS_CHERRYVIEW(dev)) {
391 __raw_i915_write32(dev_priv, GTFIFOCTL,
392 __raw_i915_read32(dev_priv, GTFIFOCTL) |
393 GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
394 GT_FIFO_CTL_RC6_POLICY_STALL);
397 intel_uncore_forcewake_reset(dev, restore_forcewake);
400 void intel_uncore_early_sanitize(struct drm_device *dev, bool restore_forcewake)
402 __intel_uncore_early_sanitize(dev, restore_forcewake);
403 i915_check_and_clear_faults(dev);
406 void intel_uncore_sanitize(struct drm_device *dev)
408 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
410 /* BIOS often leaves RC6 enabled, but disable it for hw init */
411 intel_disable_gt_powersave(dev);
414 static void __intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
415 enum forcewake_domains fw_domains)
417 struct intel_uncore_forcewake_domain *domain;
419 if (!dev_priv->uncore.funcs.force_wake_get)
422 fw_domains &= dev_priv->uncore.fw_domains;
424 for_each_fw_domain_masked(domain, fw_domains, dev_priv) {
425 if (domain->wake_count++)
426 fw_domains &= ~domain->mask;
430 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
434 * intel_uncore_forcewake_get - grab forcewake domain references
435 * @dev_priv: i915 device instance
436 * @fw_domains: forcewake domains to get reference on
438 * This function can be used get GT's forcewake domain references.
439 * Normal register access will handle the forcewake domains automatically.
440 * However if some sequence requires the GT to not power down a particular
441 * forcewake domains this function should be called at the beginning of the
442 * sequence. And subsequently the reference should be dropped by symmetric
443 * call to intel_unforce_forcewake_put(). Usually caller wants all the domains
444 * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL.
446 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
447 enum forcewake_domains fw_domains)
449 unsigned long irqflags;
451 if (!dev_priv->uncore.funcs.force_wake_get)
454 assert_rpm_wakelock_held(dev_priv);
456 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
457 __intel_uncore_forcewake_get(dev_priv, fw_domains);
458 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
462 * intel_uncore_forcewake_get__locked - grab forcewake domain references
463 * @dev_priv: i915 device instance
464 * @fw_domains: forcewake domains to get reference on
466 * See intel_uncore_forcewake_get(). This variant places the onus
467 * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
469 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
470 enum forcewake_domains fw_domains)
472 assert_spin_locked(&dev_priv->uncore.lock);
474 if (!dev_priv->uncore.funcs.force_wake_get)
477 __intel_uncore_forcewake_get(dev_priv, fw_domains);
480 static void __intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
481 enum forcewake_domains fw_domains)
483 struct intel_uncore_forcewake_domain *domain;
485 if (!dev_priv->uncore.funcs.force_wake_put)
488 fw_domains &= dev_priv->uncore.fw_domains;
490 for_each_fw_domain_masked(domain, fw_domains, dev_priv) {
491 if (WARN_ON(domain->wake_count == 0))
494 if (--domain->wake_count)
497 fw_domain_arm_timer(domain);
502 * intel_uncore_forcewake_put - release a forcewake domain reference
503 * @dev_priv: i915 device instance
504 * @fw_domains: forcewake domains to put references
506 * This function drops the device-level forcewakes for specified
507 * domains obtained by intel_uncore_forcewake_get().
509 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
510 enum forcewake_domains fw_domains)
512 unsigned long irqflags;
514 if (!dev_priv->uncore.funcs.force_wake_put)
517 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
518 __intel_uncore_forcewake_put(dev_priv, fw_domains);
519 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
523 * intel_uncore_forcewake_put__locked - grab forcewake domain references
524 * @dev_priv: i915 device instance
525 * @fw_domains: forcewake domains to get reference on
527 * See intel_uncore_forcewake_put(). This variant places the onus
528 * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
530 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
531 enum forcewake_domains fw_domains)
533 assert_spin_locked(&dev_priv->uncore.lock);
535 if (!dev_priv->uncore.funcs.force_wake_put)
538 __intel_uncore_forcewake_put(dev_priv, fw_domains);
541 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv)
543 struct intel_uncore_forcewake_domain *domain;
545 if (!dev_priv->uncore.funcs.force_wake_get)
548 for_each_fw_domain(domain, dev_priv)
549 WARN_ON(domain->wake_count);
552 /* We give fast paths for the really cool registers */
553 #define NEEDS_FORCE_WAKE(reg) ((reg) < 0x40000)
555 #define __gen6_reg_read_fw_domains(offset) \
557 enum forcewake_domains __fwd; \
558 if (NEEDS_FORCE_WAKE(offset)) \
559 __fwd = FORCEWAKE_RENDER; \
565 #define REG_RANGE(reg, start, end) ((reg) >= (start) && (reg) < (end))
567 #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \
568 (REG_RANGE((reg), 0x2000, 0x4000) || \
569 REG_RANGE((reg), 0x5000, 0x8000) || \
570 REG_RANGE((reg), 0xB000, 0x12000) || \
571 REG_RANGE((reg), 0x2E000, 0x30000))
573 #define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg) \
574 (REG_RANGE((reg), 0x12000, 0x14000) || \
575 REG_RANGE((reg), 0x22000, 0x24000) || \
576 REG_RANGE((reg), 0x30000, 0x40000))
578 #define __vlv_reg_read_fw_domains(offset) \
580 enum forcewake_domains __fwd = 0; \
581 if (!NEEDS_FORCE_WAKE(offset)) \
583 else if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(offset)) \
584 __fwd = FORCEWAKE_RENDER; \
585 else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(offset)) \
586 __fwd = FORCEWAKE_MEDIA; \
590 static const i915_reg_t gen8_shadowed_regs[] = {
593 RING_TAIL(RENDER_RING_BASE),
594 RING_TAIL(GEN6_BSD_RING_BASE),
595 RING_TAIL(VEBOX_RING_BASE),
596 RING_TAIL(BLT_RING_BASE),
597 /* TODO: Other registers are not yet used */
600 static bool is_gen8_shadowed(u32 offset)
603 for (i = 0; i < ARRAY_SIZE(gen8_shadowed_regs); i++)
604 if (offset == gen8_shadowed_regs[i].reg)
610 #define __gen8_reg_write_fw_domains(offset) \
612 enum forcewake_domains __fwd; \
613 if (NEEDS_FORCE_WAKE(offset) && !is_gen8_shadowed(offset)) \
614 __fwd = FORCEWAKE_RENDER; \
620 #define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \
621 (REG_RANGE((reg), 0x2000, 0x4000) || \
622 REG_RANGE((reg), 0x5200, 0x8000) || \
623 REG_RANGE((reg), 0x8300, 0x8500) || \
624 REG_RANGE((reg), 0xB000, 0xB480) || \
625 REG_RANGE((reg), 0xE000, 0xE800))
627 #define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg) \
628 (REG_RANGE((reg), 0x8800, 0x8900) || \
629 REG_RANGE((reg), 0xD000, 0xD800) || \
630 REG_RANGE((reg), 0x12000, 0x14000) || \
631 REG_RANGE((reg), 0x1A000, 0x1C000) || \
632 REG_RANGE((reg), 0x1E800, 0x1EA00) || \
633 REG_RANGE((reg), 0x30000, 0x38000))
635 #define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg) \
636 (REG_RANGE((reg), 0x4000, 0x5000) || \
637 REG_RANGE((reg), 0x8000, 0x8300) || \
638 REG_RANGE((reg), 0x8500, 0x8600) || \
639 REG_RANGE((reg), 0x9000, 0xB000) || \
640 REG_RANGE((reg), 0xF000, 0x10000))
642 #define __chv_reg_read_fw_domains(offset) \
644 enum forcewake_domains __fwd = 0; \
645 if (!NEEDS_FORCE_WAKE(offset)) \
647 else if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(offset)) \
648 __fwd = FORCEWAKE_RENDER; \
649 else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(offset)) \
650 __fwd = FORCEWAKE_MEDIA; \
651 else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(offset)) \
652 __fwd = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
656 #define __chv_reg_write_fw_domains(offset) \
658 enum forcewake_domains __fwd = 0; \
659 if (!NEEDS_FORCE_WAKE(offset) || is_gen8_shadowed(offset)) \
661 else if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(offset)) \
662 __fwd = FORCEWAKE_RENDER; \
663 else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(offset)) \
664 __fwd = FORCEWAKE_MEDIA; \
665 else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(offset)) \
666 __fwd = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
670 #define FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) \
671 REG_RANGE((reg), 0xB00, 0x2000)
673 #define FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) \
674 (REG_RANGE((reg), 0x2000, 0x2700) || \
675 REG_RANGE((reg), 0x3000, 0x4000) || \
676 REG_RANGE((reg), 0x5200, 0x8000) || \
677 REG_RANGE((reg), 0x8140, 0x8160) || \
678 REG_RANGE((reg), 0x8300, 0x8500) || \
679 REG_RANGE((reg), 0x8C00, 0x8D00) || \
680 REG_RANGE((reg), 0xB000, 0xB480) || \
681 REG_RANGE((reg), 0xE000, 0xE900) || \
682 REG_RANGE((reg), 0x24400, 0x24800))
684 #define FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) \
685 (REG_RANGE((reg), 0x8130, 0x8140) || \
686 REG_RANGE((reg), 0x8800, 0x8A00) || \
687 REG_RANGE((reg), 0xD000, 0xD800) || \
688 REG_RANGE((reg), 0x12000, 0x14000) || \
689 REG_RANGE((reg), 0x1A000, 0x1EA00) || \
690 REG_RANGE((reg), 0x30000, 0x40000))
692 #define FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg) \
693 REG_RANGE((reg), 0x9400, 0x9800)
695 #define FORCEWAKE_GEN9_BLITTER_RANGE_OFFSET(reg) \
696 ((reg) < 0x40000 && \
697 !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) && \
698 !FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) && \
699 !FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) && \
700 !FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg))
702 #define SKL_NEEDS_FORCE_WAKE(reg) \
703 ((reg) < 0x40000 && !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg))
705 #define __gen9_reg_read_fw_domains(offset) \
707 enum forcewake_domains __fwd; \
708 if (!SKL_NEEDS_FORCE_WAKE(offset)) \
710 else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(offset)) \
711 __fwd = FORCEWAKE_RENDER; \
712 else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(offset)) \
713 __fwd = FORCEWAKE_MEDIA; \
714 else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(offset)) \
715 __fwd = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
717 __fwd = FORCEWAKE_BLITTER; \
721 static const i915_reg_t gen9_shadowed_regs[] = {
722 RING_TAIL(RENDER_RING_BASE),
723 RING_TAIL(GEN6_BSD_RING_BASE),
724 RING_TAIL(VEBOX_RING_BASE),
725 RING_TAIL(BLT_RING_BASE),
728 /* TODO: Other registers are not yet used */
731 static bool is_gen9_shadowed(u32 offset)
734 for (i = 0; i < ARRAY_SIZE(gen9_shadowed_regs); i++)
735 if (offset == gen9_shadowed_regs[i].reg)
741 #define __gen9_reg_write_fw_domains(offset) \
743 enum forcewake_domains __fwd; \
744 if (!SKL_NEEDS_FORCE_WAKE(offset) || is_gen9_shadowed(offset)) \
746 else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(offset)) \
747 __fwd = FORCEWAKE_RENDER; \
748 else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(offset)) \
749 __fwd = FORCEWAKE_MEDIA; \
750 else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(offset)) \
751 __fwd = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
753 __fwd = FORCEWAKE_BLITTER; \
758 ilk_dummy_write(struct drm_i915_private *dev_priv)
760 /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
761 * the chip from rc6 before touching it for real. MI_MODE is masked,
762 * hence harmless to write 0 into. */
763 __raw_i915_write32(dev_priv, MI_MODE, 0);
767 __unclaimed_reg_debug(struct drm_i915_private *dev_priv,
768 const i915_reg_t reg,
772 /* XXX. We limit the auto arming traces for mmio
773 * debugs on these platforms. There are just too many
774 * revealed by these and CI/Bat suffers from the noise.
775 * Please fix and then re-enable the automatic traces.
777 if (i915.mmio_debug < 2 &&
778 (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
781 if (WARN(check_for_unclaimed_mmio(dev_priv),
782 "Unclaimed register detected %s %s register 0x%x\n",
783 before ? "before" : "after",
784 read ? "reading" : "writing to",
785 i915_mmio_reg_offset(reg)))
786 i915.mmio_debug--; /* Only report the first N failures */
790 unclaimed_reg_debug(struct drm_i915_private *dev_priv,
791 const i915_reg_t reg,
795 if (likely(!i915.mmio_debug))
798 __unclaimed_reg_debug(dev_priv, reg, read, before);
801 #define GEN2_READ_HEADER(x) \
803 assert_rpm_wakelock_held(dev_priv);
805 #define GEN2_READ_FOOTER \
806 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
809 #define __gen2_read(x) \
811 gen2_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
812 GEN2_READ_HEADER(x); \
813 val = __raw_i915_read##x(dev_priv, reg); \
817 #define __gen5_read(x) \
819 gen5_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
820 GEN2_READ_HEADER(x); \
821 ilk_dummy_write(dev_priv); \
822 val = __raw_i915_read##x(dev_priv, reg); \
838 #undef GEN2_READ_FOOTER
839 #undef GEN2_READ_HEADER
841 #define GEN6_READ_HEADER(x) \
842 u32 offset = i915_mmio_reg_offset(reg); \
843 unsigned long irqflags; \
845 assert_rpm_wakelock_held(dev_priv); \
846 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \
847 unclaimed_reg_debug(dev_priv, reg, true, true)
849 #define GEN6_READ_FOOTER \
850 unclaimed_reg_debug(dev_priv, reg, true, false); \
851 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
852 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
855 static inline void __force_wake_auto(struct drm_i915_private *dev_priv,
856 enum forcewake_domains fw_domains)
858 struct intel_uncore_forcewake_domain *domain;
860 if (WARN_ON(!fw_domains))
863 /* Ideally GCC would be constant-fold and eliminate this loop */
864 for_each_fw_domain_masked(domain, fw_domains, dev_priv) {
865 if (domain->wake_count) {
866 fw_domains &= ~domain->mask;
870 fw_domain_arm_timer(domain);
874 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
877 #define __gen6_read(x) \
879 gen6_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
880 enum forcewake_domains fw_engine; \
881 GEN6_READ_HEADER(x); \
882 fw_engine = __gen6_reg_read_fw_domains(offset); \
884 __force_wake_auto(dev_priv, fw_engine); \
885 val = __raw_i915_read##x(dev_priv, reg); \
889 #define __vlv_read(x) \
891 vlv_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
892 enum forcewake_domains fw_engine; \
893 GEN6_READ_HEADER(x); \
894 fw_engine = __vlv_reg_read_fw_domains(offset); \
896 __force_wake_auto(dev_priv, fw_engine); \
897 val = __raw_i915_read##x(dev_priv, reg); \
901 #define __chv_read(x) \
903 chv_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
904 enum forcewake_domains fw_engine; \
905 GEN6_READ_HEADER(x); \
906 fw_engine = __chv_reg_read_fw_domains(offset); \
908 __force_wake_auto(dev_priv, fw_engine); \
909 val = __raw_i915_read##x(dev_priv, reg); \
913 #define __gen9_read(x) \
915 gen9_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
916 enum forcewake_domains fw_engine; \
917 GEN6_READ_HEADER(x); \
918 fw_engine = __gen9_reg_read_fw_domains(offset); \
920 __force_wake_auto(dev_priv, fw_engine); \
921 val = __raw_i915_read##x(dev_priv, reg); \
946 #undef GEN6_READ_FOOTER
947 #undef GEN6_READ_HEADER
949 #define VGPU_READ_HEADER(x) \
950 unsigned long irqflags; \
952 assert_rpm_device_not_suspended(dev_priv); \
953 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
955 #define VGPU_READ_FOOTER \
956 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
957 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
960 #define __vgpu_read(x) \
962 vgpu_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
963 VGPU_READ_HEADER(x); \
964 val = __raw_i915_read##x(dev_priv, reg); \
974 #undef VGPU_READ_FOOTER
975 #undef VGPU_READ_HEADER
977 #define GEN2_WRITE_HEADER \
978 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
979 assert_rpm_wakelock_held(dev_priv); \
981 #define GEN2_WRITE_FOOTER
983 #define __gen2_write(x) \
985 gen2_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
987 __raw_i915_write##x(dev_priv, reg, val); \
991 #define __gen5_write(x) \
993 gen5_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
995 ilk_dummy_write(dev_priv); \
996 __raw_i915_write##x(dev_priv, reg, val); \
1012 #undef GEN2_WRITE_FOOTER
1013 #undef GEN2_WRITE_HEADER
1015 #define GEN6_WRITE_HEADER \
1016 u32 offset = i915_mmio_reg_offset(reg); \
1017 unsigned long irqflags; \
1018 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1019 assert_rpm_wakelock_held(dev_priv); \
1020 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \
1021 unclaimed_reg_debug(dev_priv, reg, false, true)
1023 #define GEN6_WRITE_FOOTER \
1024 unclaimed_reg_debug(dev_priv, reg, false, false); \
1025 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
1027 #define __gen6_write(x) \
1029 gen6_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1030 u32 __fifo_ret = 0; \
1031 GEN6_WRITE_HEADER; \
1032 if (NEEDS_FORCE_WAKE(offset)) { \
1033 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1035 __raw_i915_write##x(dev_priv, reg, val); \
1036 if (unlikely(__fifo_ret)) { \
1037 gen6_gt_check_fifodbg(dev_priv); \
1039 GEN6_WRITE_FOOTER; \
1042 #define __hsw_write(x) \
1044 hsw_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1045 u32 __fifo_ret = 0; \
1046 GEN6_WRITE_HEADER; \
1047 if (NEEDS_FORCE_WAKE(offset)) { \
1048 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1050 __raw_i915_write##x(dev_priv, reg, val); \
1051 if (unlikely(__fifo_ret)) { \
1052 gen6_gt_check_fifodbg(dev_priv); \
1054 GEN6_WRITE_FOOTER; \
1057 #define __gen8_write(x) \
1059 gen8_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1060 enum forcewake_domains fw_engine; \
1061 GEN6_WRITE_HEADER; \
1062 fw_engine = __gen8_reg_write_fw_domains(offset); \
1064 __force_wake_auto(dev_priv, fw_engine); \
1065 __raw_i915_write##x(dev_priv, reg, val); \
1066 GEN6_WRITE_FOOTER; \
1069 #define __chv_write(x) \
1071 chv_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1072 enum forcewake_domains fw_engine; \
1073 GEN6_WRITE_HEADER; \
1074 fw_engine = __chv_reg_write_fw_domains(offset); \
1076 __force_wake_auto(dev_priv, fw_engine); \
1077 __raw_i915_write##x(dev_priv, reg, val); \
1078 GEN6_WRITE_FOOTER; \
1081 #define __gen9_write(x) \
1083 gen9_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, \
1085 enum forcewake_domains fw_engine; \
1086 GEN6_WRITE_HEADER; \
1087 fw_engine = __gen9_reg_write_fw_domains(offset); \
1089 __force_wake_auto(dev_priv, fw_engine); \
1090 __raw_i915_write##x(dev_priv, reg, val); \
1091 GEN6_WRITE_FOOTER; \
1120 #undef GEN6_WRITE_FOOTER
1121 #undef GEN6_WRITE_HEADER
1123 #define VGPU_WRITE_HEADER \
1124 unsigned long irqflags; \
1125 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1126 assert_rpm_device_not_suspended(dev_priv); \
1127 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
1129 #define VGPU_WRITE_FOOTER \
1130 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
1132 #define __vgpu_write(x) \
1133 static void vgpu_write##x(struct drm_i915_private *dev_priv, \
1134 i915_reg_t reg, u##x val, bool trace) { \
1135 VGPU_WRITE_HEADER; \
1136 __raw_i915_write##x(dev_priv, reg, val); \
1137 VGPU_WRITE_FOOTER; \
1146 #undef VGPU_WRITE_FOOTER
1147 #undef VGPU_WRITE_HEADER
1149 #define ASSIGN_WRITE_MMIO_VFUNCS(x) \
1151 dev_priv->uncore.funcs.mmio_writeb = x##_write8; \
1152 dev_priv->uncore.funcs.mmio_writew = x##_write16; \
1153 dev_priv->uncore.funcs.mmio_writel = x##_write32; \
1154 dev_priv->uncore.funcs.mmio_writeq = x##_write64; \
1157 #define ASSIGN_READ_MMIO_VFUNCS(x) \
1159 dev_priv->uncore.funcs.mmio_readb = x##_read8; \
1160 dev_priv->uncore.funcs.mmio_readw = x##_read16; \
1161 dev_priv->uncore.funcs.mmio_readl = x##_read32; \
1162 dev_priv->uncore.funcs.mmio_readq = x##_read64; \
1166 static void fw_domain_init(struct drm_i915_private *dev_priv,
1167 enum forcewake_domain_id domain_id,
1171 struct intel_uncore_forcewake_domain *d;
1173 if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT))
1176 d = &dev_priv->uncore.fw_domain[domain_id];
1178 WARN_ON(d->wake_count);
1181 d->reg_set = reg_set;
1182 d->reg_ack = reg_ack;
1184 if (IS_GEN6(dev_priv)) {
1186 d->val_set = FORCEWAKE_KERNEL;
1189 /* WaRsClearFWBitsAtReset:bdw,skl */
1190 d->val_reset = _MASKED_BIT_DISABLE(0xffff);
1191 d->val_set = _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL);
1192 d->val_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL);
1195 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1196 d->reg_post = FORCEWAKE_ACK_VLV;
1197 else if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv) || IS_GEN8(dev_priv))
1198 d->reg_post = ECOBUS;
1203 BUILD_BUG_ON(FORCEWAKE_RENDER != (1 << FW_DOMAIN_ID_RENDER));
1204 BUILD_BUG_ON(FORCEWAKE_BLITTER != (1 << FW_DOMAIN_ID_BLITTER));
1205 BUILD_BUG_ON(FORCEWAKE_MEDIA != (1 << FW_DOMAIN_ID_MEDIA));
1207 d->mask = 1 << domain_id;
1209 hrtimer_init(&d->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1210 d->timer.function = intel_uncore_fw_release_timer;
1212 dev_priv->uncore.fw_domains |= (1 << domain_id);
1217 static void intel_uncore_fw_domains_init(struct drm_device *dev)
1219 struct drm_i915_private *dev_priv = dev->dev_private;
1221 if (INTEL_INFO(dev_priv)->gen <= 5)
1225 dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
1226 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1227 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1228 FORCEWAKE_RENDER_GEN9,
1229 FORCEWAKE_ACK_RENDER_GEN9);
1230 fw_domain_init(dev_priv, FW_DOMAIN_ID_BLITTER,
1231 FORCEWAKE_BLITTER_GEN9,
1232 FORCEWAKE_ACK_BLITTER_GEN9);
1233 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
1234 FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
1235 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1236 dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
1237 if (!IS_CHERRYVIEW(dev))
1238 dev_priv->uncore.funcs.force_wake_put =
1239 fw_domains_put_with_fifo;
1241 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1242 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1243 FORCEWAKE_VLV, FORCEWAKE_ACK_VLV);
1244 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
1245 FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV);
1246 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1247 dev_priv->uncore.funcs.force_wake_get =
1248 fw_domains_get_with_thread_status;
1249 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1250 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1251 FORCEWAKE_MT, FORCEWAKE_ACK_HSW);
1252 } else if (IS_IVYBRIDGE(dev)) {
1255 /* IVB configs may use multi-threaded forcewake */
1257 /* A small trick here - if the bios hasn't configured
1258 * MT forcewake, and if the device is in RC6, then
1259 * force_wake_mt_get will not wake the device and the
1260 * ECOBUS read will return zero. Which will be
1261 * (correctly) interpreted by the test below as MT
1262 * forcewake being disabled.
1264 dev_priv->uncore.funcs.force_wake_get =
1265 fw_domains_get_with_thread_status;
1266 dev_priv->uncore.funcs.force_wake_put =
1267 fw_domains_put_with_fifo;
1269 /* We need to init first for ECOBUS access and then
1270 * determine later if we want to reinit, in case of MT access is
1271 * not working. In this stage we don't know which flavour this
1272 * ivb is, so it is better to reset also the gen6 fw registers
1273 * before the ecobus check.
1276 __raw_i915_write32(dev_priv, FORCEWAKE, 0);
1277 __raw_posting_read(dev_priv, ECOBUS);
1279 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1280 FORCEWAKE_MT, FORCEWAKE_MT_ACK);
1282 mutex_lock(&dev->struct_mutex);
1283 fw_domains_get_with_thread_status(dev_priv, FORCEWAKE_ALL);
1284 ecobus = __raw_i915_read32(dev_priv, ECOBUS);
1285 fw_domains_put_with_fifo(dev_priv, FORCEWAKE_ALL);
1286 mutex_unlock(&dev->struct_mutex);
1288 if (!(ecobus & FORCEWAKE_MT_ENABLE)) {
1289 DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
1290 DRM_INFO("when using vblank-synced partial screen updates.\n");
1291 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1292 FORCEWAKE, FORCEWAKE_ACK);
1294 } else if (IS_GEN6(dev)) {
1295 dev_priv->uncore.funcs.force_wake_get =
1296 fw_domains_get_with_thread_status;
1297 dev_priv->uncore.funcs.force_wake_put =
1298 fw_domains_put_with_fifo;
1299 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1300 FORCEWAKE, FORCEWAKE_ACK);
1303 /* All future platforms are expected to require complex power gating */
1304 WARN_ON(dev_priv->uncore.fw_domains == 0);
1307 void intel_uncore_init(struct drm_device *dev)
1309 struct drm_i915_private *dev_priv = dev->dev_private;
1311 i915_check_vgpu(dev);
1313 intel_uncore_ellc_detect(dev);
1314 intel_uncore_fw_domains_init(dev);
1315 __intel_uncore_early_sanitize(dev, false);
1317 dev_priv->uncore.unclaimed_mmio_check = 1;
1319 switch (INTEL_INFO(dev)->gen) {
1322 ASSIGN_WRITE_MMIO_VFUNCS(gen9);
1323 ASSIGN_READ_MMIO_VFUNCS(gen9);
1326 if (IS_CHERRYVIEW(dev)) {
1327 ASSIGN_WRITE_MMIO_VFUNCS(chv);
1328 ASSIGN_READ_MMIO_VFUNCS(chv);
1331 ASSIGN_WRITE_MMIO_VFUNCS(gen8);
1332 ASSIGN_READ_MMIO_VFUNCS(gen6);
1337 if (IS_HASWELL(dev)) {
1338 ASSIGN_WRITE_MMIO_VFUNCS(hsw);
1340 ASSIGN_WRITE_MMIO_VFUNCS(gen6);
1343 if (IS_VALLEYVIEW(dev)) {
1344 ASSIGN_READ_MMIO_VFUNCS(vlv);
1346 ASSIGN_READ_MMIO_VFUNCS(gen6);
1350 ASSIGN_WRITE_MMIO_VFUNCS(gen5);
1351 ASSIGN_READ_MMIO_VFUNCS(gen5);
1356 ASSIGN_WRITE_MMIO_VFUNCS(gen2);
1357 ASSIGN_READ_MMIO_VFUNCS(gen2);
1361 if (intel_vgpu_active(dev)) {
1362 ASSIGN_WRITE_MMIO_VFUNCS(vgpu);
1363 ASSIGN_READ_MMIO_VFUNCS(vgpu);
1366 i915_check_and_clear_faults(dev);
1368 #undef ASSIGN_WRITE_MMIO_VFUNCS
1369 #undef ASSIGN_READ_MMIO_VFUNCS
1371 void intel_uncore_fini(struct drm_device *dev)
1373 /* Paranoia: make sure we have disabled everything before we exit. */
1374 intel_uncore_sanitize(dev);
1375 intel_uncore_forcewake_reset(dev, false);
1378 #define GEN_RANGE(l, h) GENMASK(h, l)
1380 static const struct register_whitelist {
1381 i915_reg_t offset_ldw, offset_udw;
1383 /* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
1384 uint32_t gen_bitmask;
1386 { .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
1387 .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
1388 .size = 8, .gen_bitmask = GEN_RANGE(4, 9) },
1391 int i915_reg_read_ioctl(struct drm_device *dev,
1392 void *data, struct drm_file *file)
1394 struct drm_i915_private *dev_priv = dev->dev_private;
1395 struct drm_i915_reg_read *reg = data;
1396 struct register_whitelist const *entry = whitelist;
1398 i915_reg_t offset_ldw, offset_udw;
1401 for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
1402 if (i915_mmio_reg_offset(entry->offset_ldw) == (reg->offset & -entry->size) &&
1403 (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
1407 if (i == ARRAY_SIZE(whitelist))
1410 /* We use the low bits to encode extra flags as the register should
1411 * be naturally aligned (and those that are not so aligned merely
1412 * limit the available flags for that register).
1414 offset_ldw = entry->offset_ldw;
1415 offset_udw = entry->offset_udw;
1417 size |= reg->offset ^ i915_mmio_reg_offset(offset_ldw);
1419 intel_runtime_pm_get(dev_priv);
1423 reg->val = I915_READ64_2x32(offset_ldw, offset_udw);
1426 reg->val = I915_READ64(offset_ldw);
1429 reg->val = I915_READ(offset_ldw);
1432 reg->val = I915_READ16(offset_ldw);
1435 reg->val = I915_READ8(offset_ldw);
1443 intel_runtime_pm_put(dev_priv);
1447 int i915_get_reset_stats_ioctl(struct drm_device *dev,
1448 void *data, struct drm_file *file)
1450 struct drm_i915_private *dev_priv = dev->dev_private;
1451 struct drm_i915_reset_stats *args = data;
1452 struct i915_ctx_hang_stats *hs;
1453 struct intel_context *ctx;
1456 if (args->flags || args->pad)
1459 if (args->ctx_id == DEFAULT_CONTEXT_HANDLE && !capable(CAP_SYS_ADMIN))
1462 ret = mutex_lock_interruptible(&dev->struct_mutex);
1466 ctx = i915_gem_context_get(file->driver_priv, args->ctx_id);
1468 mutex_unlock(&dev->struct_mutex);
1469 return PTR_ERR(ctx);
1471 hs = &ctx->hang_stats;
1473 if (capable(CAP_SYS_ADMIN))
1474 args->reset_count = i915_reset_count(&dev_priv->gpu_error);
1476 args->reset_count = 0;
1478 args->batch_active = hs->batch_active;
1479 args->batch_pending = hs->batch_pending;
1481 mutex_unlock(&dev->struct_mutex);
1486 static int i915_reset_complete(struct drm_device *dev)
1489 pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst);
1490 return (gdrst & GRDOM_RESET_STATUS) == 0;
1493 static int i915_do_reset(struct drm_device *dev, unsigned engine_mask)
1495 /* assert reset for at least 20 usec */
1496 pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1498 pci_write_config_byte(dev->pdev, I915_GDRST, 0);
1500 return wait_for(i915_reset_complete(dev), 500);
1503 static int g4x_reset_complete(struct drm_device *dev)
1506 pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst);
1507 return (gdrst & GRDOM_RESET_ENABLE) == 0;
1510 static int g33_do_reset(struct drm_device *dev, unsigned engine_mask)
1512 pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1513 return wait_for(g4x_reset_complete(dev), 500);
1516 static int g4x_do_reset(struct drm_device *dev, unsigned engine_mask)
1518 struct drm_i915_private *dev_priv = dev->dev_private;
1521 pci_write_config_byte(dev->pdev, I915_GDRST,
1522 GRDOM_RENDER | GRDOM_RESET_ENABLE);
1523 ret = wait_for(g4x_reset_complete(dev), 500);
1527 /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1528 I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE);
1529 POSTING_READ(VDECCLK_GATE_D);
1531 pci_write_config_byte(dev->pdev, I915_GDRST,
1532 GRDOM_MEDIA | GRDOM_RESET_ENABLE);
1533 ret = wait_for(g4x_reset_complete(dev), 500);
1537 /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1538 I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE);
1539 POSTING_READ(VDECCLK_GATE_D);
1541 pci_write_config_byte(dev->pdev, I915_GDRST, 0);
1546 static int ironlake_do_reset(struct drm_device *dev, unsigned engine_mask)
1548 struct drm_i915_private *dev_priv = dev->dev_private;
1551 I915_WRITE(ILK_GDSR,
1552 ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
1553 ret = wait_for((I915_READ(ILK_GDSR) &
1554 ILK_GRDOM_RESET_ENABLE) == 0, 500);
1558 I915_WRITE(ILK_GDSR,
1559 ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
1560 ret = wait_for((I915_READ(ILK_GDSR) &
1561 ILK_GRDOM_RESET_ENABLE) == 0, 500);
1565 I915_WRITE(ILK_GDSR, 0);
1570 /* Reset the hardware domains (GENX_GRDOM_*) specified by mask */
1571 static int gen6_hw_domain_reset(struct drm_i915_private *dev_priv,
1576 /* GEN6_GDRST is not in the gt power well, no need to check
1577 * for fifo space for the write or forcewake the chip for
1580 __raw_i915_write32(dev_priv, GEN6_GDRST, hw_domain_mask);
1582 #define ACKED ((__raw_i915_read32(dev_priv, GEN6_GDRST) & hw_domain_mask) == 0)
1583 /* Spin waiting for the device to ack the reset requests */
1584 ret = wait_for(ACKED, 500);
1591 * gen6_reset_engines - reset individual engines
1593 * @engine_mask: mask of intel_ring_flag() engines or ALL_ENGINES for full reset
1595 * This function will reset the individual engines that are set in engine_mask.
1596 * If you provide ALL_ENGINES as mask, full global domain reset will be issued.
1598 * Note: It is responsibility of the caller to handle the difference between
1599 * asking full domain reset versus reset for all available individual engines.
1601 * Returns 0 on success, nonzero on error.
1603 static int gen6_reset_engines(struct drm_device *dev, unsigned engine_mask)
1605 struct drm_i915_private *dev_priv = dev->dev_private;
1606 struct intel_engine_cs *engine;
1607 const u32 hw_engine_mask[I915_NUM_ENGINES] = {
1608 [RCS] = GEN6_GRDOM_RENDER,
1609 [BCS] = GEN6_GRDOM_BLT,
1610 [VCS] = GEN6_GRDOM_MEDIA,
1611 [VCS2] = GEN8_GRDOM_MEDIA2,
1612 [VECS] = GEN6_GRDOM_VECS,
1617 if (engine_mask == ALL_ENGINES) {
1618 hw_mask = GEN6_GRDOM_FULL;
1621 for_each_engine_masked(engine, dev_priv, engine_mask)
1622 hw_mask |= hw_engine_mask[engine->id];
1625 ret = gen6_hw_domain_reset(dev_priv, hw_mask);
1627 intel_uncore_forcewake_reset(dev, true);
1632 static int wait_for_register_fw(struct drm_i915_private *dev_priv,
1636 const unsigned long timeout_ms)
1638 return wait_for((I915_READ_FW(reg) & mask) == value, timeout_ms);
1641 static int gen8_request_engine_reset(struct intel_engine_cs *engine)
1644 struct drm_i915_private *dev_priv = engine->dev->dev_private;
1646 I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base),
1647 _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET));
1649 ret = wait_for_register_fw(dev_priv,
1650 RING_RESET_CTL(engine->mmio_base),
1651 RESET_CTL_READY_TO_RESET,
1652 RESET_CTL_READY_TO_RESET,
1655 DRM_ERROR("%s: reset request timeout\n", engine->name);
1660 static void gen8_unrequest_engine_reset(struct intel_engine_cs *engine)
1662 struct drm_i915_private *dev_priv = engine->dev->dev_private;
1664 I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base),
1665 _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET));
1668 static int gen8_reset_engines(struct drm_device *dev, unsigned engine_mask)
1670 struct drm_i915_private *dev_priv = dev->dev_private;
1671 struct intel_engine_cs *engine;
1673 for_each_engine_masked(engine, dev_priv, engine_mask)
1674 if (gen8_request_engine_reset(engine))
1677 return gen6_reset_engines(dev, engine_mask);
1680 for_each_engine_masked(engine, dev_priv, engine_mask)
1681 gen8_unrequest_engine_reset(engine);
1686 static int (*intel_get_gpu_reset(struct drm_device *dev))(struct drm_device *,
1687 unsigned engine_mask)
1692 if (INTEL_INFO(dev)->gen >= 8)
1693 return gen8_reset_engines;
1694 else if (INTEL_INFO(dev)->gen >= 6)
1695 return gen6_reset_engines;
1696 else if (IS_GEN5(dev))
1697 return ironlake_do_reset;
1698 else if (IS_G4X(dev))
1699 return g4x_do_reset;
1700 else if (IS_G33(dev))
1701 return g33_do_reset;
1702 else if (INTEL_INFO(dev)->gen >= 3)
1703 return i915_do_reset;
1708 int intel_gpu_reset(struct drm_device *dev, unsigned engine_mask)
1710 struct drm_i915_private *dev_priv = to_i915(dev);
1711 int (*reset)(struct drm_device *, unsigned);
1714 reset = intel_get_gpu_reset(dev);
1718 /* If the power well sleeps during the reset, the reset
1719 * request may be dropped and never completes (causing -EIO).
1721 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1722 ret = reset(dev, engine_mask);
1723 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1728 bool intel_has_gpu_reset(struct drm_device *dev)
1730 return intel_get_gpu_reset(dev) != NULL;
1733 int intel_guc_reset(struct drm_i915_private *dev_priv)
1736 unsigned long irqflags;
1738 if (!i915.enable_guc_submission)
1741 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1742 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1744 ret = gen6_hw_domain_reset(dev_priv, GEN9_GRDOM_GUC);
1746 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1747 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1752 bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv)
1754 return check_for_unclaimed_mmio(dev_priv);
1758 intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv)
1760 if (unlikely(i915.mmio_debug ||
1761 dev_priv->uncore.unclaimed_mmio_check <= 0))
1764 if (unlikely(intel_uncore_unclaimed_mmio(dev_priv))) {
1765 DRM_DEBUG("Unclaimed register detected, "
1766 "enabling oneshot unclaimed register reporting. "
1767 "Please use i915.mmio_debug=N for more information.\n");
1769 dev_priv->uncore.unclaimed_mmio_check--;