drivers/gpu/drm/i915/intel_uncore.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "i915_drv.h"
  25 #include "intel_drv.h"
  26 #include "i915_vgpu.h"
  27
  28 #include <linux/pm_runtime.h>
  29
  30 #define FORCEWAKE_ACK_TIMEOUT_MS 50
  31
  32 #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32((dev_priv__), (reg__))
  33
  34 static const char * const forcewake_domain_names[] = {
  35         "render",
  36         "blitter",
  37         "media",
  38 };
  39
  40 const char *
  41 intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id)
  42 {
  43         BUILD_BUG_ON(ARRAY_SIZE(forcewake_domain_names) != FW_DOMAIN_ID_COUNT);
  44
  45         if (id >= 0 && id < FW_DOMAIN_ID_COUNT)
  46                 return forcewake_domain_names[id];
  47
  48         WARN_ON(id);
  49
  50         return "unknown";
  51 }
  52
  53 static inline void
  54 fw_domain_reset(const struct intel_uncore_forcewake_domain *d)
  55 {
  56         WARN_ON(!i915_mmio_reg_valid(d->reg_set));
  57         __raw_i915_write32(d->i915, d->reg_set, d->val_reset);
  58 }
  59
  60 static inline void
  61 fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d)
  62 {
  63         mod_timer_pinned(&d->timer, jiffies + 1);
  64 }
  65
  66 static inline void
  67 fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d)
  68 {
  69         if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) &
  70                              FORCEWAKE_KERNEL) == 0,
  71                             FORCEWAKE_ACK_TIMEOUT_MS))
  72                 DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n",
  73                           intel_uncore_forcewake_domain_to_str(d->id));
  74 }
  75
  76 static inline void
  77 fw_domain_get(const struct intel_uncore_forcewake_domain *d)
  78 {
  79         __raw_i915_write32(d->i915, d->reg_set, d->val_set);
  80 }
  81
  82 static inline void
  83 fw_domain_wait_ack(const struct intel_uncore_forcewake_domain *d)
  84 {
  85         if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) &
  86                              FORCEWAKE_KERNEL),
  87                             FORCEWAKE_ACK_TIMEOUT_MS))
  88                 DRM_ERROR("%s: timed out waiting for forcewake ack request.\n",
  89                           intel_uncore_forcewake_domain_to_str(d->id));
  90 }
  91
  92 static inline void
  93 fw_domain_put(const struct intel_uncore_forcewake_domain *d)
  94 {
  95         __raw_i915_write32(d->i915, d->reg_set, d->val_clear);
  96 }
  97
  98 static inline void
  99 fw_domain_posting_read(const struct intel_uncore_forcewake_domain *d)
 100 {
 101         /* something from same cacheline, but not from the set register */
 102         if (i915_mmio_reg_valid(d->reg_post))
 103                 __raw_posting_read(d->i915, d->reg_post);
 104 }
 105
 106 static void
 107 fw_domains_get(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
 108 {
 109         struct intel_uncore_forcewake_domain *d;
 110         enum forcewake_domain_id id;
 111
 112         for_each_fw_domain_mask(d, fw_domains, dev_priv, id) {
 113                 fw_domain_wait_ack_clear(d);
 114                 fw_domain_get(d);
 115                 fw_domain_wait_ack(d);
 116         }
 117 }
 118
 119 static void
 120 fw_domains_put(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
 121 {
 122         struct intel_uncore_forcewake_domain *d;
 123         enum forcewake_domain_id id;
 124
 125         for_each_fw_domain_mask(d, fw_domains, dev_priv, id) {
 126                 fw_domain_put(d);
 127                 fw_domain_posting_read(d);
 128         }
 129 }
 130
 131 static void
 132 fw_domains_posting_read(struct drm_i915_private *dev_priv)
 133 {
 134         struct intel_uncore_forcewake_domain *d;
 135         enum forcewake_domain_id id;
 136
 137         /* No need to do for all, just do for first found */
 138         for_each_fw_domain(d, dev_priv, id) {
 139                 fw_domain_posting_read(d);
 140                 break;
 141         }
 142 }
 143
 144 static void
 145 fw_domains_reset(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
 146 {
 147         struct intel_uncore_forcewake_domain *d;
 148         enum forcewake_domain_id id;
 149
 150         if (dev_priv->uncore.fw_domains == 0)
 151                 return;
 152
 153         for_each_fw_domain_mask(d, fw_domains, dev_priv, id)
 154                 fw_domain_reset(d);
 155
 156         fw_domains_posting_read(dev_priv);
 157 }
 158
 159 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
 160 {
 161         /* w/a for a sporadic read returning 0 by waiting for the GT
 162          * thread to wake up.
 163          */
 164         if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) &
 165                                 GEN6_GT_THREAD_STATUS_CORE_MASK) == 0, 500))
 166                 DRM_ERROR("GT thread status wait timed out\n");
 167 }
 168
 169 static void fw_domains_get_with_thread_status(struct drm_i915_private *dev_priv,
 170                                               enum forcewake_domains fw_domains)
 171 {
 172         fw_domains_get(dev_priv, fw_domains);
 173
 174         /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */
 175         __gen6_gt_wait_for_thread_c0(dev_priv);
 176 }
 177
 178 static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
 179 {
 180         u32 gtfifodbg;
 181
 182         gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG);
 183         if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg))
 184                 __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg);
 185 }
 186
 187 static void fw_domains_put_with_fifo(struct drm_i915_private *dev_priv,
 188                                      enum forcewake_domains fw_domains)
 189 {
 190         fw_domains_put(dev_priv, fw_domains);
 191         gen6_gt_check_fifodbg(dev_priv);
 192 }
 193
 194 static inline u32 fifo_free_entries(struct drm_i915_private *dev_priv)
 195 {
 196         u32 count = __raw_i915_read32(dev_priv, GTFIFOCTL);
 197
 198         return count & GT_FIFO_FREE_ENTRIES_MASK;
 199 }
 200
 201 static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
 202 {
 203         int ret = 0;
 204
 205         /* On VLV, FIFO will be shared by both SW and HW.
 206          * So, we need to read the FREE_ENTRIES everytime */
 207         if (IS_VALLEYVIEW(dev_priv->dev))
 208                 dev_priv->uncore.fifo_count = fifo_free_entries(dev_priv);
 209
 210         if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
 211                 int loop = 500;
 212                 u32 fifo = fifo_free_entries(dev_priv);
 213
 214                 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
 215                         udelay(10);
 216                         fifo = fifo_free_entries(dev_priv);
 217                 }
 218                 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
 219                         ++ret;
 220                 dev_priv->uncore.fifo_count = fifo;
 221         }
 222         dev_priv->uncore.fifo_count--;
 223
 224         return ret;
 225 }
 226
 227 static void intel_uncore_fw_release_timer(unsigned long arg)
 228 {
 229         struct intel_uncore_forcewake_domain *domain = (void *)arg;
 230         unsigned long irqflags;
 231
 232         assert_rpm_device_not_suspended(domain->i915);
 233
 234         spin_lock_irqsave(&domain->i915->uncore.lock, irqflags);
 235         if (WARN_ON(domain->wake_count == 0))
 236                 domain->wake_count++;
 237
 238         if (--domain->wake_count == 0)
 239                 domain->i915->uncore.funcs.force_wake_put(domain->i915,
 240                                                           1 << domain->id);
 241
 242         spin_unlock_irqrestore(&domain->i915->uncore.lock, irqflags);
 243 }
 244
 245 void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore)
 246 {
 247         struct drm_i915_private *dev_priv = dev->dev_private;
 248         unsigned long irqflags;
 249         struct intel_uncore_forcewake_domain *domain;
 250         int retry_count = 100;
 251         enum forcewake_domain_id id;
 252         enum forcewake_domains fw = 0, active_domains;
 253
 254         /* Hold uncore.lock across reset to prevent any register access
 255          * with forcewake not set correctly. Wait until all pending
 256          * timers are run before holding.
 257          */
 258         while (1) {
 259                 active_domains = 0;
 260
 261                 for_each_fw_domain(domain, dev_priv, id) {
 262                         if (del_timer_sync(&domain->timer) == 0)
 263                                 continue;
 264
 265                         intel_uncore_fw_release_timer((unsigned long)domain);
 266                 }
 267
 268                 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 269
 270                 for_each_fw_domain(domain, dev_priv, id) {
 271                         if (timer_pending(&domain->timer))
 272                                 active_domains |= (1 << id);
 273                 }
 274
 275                 if (active_domains == 0)
 276                         break;
 277
 278                 if (--retry_count == 0) {
 279                         DRM_ERROR("Timed out waiting for forcewake timers to finish\n");
 280                         break;
 281                 }
 282
 283                 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 284                 cond_resched();
 285         }
 286
 287         WARN_ON(active_domains);
 288
 289         for_each_fw_domain(domain, dev_priv, id)
 290                 if (domain->wake_count)
 291                         fw |= 1 << id;
 292
 293         if (fw)
 294                 dev_priv->uncore.funcs.force_wake_put(dev_priv, fw);
 295
 296         fw_domains_reset(dev_priv, FORCEWAKE_ALL);
 297
 298         if (restore) { /* If reset with a user forcewake, try to restore */
 299                 if (fw)
 300                         dev_priv->uncore.funcs.force_wake_get(dev_priv, fw);
 301
 302                 if (IS_GEN6(dev) || IS_GEN7(dev))
 303                         dev_priv->uncore.fifo_count =
 304                                 fifo_free_entries(dev_priv);
 305         }
 306
 307         if (!restore)
 308                 assert_forcewakes_inactive(dev_priv);
 309
 310         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 311 }
 312
 313 static void intel_uncore_ellc_detect(struct drm_device *dev)
 314 {
 315         struct drm_i915_private *dev_priv = dev->dev_private;
 316
 317         if ((IS_HASWELL(dev) || IS_BROADWELL(dev) ||
 318              INTEL_INFO(dev)->gen >= 9) &&
 319             (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) & EDRAM_ENABLED)) {
 320                 /* The docs do not explain exactly how the calculation can be
 321                  * made. It is somewhat guessable, but for now, it's always
 322                  * 128MB.
 323                  * NB: We can't write IDICR yet because we do not have gt funcs
 324                  * set up */
 325                 dev_priv->ellc_size = 128;
 326                 DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size);
 327         }
 328 }
 329
 330 static bool
 331 fpga_check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
 332 {
 333         u32 dbg;
 334
 335         dbg = __raw_i915_read32(dev_priv, FPGA_DBG);
 336         if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM)))
 337                 return false;
 338
 339         __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 340
 341         return true;
 342 }
 343
 344 static bool
 345 vlv_check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
 346 {
 347         u32 cer;
 348
 349         cer = __raw_i915_read32(dev_priv, CLAIM_ER);
 350         if (likely(!(cer & (CLAIM_ER_OVERFLOW | CLAIM_ER_CTR_MASK))))
 351                 return false;
 352
 353         __raw_i915_write32(dev_priv, CLAIM_ER, CLAIM_ER_CLR);
 354
 355         return true;
 356 }
 357
 358 static bool
 359 check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
 360 {
 361         if (HAS_FPGA_DBG_UNCLAIMED(dev_priv))
 362                 return fpga_check_for_unclaimed_mmio(dev_priv);
 363
 364         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 365                 return vlv_check_for_unclaimed_mmio(dev_priv);
 366
 367         return false;
 368 }
 369
 370 static void __intel_uncore_early_sanitize(struct drm_device *dev,
 371                                           bool restore_forcewake)
 372 {
 373         struct drm_i915_private *dev_priv = dev->dev_private;
 374
 375         /* clear out unclaimed reg detection bit */
 376         if (check_for_unclaimed_mmio(dev_priv))
 377                 DRM_DEBUG("unclaimed mmio detected on uncore init, clearing\n");
 378
 379         /* clear out old GT FIFO errors */
 380         if (IS_GEN6(dev) || IS_GEN7(dev))
 381                 __raw_i915_write32(dev_priv, GTFIFODBG,
 382                                    __raw_i915_read32(dev_priv, GTFIFODBG));
 383
 384         /* WaDisableShadowRegForCpd:chv */
 385         if (IS_CHERRYVIEW(dev)) {
 386                 __raw_i915_write32(dev_priv, GTFIFOCTL,
 387                                    __raw_i915_read32(dev_priv, GTFIFOCTL) |
 388                                    GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
 389                                    GT_FIFO_CTL_RC6_POLICY_STALL);
 390         }
 391
 392         intel_uncore_forcewake_reset(dev, restore_forcewake);
 393 }
 394
 395 void intel_uncore_early_sanitize(struct drm_device *dev, bool restore_forcewake)
 396 {
 397         __intel_uncore_early_sanitize(dev, restore_forcewake);
 398         i915_check_and_clear_faults(dev);
 399 }
 400
 401 void intel_uncore_sanitize(struct drm_device *dev)
 402 {
 403         /* BIOS often leaves RC6 enabled, but disable it for hw init */
 404         intel_disable_gt_powersave(dev);
 405 }
 406
 407 static void __intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
 408                                          enum forcewake_domains fw_domains)
 409 {
 410         struct intel_uncore_forcewake_domain *domain;
 411         enum forcewake_domain_id id;
 412
 413         if (!dev_priv->uncore.funcs.force_wake_get)
 414                 return;
 415
 416         fw_domains &= dev_priv->uncore.fw_domains;
 417
 418         for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) {
 419                 if (domain->wake_count++)
 420                         fw_domains &= ~(1 << id);
 421         }
 422
 423         if (fw_domains)
 424                 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
 425 }
 426
 427 /**
 428  * intel_uncore_forcewake_get - grab forcewake domain references
 429  * @dev_priv: i915 device instance
 430  * @fw_domains: forcewake domains to get reference on
 431  *
 432  * This function can be used get GT's forcewake domain references.
 433  * Normal register access will handle the forcewake domains automatically.
 434  * However if some sequence requires the GT to not power down a particular
 435  * forcewake domains this function should be called at the beginning of the
 436  * sequence. And subsequently the reference should be dropped by symmetric
 437  * call to intel_unforce_forcewake_put(). Usually caller wants all the domains
 438  * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL.
 439  */
 440 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
 441                                 enum forcewake_domains fw_domains)
 442 {
 443         unsigned long irqflags;
 444
 445         if (!dev_priv->uncore.funcs.force_wake_get)
 446                 return;
 447
 448         assert_rpm_wakelock_held(dev_priv);
 449
 450         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 451         __intel_uncore_forcewake_get(dev_priv, fw_domains);
 452         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 453 }
 454
 455 /**
 456  * intel_uncore_forcewake_get__locked - grab forcewake domain references
 457  * @dev_priv: i915 device instance
 458  * @fw_domains: forcewake domains to get reference on
 459  *
 460  * See intel_uncore_forcewake_get(). This variant places the onus
 461  * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
 462  */
 463 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
 464                                         enum forcewake_domains fw_domains)
 465 {
 466         assert_spin_locked(&dev_priv->uncore.lock);
 467
 468         if (!dev_priv->uncore.funcs.force_wake_get)
 469                 return;
 470
 471         __intel_uncore_forcewake_get(dev_priv, fw_domains);
 472 }
 473
 474 static void __intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
 475                                          enum forcewake_domains fw_domains)
 476 {
 477         struct intel_uncore_forcewake_domain *domain;
 478         enum forcewake_domain_id id;
 479
 480         if (!dev_priv->uncore.funcs.force_wake_put)
 481                 return;
 482
 483         fw_domains &= dev_priv->uncore.fw_domains;
 484
 485         for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) {
 486                 if (WARN_ON(domain->wake_count == 0))
 487                         continue;
 488
 489                 if (--domain->wake_count)
 490                         continue;
 491
 492                 domain->wake_count++;
 493                 fw_domain_arm_timer(domain);
 494         }
 495 }
 496
 497 /**
 498  * intel_uncore_forcewake_put - release a forcewake domain reference
 499  * @dev_priv: i915 device instance
 500  * @fw_domains: forcewake domains to put references
 501  *
 502  * This function drops the device-level forcewakes for specified
 503  * domains obtained by intel_uncore_forcewake_get().
 504  */
 505 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
 506                                 enum forcewake_domains fw_domains)
 507 {
 508         unsigned long irqflags;
 509
 510         if (!dev_priv->uncore.funcs.force_wake_put)
 511                 return;
 512
 513         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 514         __intel_uncore_forcewake_put(dev_priv, fw_domains);
 515         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 516 }
 517
 518 /**
 519  * intel_uncore_forcewake_put__locked - grab forcewake domain references
 520  * @dev_priv: i915 device instance
 521  * @fw_domains: forcewake domains to get reference on
 522  *
 523  * See intel_uncore_forcewake_put(). This variant places the onus
 524  * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
 525  */
 526 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
 527                                         enum forcewake_domains fw_domains)
 528 {
 529         assert_spin_locked(&dev_priv->uncore.lock);
 530
 531         if (!dev_priv->uncore.funcs.force_wake_put)
 532                 return;
 533
 534         __intel_uncore_forcewake_put(dev_priv, fw_domains);
 535 }
 536
 537 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv)
 538 {
 539         struct intel_uncore_forcewake_domain *domain;
 540         enum forcewake_domain_id id;
 541
 542         if (!dev_priv->uncore.funcs.force_wake_get)
 543                 return;
 544
 545         for_each_fw_domain(domain, dev_priv, id)
 546                 WARN_ON(domain->wake_count);
 547 }
 548
 549 /* We give fast paths for the really cool registers */
 550 #define NEEDS_FORCE_WAKE(reg) ((reg) < 0x40000)
 551
 552 #define REG_RANGE(reg, start, end) ((reg) >= (start) && (reg) < (end))
 553
 554 #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \
 555         (REG_RANGE((reg), 0x2000, 0x4000) || \
 556          REG_RANGE((reg), 0x5000, 0x8000) || \
 557          REG_RANGE((reg), 0xB000, 0x12000) || \
 558          REG_RANGE((reg), 0x2E000, 0x30000))
 559
 560 #define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg) \
 561         (REG_RANGE((reg), 0x12000, 0x14000) || \
 562          REG_RANGE((reg), 0x22000, 0x24000) || \
 563          REG_RANGE((reg), 0x30000, 0x40000))
 564
 565 #define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \
 566         (REG_RANGE((reg), 0x2000, 0x4000) || \
 567          REG_RANGE((reg), 0x5200, 0x8000) || \
 568          REG_RANGE((reg), 0x8300, 0x8500) || \
 569          REG_RANGE((reg), 0xB000, 0xB480) || \
 570          REG_RANGE((reg), 0xE000, 0xE800))
 571
 572 #define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg) \
 573         (REG_RANGE((reg), 0x8800, 0x8900) || \
 574          REG_RANGE((reg), 0xD000, 0xD800) || \
 575          REG_RANGE((reg), 0x12000, 0x14000) || \
 576          REG_RANGE((reg), 0x1A000, 0x1C000) || \
 577          REG_RANGE((reg), 0x1E800, 0x1EA00) || \
 578          REG_RANGE((reg), 0x30000, 0x38000))
 579
 580 #define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg) \
 581         (REG_RANGE((reg), 0x4000, 0x5000) || \
 582          REG_RANGE((reg), 0x8000, 0x8300) || \
 583          REG_RANGE((reg), 0x8500, 0x8600) || \
 584          REG_RANGE((reg), 0x9000, 0xB000) || \
 585          REG_RANGE((reg), 0xF000, 0x10000))
 586
 587 #define FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) \
 588         REG_RANGE((reg), 0xB00,  0x2000)
 589
 590 #define FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) \
 591         (REG_RANGE((reg), 0x2000, 0x2700) || \
 592          REG_RANGE((reg), 0x3000, 0x4000) || \
 593          REG_RANGE((reg), 0x5200, 0x8000) || \
 594          REG_RANGE((reg), 0x8140, 0x8160) || \
 595          REG_RANGE((reg), 0x8300, 0x8500) || \
 596          REG_RANGE((reg), 0x8C00, 0x8D00) || \
 597          REG_RANGE((reg), 0xB000, 0xB480) || \
 598          REG_RANGE((reg), 0xE000, 0xE900) || \
 599          REG_RANGE((reg), 0x24400, 0x24800))
 600
 601 #define FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) \
 602         (REG_RANGE((reg), 0x8130, 0x8140) || \
 603          REG_RANGE((reg), 0x8800, 0x8A00) || \
 604          REG_RANGE((reg), 0xD000, 0xD800) || \
 605          REG_RANGE((reg), 0x12000, 0x14000) || \
 606          REG_RANGE((reg), 0x1A000, 0x1EA00) || \
 607          REG_RANGE((reg), 0x30000, 0x40000))
 608
 609 #define FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg) \
 610         REG_RANGE((reg), 0x9400, 0x9800)
 611
 612 #define FORCEWAKE_GEN9_BLITTER_RANGE_OFFSET(reg) \
 613         ((reg) < 0x40000 && \
 614          !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) && \
 615          !FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) && \
 616          !FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) && \
 617          !FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg))
 618
 619 static void
 620 ilk_dummy_write(struct drm_i915_private *dev_priv)
 621 {
 622         /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
 623          * the chip from rc6 before touching it for real. MI_MODE is masked,
 624          * hence harmless to write 0 into. */
 625         __raw_i915_write32(dev_priv, MI_MODE, 0);
 626 }
 627
 628 static void
 629 __unclaimed_reg_debug(struct drm_i915_private *dev_priv,
 630                       const i915_reg_t reg,
 631                       const bool read,
 632                       const bool before)
 633 {
 634         /* XXX. We limit the auto arming traces for mmio
 635          * debugs on these platforms. There are just too many
 636          * revealed by these and CI/Bat suffers from the noise.
 637          * Please fix and then re-enable the automatic traces.
 638          */
 639         if (i915.mmio_debug < 2 &&
 640             (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 641                 return;
 642
 643         if (WARN(check_for_unclaimed_mmio(dev_priv),
 644                  "Unclaimed register detected %s %s register 0x%x\n",
 645                  before ? "before" : "after",
 646                  read ? "reading" : "writing to",
 647                  i915_mmio_reg_offset(reg)))
 648                 i915.mmio_debug--; /* Only report the first N failures */
 649 }
 650
 651 static inline void
 652 unclaimed_reg_debug(struct drm_i915_private *dev_priv,
 653                     const i915_reg_t reg,
 654                     const bool read,
 655                     const bool before)
 656 {
 657         if (likely(!i915.mmio_debug))
 658                 return;
 659
 660         __unclaimed_reg_debug(dev_priv, reg, read, before);
 661 }
 662
 663 #define GEN2_READ_HEADER(x) \
 664         u##x val = 0; \
 665         assert_rpm_wakelock_held(dev_priv);
 666
 667 #define GEN2_READ_FOOTER \
 668         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
 669         return val
 670
 671 #define __gen2_read(x) \
 672 static u##x \
 673 gen2_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 674         GEN2_READ_HEADER(x); \
 675         val = __raw_i915_read##x(dev_priv, reg); \
 676         GEN2_READ_FOOTER; \
 677 }
 678
 679 #define __gen5_read(x) \
 680 static u##x \
 681 gen5_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 682         GEN2_READ_HEADER(x); \
 683         ilk_dummy_write(dev_priv); \
 684         val = __raw_i915_read##x(dev_priv, reg); \
 685         GEN2_READ_FOOTER; \
 686 }
 687
 688 __gen5_read(8)
 689 __gen5_read(16)
 690 __gen5_read(32)
 691 __gen5_read(64)
 692 __gen2_read(8)
 693 __gen2_read(16)
 694 __gen2_read(32)
 695 __gen2_read(64)
 696
 697 #undef __gen5_read
 698 #undef __gen2_read
 699
 700 #undef GEN2_READ_FOOTER
 701 #undef GEN2_READ_HEADER
 702
 703 #define GEN6_READ_HEADER(x) \
 704         u32 offset = i915_mmio_reg_offset(reg); \
 705         unsigned long irqflags; \
 706         u##x val = 0; \
 707         assert_rpm_wakelock_held(dev_priv); \
 708         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \
 709         unclaimed_reg_debug(dev_priv, reg, true, true)
 710
 711 #define GEN6_READ_FOOTER \
 712         unclaimed_reg_debug(dev_priv, reg, true, false); \
 713         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
 714         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
 715         return val
 716
 717 static inline void __force_wake_get(struct drm_i915_private *dev_priv,
 718                                     enum forcewake_domains fw_domains)
 719 {
 720         struct intel_uncore_forcewake_domain *domain;
 721         enum forcewake_domain_id id;
 722
 723         if (WARN_ON(!fw_domains))
 724                 return;
 725
 726         /* Ideally GCC would be constant-fold and eliminate this loop */
 727         for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) {
 728                 if (domain->wake_count) {
 729                         fw_domains &= ~(1 << id);
 730                         continue;
 731                 }
 732
 733                 domain->wake_count++;
 734                 fw_domain_arm_timer(domain);
 735         }
 736
 737         if (fw_domains)
 738                 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
 739 }
 740
 741 #define __gen6_read(x) \
 742 static u##x \
 743 gen6_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 744         GEN6_READ_HEADER(x); \
 745         if (NEEDS_FORCE_WAKE(offset)) \
 746                 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
 747         val = __raw_i915_read##x(dev_priv, reg); \
 748         GEN6_READ_FOOTER; \
 749 }
 750
 751 #define __vlv_read(x) \
 752 static u##x \
 753 vlv_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 754         enum forcewake_domains fw_engine = 0; \
 755         GEN6_READ_HEADER(x); \
 756         if (!NEEDS_FORCE_WAKE(offset)) \
 757                 fw_engine = 0; \
 758         else if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(offset)) \
 759                 fw_engine = FORCEWAKE_RENDER; \
 760         else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(offset)) \
 761                 fw_engine = FORCEWAKE_MEDIA; \
 762         if (fw_engine) \
 763                 __force_wake_get(dev_priv, fw_engine); \
 764         val = __raw_i915_read##x(dev_priv, reg); \
 765         GEN6_READ_FOOTER; \
 766 }
 767
 768 #define __chv_read(x) \
 769 static u##x \
 770 chv_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 771         enum forcewake_domains fw_engine = 0; \
 772         GEN6_READ_HEADER(x); \
 773         if (!NEEDS_FORCE_WAKE(offset)) \
 774                 fw_engine = 0; \
 775         else if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(offset)) \
 776                 fw_engine = FORCEWAKE_RENDER; \
 777         else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(offset)) \
 778                 fw_engine = FORCEWAKE_MEDIA; \
 779         else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(offset)) \
 780                 fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
 781         if (fw_engine) \
 782                 __force_wake_get(dev_priv, fw_engine); \
 783         val = __raw_i915_read##x(dev_priv, reg); \
 784         GEN6_READ_FOOTER; \
 785 }
 786
 787 #define SKL_NEEDS_FORCE_WAKE(reg) \
 788         ((reg) < 0x40000 && !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg))
 789
 790 #define __gen9_read(x) \
 791 static u##x \
 792 gen9_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 793         enum forcewake_domains fw_engine; \
 794         GEN6_READ_HEADER(x); \
 795         if (!SKL_NEEDS_FORCE_WAKE(offset)) \
 796                 fw_engine = 0; \
 797         else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(offset)) \
 798                 fw_engine = FORCEWAKE_RENDER; \
 799         else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(offset)) \
 800                 fw_engine = FORCEWAKE_MEDIA; \
 801         else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(offset)) \
 802                 fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
 803         else \
 804                 fw_engine = FORCEWAKE_BLITTER; \
 805         if (fw_engine) \
 806                 __force_wake_get(dev_priv, fw_engine); \
 807         val = __raw_i915_read##x(dev_priv, reg); \
 808         GEN6_READ_FOOTER; \
 809 }
 810
 811 __gen9_read(8)
 812 __gen9_read(16)
 813 __gen9_read(32)
 814 __gen9_read(64)
 815 __chv_read(8)
 816 __chv_read(16)
 817 __chv_read(32)
 818 __chv_read(64)
 819 __vlv_read(8)
 820 __vlv_read(16)
 821 __vlv_read(32)
 822 __vlv_read(64)
 823 __gen6_read(8)
 824 __gen6_read(16)
 825 __gen6_read(32)
 826 __gen6_read(64)
 827
 828 #undef __gen9_read
 829 #undef __chv_read
 830 #undef __vlv_read
 831 #undef __gen6_read
 832 #undef GEN6_READ_FOOTER
 833 #undef GEN6_READ_HEADER
 834
 835 #define VGPU_READ_HEADER(x) \
 836         unsigned long irqflags; \
 837         u##x val = 0; \
 838         assert_rpm_device_not_suspended(dev_priv); \
 839         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
 840
 841 #define VGPU_READ_FOOTER \
 842         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
 843         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
 844         return val
 845
 846 #define __vgpu_read(x) \
 847 static u##x \
 848 vgpu_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 849         VGPU_READ_HEADER(x); \
 850         val = __raw_i915_read##x(dev_priv, reg); \
 851         VGPU_READ_FOOTER; \
 852 }
 853
 854 __vgpu_read(8)
 855 __vgpu_read(16)
 856 __vgpu_read(32)
 857 __vgpu_read(64)
 858
 859 #undef __vgpu_read
 860 #undef VGPU_READ_FOOTER
 861 #undef VGPU_READ_HEADER
 862
 863 #define GEN2_WRITE_HEADER \
 864         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
 865         assert_rpm_wakelock_held(dev_priv); \
 866
 867 #define GEN2_WRITE_FOOTER
 868
 869 #define __gen2_write(x) \
 870 static void \
 871 gen2_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
 872         GEN2_WRITE_HEADER; \
 873         __raw_i915_write##x(dev_priv, reg, val); \
 874         GEN2_WRITE_FOOTER; \
 875 }
 876
 877 #define __gen5_write(x) \
 878 static void \
 879 gen5_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
 880         GEN2_WRITE_HEADER; \
 881         ilk_dummy_write(dev_priv); \
 882         __raw_i915_write##x(dev_priv, reg, val); \
 883         GEN2_WRITE_FOOTER; \
 884 }
 885
 886 __gen5_write(8)
 887 __gen5_write(16)
 888 __gen5_write(32)
 889 __gen5_write(64)
 890 __gen2_write(8)
 891 __gen2_write(16)
 892 __gen2_write(32)
 893 __gen2_write(64)
 894
 895 #undef __gen5_write
 896 #undef __gen2_write
 897
 898 #undef GEN2_WRITE_FOOTER
 899 #undef GEN2_WRITE_HEADER
 900
 901 #define GEN6_WRITE_HEADER \
 902         u32 offset = i915_mmio_reg_offset(reg); \
 903         unsigned long irqflags; \
 904         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
 905         assert_rpm_wakelock_held(dev_priv); \
 906         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \
 907         unclaimed_reg_debug(dev_priv, reg, false, true)
 908
 909 #define GEN6_WRITE_FOOTER \
 910         unclaimed_reg_debug(dev_priv, reg, false, false); \
 911         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
 912
 913 #define __gen6_write(x) \
 914 static void \
 915 gen6_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
 916         u32 __fifo_ret = 0; \
 917         GEN6_WRITE_HEADER; \
 918         if (NEEDS_FORCE_WAKE(offset)) { \
 919                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
 920         } \
 921         __raw_i915_write##x(dev_priv, reg, val); \
 922         if (unlikely(__fifo_ret)) { \
 923                 gen6_gt_check_fifodbg(dev_priv); \
 924         } \
 925         GEN6_WRITE_FOOTER; \
 926 }
 927
 928 #define __hsw_write(x) \
 929 static void \
 930 hsw_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
 931         u32 __fifo_ret = 0; \
 932         GEN6_WRITE_HEADER; \
 933         if (NEEDS_FORCE_WAKE(offset)) { \
 934                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
 935         } \
 936         __raw_i915_write##x(dev_priv, reg, val); \
 937         if (unlikely(__fifo_ret)) { \
 938                 gen6_gt_check_fifodbg(dev_priv); \
 939         } \
 940         GEN6_WRITE_FOOTER; \
 941 }
 942
 943 static const i915_reg_t gen8_shadowed_regs[] = {
 944         FORCEWAKE_MT,
 945         GEN6_RPNSWREQ,
 946         GEN6_RC_VIDEO_FREQ,
 947         RING_TAIL(RENDER_RING_BASE),
 948         RING_TAIL(GEN6_BSD_RING_BASE),
 949         RING_TAIL(VEBOX_RING_BASE),
 950         RING_TAIL(BLT_RING_BASE),
 951         /* TODO: Other registers are not yet used */
 952 };
 953
 954 static bool is_gen8_shadowed(struct drm_i915_private *dev_priv,
 955                              i915_reg_t reg)
 956 {
 957         int i;
 958         for (i = 0; i < ARRAY_SIZE(gen8_shadowed_regs); i++)
 959                 if (i915_mmio_reg_equal(reg, gen8_shadowed_regs[i]))
 960                         return true;
 961
 962         return false;
 963 }
 964
 965 #define __gen8_write(x) \
 966 static void \
 967 gen8_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
 968         GEN6_WRITE_HEADER; \
 969         if (NEEDS_FORCE_WAKE(offset) && !is_gen8_shadowed(dev_priv, reg)) \
 970                 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
 971         __raw_i915_write##x(dev_priv, reg, val); \
 972         GEN6_WRITE_FOOTER; \
 973 }
 974
 975 #define __chv_write(x) \
 976 static void \
 977 chv_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
 978         enum forcewake_domains fw_engine = 0; \
 979         GEN6_WRITE_HEADER; \
 980         if (!NEEDS_FORCE_WAKE(offset) || \
 981             is_gen8_shadowed(dev_priv, reg)) \
 982                 fw_engine = 0; \
 983         else if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(offset)) \
 984                 fw_engine = FORCEWAKE_RENDER; \
 985         else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(offset)) \
 986                 fw_engine = FORCEWAKE_MEDIA; \
 987         else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(offset)) \
 988                 fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
 989         if (fw_engine) \
 990                 __force_wake_get(dev_priv, fw_engine); \
 991         __raw_i915_write##x(dev_priv, reg, val); \
 992         GEN6_WRITE_FOOTER; \
 993 }
 994
 995 static const i915_reg_t gen9_shadowed_regs[] = {
 996         RING_TAIL(RENDER_RING_BASE),
 997         RING_TAIL(GEN6_BSD_RING_BASE),
 998         RING_TAIL(VEBOX_RING_BASE),
 999         RING_TAIL(BLT_RING_BASE),
1000         FORCEWAKE_BLITTER_GEN9,
1001         FORCEWAKE_RENDER_GEN9,
1002         FORCEWAKE_MEDIA_GEN9,
1003         GEN6_RPNSWREQ,
1004         GEN6_RC_VIDEO_FREQ,
1005         /* TODO: Other registers are not yet used */
1006 };
1007
1008 static bool is_gen9_shadowed(struct drm_i915_private *dev_priv,
1009                              i915_reg_t reg)
1010 {
1011         int i;
1012         for (i = 0; i < ARRAY_SIZE(gen9_shadowed_regs); i++)
1013                 if (i915_mmio_reg_equal(reg, gen9_shadowed_regs[i]))
1014                         return true;
1015
1016         return false;
1017 }
1018
1019 #define __gen9_write(x) \
1020 static void \
1021 gen9_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, \
1022                 bool trace) { \
1023         enum forcewake_domains fw_engine; \
1024         GEN6_WRITE_HEADER; \
1025         if (!SKL_NEEDS_FORCE_WAKE(offset) || \
1026             is_gen9_shadowed(dev_priv, reg)) \
1027                 fw_engine = 0; \
1028         else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(offset)) \
1029                 fw_engine = FORCEWAKE_RENDER; \
1030         else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(offset)) \
1031                 fw_engine = FORCEWAKE_MEDIA; \
1032         else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(offset)) \
1033                 fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
1034         else \
1035                 fw_engine = FORCEWAKE_BLITTER; \
1036         if (fw_engine) \
1037                 __force_wake_get(dev_priv, fw_engine); \
1038         __raw_i915_write##x(dev_priv, reg, val); \
1039         GEN6_WRITE_FOOTER; \
1040 }
1041
1042 __gen9_write(8)
1043 __gen9_write(16)
1044 __gen9_write(32)
1045 __gen9_write(64)
1046 __chv_write(8)
1047 __chv_write(16)
1048 __chv_write(32)
1049 __chv_write(64)
1050 __gen8_write(8)
1051 __gen8_write(16)
1052 __gen8_write(32)
1053 __gen8_write(64)
1054 __hsw_write(8)
1055 __hsw_write(16)
1056 __hsw_write(32)
1057 __hsw_write(64)
1058 __gen6_write(8)
1059 __gen6_write(16)
1060 __gen6_write(32)
1061 __gen6_write(64)
1062
1063 #undef __gen9_write
1064 #undef __chv_write
1065 #undef __gen8_write
1066 #undef __hsw_write
1067 #undef __gen6_write
1068 #undef GEN6_WRITE_FOOTER
1069 #undef GEN6_WRITE_HEADER
1070
1071 #define VGPU_WRITE_HEADER \
1072         unsigned long irqflags; \
1073         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1074         assert_rpm_device_not_suspended(dev_priv); \
1075         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
1076
1077 #define VGPU_WRITE_FOOTER \
1078         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
1079
1080 #define __vgpu_write(x) \
1081 static void vgpu_write##x(struct drm_i915_private *dev_priv, \
1082                           i915_reg_t reg, u##x val, bool trace) { \
1083         VGPU_WRITE_HEADER; \
1084         __raw_i915_write##x(dev_priv, reg, val); \
1085         VGPU_WRITE_FOOTER; \
1086 }
1087
1088 __vgpu_write(8)
1089 __vgpu_write(16)
1090 __vgpu_write(32)
1091 __vgpu_write(64)
1092
1093 #undef __vgpu_write
1094 #undef VGPU_WRITE_FOOTER
1095 #undef VGPU_WRITE_HEADER
1096
1097 #define ASSIGN_WRITE_MMIO_VFUNCS(x) \
1098 do { \
1099         dev_priv->uncore.funcs.mmio_writeb = x##_write8; \
1100         dev_priv->uncore.funcs.mmio_writew = x##_write16; \
1101         dev_priv->uncore.funcs.mmio_writel = x##_write32; \
1102         dev_priv->uncore.funcs.mmio_writeq = x##_write64; \
1103 } while (0)
1104
1105 #define ASSIGN_READ_MMIO_VFUNCS(x) \
1106 do { \
1107         dev_priv->uncore.funcs.mmio_readb = x##_read8; \
1108         dev_priv->uncore.funcs.mmio_readw = x##_read16; \
1109         dev_priv->uncore.funcs.mmio_readl = x##_read32; \
1110         dev_priv->uncore.funcs.mmio_readq = x##_read64; \
1111 } while (0)
1112
1113
1114 static void fw_domain_init(struct drm_i915_private *dev_priv,
1115                            enum forcewake_domain_id domain_id,
1116                            i915_reg_t reg_set,
1117                            i915_reg_t reg_ack)
1118 {
1119         struct intel_uncore_forcewake_domain *d;
1120
1121         if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT))
1122                 return;
1123
1124         d = &dev_priv->uncore.fw_domain[domain_id];
1125
1126         WARN_ON(d->wake_count);
1127
1128         d->wake_count = 0;
1129         d->reg_set = reg_set;
1130         d->reg_ack = reg_ack;
1131
1132         if (IS_GEN6(dev_priv)) {
1133                 d->val_reset = 0;
1134                 d->val_set = FORCEWAKE_KERNEL;
1135                 d->val_clear = 0;
1136         } else {
1137                 /* WaRsClearFWBitsAtReset:bdw,skl */
1138                 d->val_reset = _MASKED_BIT_DISABLE(0xffff);
1139                 d->val_set = _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL);
1140                 d->val_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL);
1141         }
1142
1143         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1144                 d->reg_post = FORCEWAKE_ACK_VLV;
1145         else if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv) || IS_GEN8(dev_priv))
1146                 d->reg_post = ECOBUS;
1147
1148         d->i915 = dev_priv;
1149         d->id = domain_id;
1150
1151         setup_timer(&d->timer, intel_uncore_fw_release_timer, (unsigned long)d);
1152
1153         dev_priv->uncore.fw_domains |= (1 << domain_id);
1154
1155         fw_domain_reset(d);
1156 }
1157
1158 static void intel_uncore_fw_domains_init(struct drm_device *dev)
1159 {
1160         struct drm_i915_private *dev_priv = dev->dev_private;
1161
1162         if (INTEL_INFO(dev_priv->dev)->gen <= 5)
1163                 return;
1164
1165         if (IS_GEN9(dev)) {
1166                 dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
1167                 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1168                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1169                                FORCEWAKE_RENDER_GEN9,
1170                                FORCEWAKE_ACK_RENDER_GEN9);
1171                 fw_domain_init(dev_priv, FW_DOMAIN_ID_BLITTER,
1172                                FORCEWAKE_BLITTER_GEN9,
1173                                FORCEWAKE_ACK_BLITTER_GEN9);
1174                 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
1175                                FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
1176         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1177                 dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
1178                 if (!IS_CHERRYVIEW(dev))
1179                         dev_priv->uncore.funcs.force_wake_put =
1180                                 fw_domains_put_with_fifo;
1181                 else
1182                         dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1183                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1184                                FORCEWAKE_VLV, FORCEWAKE_ACK_VLV);
1185                 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
1186                                FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV);
1187         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1188                 dev_priv->uncore.funcs.force_wake_get =
1189                         fw_domains_get_with_thread_status;
1190                 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1191                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1192                                FORCEWAKE_MT, FORCEWAKE_ACK_HSW);
1193         } else if (IS_IVYBRIDGE(dev)) {
1194                 u32 ecobus;
1195
1196                 /* IVB configs may use multi-threaded forcewake */
1197
1198                 /* A small trick here - if the bios hasn't configured
1199                  * MT forcewake, and if the device is in RC6, then
1200                  * force_wake_mt_get will not wake the device and the
1201                  * ECOBUS read will return zero. Which will be
1202                  * (correctly) interpreted by the test below as MT
1203                  * forcewake being disabled.
1204                  */
1205                 dev_priv->uncore.funcs.force_wake_get =
1206                         fw_domains_get_with_thread_status;
1207                 dev_priv->uncore.funcs.force_wake_put =
1208                         fw_domains_put_with_fifo;
1209
1210                 /* We need to init first for ECOBUS access and then
1211                  * determine later if we want to reinit, in case of MT access is
1212                  * not working. In this stage we don't know which flavour this
1213                  * ivb is, so it is better to reset also the gen6 fw registers
1214                  * before the ecobus check.
1215                  */
1216
1217                 __raw_i915_write32(dev_priv, FORCEWAKE, 0);
1218                 __raw_posting_read(dev_priv, ECOBUS);
1219
1220                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1221                                FORCEWAKE_MT, FORCEWAKE_MT_ACK);
1222
1223                 mutex_lock(&dev->struct_mutex);
1224                 fw_domains_get_with_thread_status(dev_priv, FORCEWAKE_ALL);
1225                 ecobus = __raw_i915_read32(dev_priv, ECOBUS);
1226                 fw_domains_put_with_fifo(dev_priv, FORCEWAKE_ALL);
1227                 mutex_unlock(&dev->struct_mutex);
1228
1229                 if (!(ecobus & FORCEWAKE_MT_ENABLE)) {
1230                         DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
1231                         DRM_INFO("when using vblank-synced partial screen updates.\n");
1232                         fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1233                                        FORCEWAKE, FORCEWAKE_ACK);
1234                 }
1235         } else if (IS_GEN6(dev)) {
1236                 dev_priv->uncore.funcs.force_wake_get =
1237                         fw_domains_get_with_thread_status;
1238                 dev_priv->uncore.funcs.force_wake_put =
1239                         fw_domains_put_with_fifo;
1240                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1241                                FORCEWAKE, FORCEWAKE_ACK);
1242         }
1243
1244         /* All future platforms are expected to require complex power gating */
1245         WARN_ON(dev_priv->uncore.fw_domains == 0);
1246 }
1247
1248 void intel_uncore_init(struct drm_device *dev)
1249 {
1250         struct drm_i915_private *dev_priv = dev->dev_private;
1251
1252         i915_check_vgpu(dev);
1253
1254         intel_uncore_ellc_detect(dev);
1255         intel_uncore_fw_domains_init(dev);
1256         __intel_uncore_early_sanitize(dev, false);
1257
1258         dev_priv->uncore.unclaimed_mmio_check = 1;
1259
1260         switch (INTEL_INFO(dev)->gen) {
1261         default:
1262         case 9:
1263                 ASSIGN_WRITE_MMIO_VFUNCS(gen9);
1264                 ASSIGN_READ_MMIO_VFUNCS(gen9);
1265                 break;
1266         case 8:
1267                 if (IS_CHERRYVIEW(dev)) {
1268                         ASSIGN_WRITE_MMIO_VFUNCS(chv);
1269                         ASSIGN_READ_MMIO_VFUNCS(chv);
1270
1271                 } else {
1272                         ASSIGN_WRITE_MMIO_VFUNCS(gen8);
1273                         ASSIGN_READ_MMIO_VFUNCS(gen6);
1274                 }
1275                 break;
1276         case 7:
1277         case 6:
1278                 if (IS_HASWELL(dev)) {
1279                         ASSIGN_WRITE_MMIO_VFUNCS(hsw);
1280                 } else {
1281                         ASSIGN_WRITE_MMIO_VFUNCS(gen6);
1282                 }
1283
1284                 if (IS_VALLEYVIEW(dev)) {
1285                         ASSIGN_READ_MMIO_VFUNCS(vlv);
1286                 } else {
1287                         ASSIGN_READ_MMIO_VFUNCS(gen6);
1288                 }
1289                 break;
1290         case 5:
1291                 ASSIGN_WRITE_MMIO_VFUNCS(gen5);
1292                 ASSIGN_READ_MMIO_VFUNCS(gen5);
1293                 break;
1294         case 4:
1295         case 3:
1296         case 2:
1297                 ASSIGN_WRITE_MMIO_VFUNCS(gen2);
1298                 ASSIGN_READ_MMIO_VFUNCS(gen2);
1299                 break;
1300         }
1301
1302         if (intel_vgpu_active(dev)) {
1303                 ASSIGN_WRITE_MMIO_VFUNCS(vgpu);
1304                 ASSIGN_READ_MMIO_VFUNCS(vgpu);
1305         }
1306
1307         i915_check_and_clear_faults(dev);
1308 }
1309 #undef ASSIGN_WRITE_MMIO_VFUNCS
1310 #undef ASSIGN_READ_MMIO_VFUNCS
1311
1312 void intel_uncore_fini(struct drm_device *dev)
1313 {
1314         /* Paranoia: make sure we have disabled everything before we exit. */
1315         intel_uncore_sanitize(dev);
1316         intel_uncore_forcewake_reset(dev, false);
1317 }
1318
1319 #define GEN_RANGE(l, h) GENMASK(h, l)
1320
1321 static const struct register_whitelist {
1322         i915_reg_t offset_ldw, offset_udw;
1323         uint32_t size;
1324         /* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
1325         uint32_t gen_bitmask;
1326 } whitelist[] = {
1327         { .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
1328           .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
1329           .size = 8, .gen_bitmask = GEN_RANGE(4, 9) },
1330 };
1331
1332 int i915_reg_read_ioctl(struct drm_device *dev,
1333                         void *data, struct drm_file *file)
1334 {
1335         struct drm_i915_private *dev_priv = dev->dev_private;
1336         struct drm_i915_reg_read *reg = data;
1337         struct register_whitelist const *entry = whitelist;
1338         unsigned size;
1339         i915_reg_t offset_ldw, offset_udw;
1340         int i, ret = 0;
1341
1342         for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
1343                 if (i915_mmio_reg_offset(entry->offset_ldw) == (reg->offset & -entry->size) &&
1344                     (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
1345                         break;
1346         }
1347
1348         if (i == ARRAY_SIZE(whitelist))
1349                 return -EINVAL;
1350
1351         /* We use the low bits to encode extra flags as the register should
1352          * be naturally aligned (and those that are not so aligned merely
1353          * limit the available flags for that register).
1354          */
1355         offset_ldw = entry->offset_ldw;
1356         offset_udw = entry->offset_udw;
1357         size = entry->size;
1358         size |= reg->offset ^ i915_mmio_reg_offset(offset_ldw);
1359
1360         intel_runtime_pm_get(dev_priv);
1361
1362         switch (size) {
1363         case 8 | 1:
1364                 reg->val = I915_READ64_2x32(offset_ldw, offset_udw);
1365                 break;
1366         case 8:
1367                 reg->val = I915_READ64(offset_ldw);
1368                 break;
1369         case 4:
1370                 reg->val = I915_READ(offset_ldw);
1371                 break;
1372         case 2:
1373                 reg->val = I915_READ16(offset_ldw);
1374                 break;
1375         case 1:
1376                 reg->val = I915_READ8(offset_ldw);
1377                 break;
1378         default:
1379                 ret = -EINVAL;
1380                 goto out;
1381         }
1382
1383 out:
1384         intel_runtime_pm_put(dev_priv);
1385         return ret;
1386 }
1387
1388 int i915_get_reset_stats_ioctl(struct drm_device *dev,
1389                                void *data, struct drm_file *file)
1390 {
1391         struct drm_i915_private *dev_priv = dev->dev_private;
1392         struct drm_i915_reset_stats *args = data;
1393         struct i915_ctx_hang_stats *hs;
1394         struct intel_context *ctx;
1395         int ret;
1396
1397         if (args->flags || args->pad)
1398                 return -EINVAL;
1399
1400         if (args->ctx_id == DEFAULT_CONTEXT_HANDLE && !capable(CAP_SYS_ADMIN))
1401                 return -EPERM;
1402
1403         ret = mutex_lock_interruptible(&dev->struct_mutex);
1404         if (ret)
1405                 return ret;
1406
1407         ctx = i915_gem_context_get(file->driver_priv, args->ctx_id);
1408         if (IS_ERR(ctx)) {
1409                 mutex_unlock(&dev->struct_mutex);
1410                 return PTR_ERR(ctx);
1411         }
1412         hs = &ctx->hang_stats;
1413
1414         if (capable(CAP_SYS_ADMIN))
1415                 args->reset_count = i915_reset_count(&dev_priv->gpu_error);
1416         else
1417                 args->reset_count = 0;
1418
1419         args->batch_active = hs->batch_active;
1420         args->batch_pending = hs->batch_pending;
1421
1422         mutex_unlock(&dev->struct_mutex);
1423
1424         return 0;
1425 }
1426
1427 static int i915_reset_complete(struct drm_device *dev)
1428 {
1429         u8 gdrst;
1430         pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst);
1431         return (gdrst & GRDOM_RESET_STATUS) == 0;
1432 }
1433
1434 static int i915_do_reset(struct drm_device *dev)
1435 {
1436         /* assert reset for at least 20 usec */
1437         pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1438         udelay(20);
1439         pci_write_config_byte(dev->pdev, I915_GDRST, 0);
1440
1441         return wait_for(i915_reset_complete(dev), 500);
1442 }
1443
1444 static int g4x_reset_complete(struct drm_device *dev)
1445 {
1446         u8 gdrst;
1447         pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst);
1448         return (gdrst & GRDOM_RESET_ENABLE) == 0;
1449 }
1450
1451 static int g33_do_reset(struct drm_device *dev)
1452 {
1453         pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1454         return wait_for(g4x_reset_complete(dev), 500);
1455 }
1456
1457 static int g4x_do_reset(struct drm_device *dev)
1458 {
1459         struct drm_i915_private *dev_priv = dev->dev_private;
1460         int ret;
1461
1462         pci_write_config_byte(dev->pdev, I915_GDRST,
1463                               GRDOM_RENDER | GRDOM_RESET_ENABLE);
1464         ret =  wait_for(g4x_reset_complete(dev), 500);
1465         if (ret)
1466                 return ret;
1467
1468         /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1469         I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE);
1470         POSTING_READ(VDECCLK_GATE_D);
1471
1472         pci_write_config_byte(dev->pdev, I915_GDRST,
1473                               GRDOM_MEDIA | GRDOM_RESET_ENABLE);
1474         ret =  wait_for(g4x_reset_complete(dev), 500);
1475         if (ret)
1476                 return ret;
1477
1478         /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1479         I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE);
1480         POSTING_READ(VDECCLK_GATE_D);
1481
1482         pci_write_config_byte(dev->pdev, I915_GDRST, 0);
1483
1484         return 0;
1485 }
1486
1487 static int ironlake_do_reset(struct drm_device *dev)
1488 {
1489         struct drm_i915_private *dev_priv = dev->dev_private;
1490         int ret;
1491
1492         I915_WRITE(ILK_GDSR,
1493                    ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
1494         ret = wait_for((I915_READ(ILK_GDSR) &
1495                         ILK_GRDOM_RESET_ENABLE) == 0, 500);
1496         if (ret)
1497                 return ret;
1498
1499         I915_WRITE(ILK_GDSR,
1500                    ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
1501         ret = wait_for((I915_READ(ILK_GDSR) &
1502                         ILK_GRDOM_RESET_ENABLE) == 0, 500);
1503         if (ret)
1504                 return ret;
1505
1506         I915_WRITE(ILK_GDSR, 0);
1507
1508         return 0;
1509 }
1510
1511 static int gen6_do_reset(struct drm_device *dev)
1512 {
1513         struct drm_i915_private *dev_priv = dev->dev_private;
1514         int     ret;
1515
1516         /* Reset the chip */
1517
1518         /* GEN6_GDRST is not in the gt power well, no need to check
1519          * for fifo space for the write or forcewake the chip for
1520          * the read
1521          */
1522         __raw_i915_write32(dev_priv, GEN6_GDRST, GEN6_GRDOM_FULL);
1523
1524         /* Spin waiting for the device to ack the reset request */
1525         ret = wait_for((__raw_i915_read32(dev_priv, GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
1526
1527         intel_uncore_forcewake_reset(dev, true);
1528
1529         return ret;
1530 }
1531
1532 static int wait_for_register(struct drm_i915_private *dev_priv,
1533                              i915_reg_t reg,
1534                              const u32 mask,
1535                              const u32 value,
1536                              const unsigned long timeout_ms)
1537 {
1538         return wait_for((I915_READ(reg) & mask) == value, timeout_ms);
1539 }
1540
1541 static int gen8_do_reset(struct drm_device *dev)
1542 {
1543         struct drm_i915_private *dev_priv = dev->dev_private;
1544         struct intel_engine_cs *engine;
1545         int i;
1546
1547         for_each_ring(engine, dev_priv, i) {
1548                 I915_WRITE(RING_RESET_CTL(engine->mmio_base),
1549                            _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET));
1550
1551                 if (wait_for_register(dev_priv,
1552                                       RING_RESET_CTL(engine->mmio_base),
1553                                       RESET_CTL_READY_TO_RESET,
1554                                       RESET_CTL_READY_TO_RESET,
1555                                       700)) {
1556                         DRM_ERROR("%s: reset request timeout\n", engine->name);
1557                         goto not_ready;
1558                 }
1559         }
1560
1561         return gen6_do_reset(dev);
1562
1563 not_ready:
1564         for_each_ring(engine, dev_priv, i)
1565                 I915_WRITE(RING_RESET_CTL(engine->mmio_base),
1566                            _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET));
1567
1568         return -EIO;
1569 }
1570
1571 static int (*intel_get_gpu_reset(struct drm_device *dev))(struct drm_device *)
1572 {
1573         if (!i915.reset)
1574                 return NULL;
1575
1576         if (INTEL_INFO(dev)->gen >= 8)
1577                 return gen8_do_reset;
1578         else if (INTEL_INFO(dev)->gen >= 6)
1579                 return gen6_do_reset;
1580         else if (IS_GEN5(dev))
1581                 return ironlake_do_reset;
1582         else if (IS_G4X(dev))
1583                 return g4x_do_reset;
1584         else if (IS_G33(dev))
1585                 return g33_do_reset;
1586         else if (INTEL_INFO(dev)->gen >= 3)
1587                 return i915_do_reset;
1588         else
1589                 return NULL;
1590 }
1591
1592 int intel_gpu_reset(struct drm_device *dev)
1593 {
1594         struct drm_i915_private *dev_priv = to_i915(dev);
1595         int (*reset)(struct drm_device *);
1596         int ret;
1597
1598         reset = intel_get_gpu_reset(dev);
1599         if (reset == NULL)
1600                 return -ENODEV;
1601
1602         /* If the power well sleeps during the reset, the reset
1603          * request may be dropped and never completes (causing -EIO).
1604          */
1605         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1606         ret = reset(dev);
1607         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1608
1609         return ret;
1610 }
1611
1612 bool intel_has_gpu_reset(struct drm_device *dev)
1613 {
1614         return intel_get_gpu_reset(dev) != NULL;
1615 }
1616
1617 bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv)
1618 {
1619         return check_for_unclaimed_mmio(dev_priv);
1620 }
1621
1622 bool
1623 intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv)
1624 {
1625         if (unlikely(i915.mmio_debug ||
1626                      dev_priv->uncore.unclaimed_mmio_check <= 0))
1627                 return false;
1628
1629         if (unlikely(intel_uncore_unclaimed_mmio(dev_priv))) {
1630                 DRM_DEBUG("Unclaimed register detected, "
1631                           "enabling oneshot unclaimed register reporting. "
1632                           "Please use i915.mmio_debug=N for more information.\n");
1633                 i915.mmio_debug++;
1634                 dev_priv->uncore.unclaimed_mmio_check--;
1635                 return true;
1636         }
1637
1638         return false;
1639 }