2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "intel_drv.h"
26 #include "i915_vgpu.h"
28 #include <linux/pm_runtime.h>
30 #define FORCEWAKE_ACK_TIMEOUT_MS 50
32 #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32((dev_priv__), (reg__))
34 static const char * const forcewake_domain_names[] = {
41 intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id)
43 BUILD_BUG_ON(ARRAY_SIZE(forcewake_domain_names) != FW_DOMAIN_ID_COUNT);
45 if (id >= 0 && id < FW_DOMAIN_ID_COUNT)
46 return forcewake_domain_names[id];
54 fw_domain_reset(const struct intel_uncore_forcewake_domain *d)
56 WARN_ON(!i915_mmio_reg_valid(d->reg_set));
57 __raw_i915_write32(d->i915, d->reg_set, d->val_reset);
61 fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d)
64 hrtimer_start_range_ns(&d->timer,
65 ktime_set(0, NSEC_PER_MSEC),
71 fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d)
73 if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) &
74 FORCEWAKE_KERNEL) == 0,
75 FORCEWAKE_ACK_TIMEOUT_MS))
76 DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n",
77 intel_uncore_forcewake_domain_to_str(d->id));
81 fw_domain_get(const struct intel_uncore_forcewake_domain *d)
83 __raw_i915_write32(d->i915, d->reg_set, d->val_set);
87 fw_domain_wait_ack(const struct intel_uncore_forcewake_domain *d)
89 if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) &
91 FORCEWAKE_ACK_TIMEOUT_MS))
92 DRM_ERROR("%s: timed out waiting for forcewake ack request.\n",
93 intel_uncore_forcewake_domain_to_str(d->id));
97 fw_domain_put(const struct intel_uncore_forcewake_domain *d)
99 __raw_i915_write32(d->i915, d->reg_set, d->val_clear);
103 fw_domain_posting_read(const struct intel_uncore_forcewake_domain *d)
105 /* something from same cacheline, but not from the set register */
106 if (i915_mmio_reg_valid(d->reg_post))
107 __raw_posting_read(d->i915, d->reg_post);
111 fw_domains_get(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
113 struct intel_uncore_forcewake_domain *d;
115 for_each_fw_domain_masked(d, fw_domains, dev_priv) {
116 fw_domain_wait_ack_clear(d);
120 for_each_fw_domain_masked(d, fw_domains, dev_priv)
121 fw_domain_wait_ack(d);
125 fw_domains_put(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
127 struct intel_uncore_forcewake_domain *d;
129 for_each_fw_domain_masked(d, fw_domains, dev_priv) {
131 fw_domain_posting_read(d);
136 fw_domains_posting_read(struct drm_i915_private *dev_priv)
138 struct intel_uncore_forcewake_domain *d;
140 /* No need to do for all, just do for first found */
141 for_each_fw_domain(d, dev_priv) {
142 fw_domain_posting_read(d);
148 fw_domains_reset(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
150 struct intel_uncore_forcewake_domain *d;
152 if (dev_priv->uncore.fw_domains == 0)
155 for_each_fw_domain_masked(d, fw_domains, dev_priv)
158 fw_domains_posting_read(dev_priv);
161 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
163 /* w/a for a sporadic read returning 0 by waiting for the GT
166 if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) &
167 GEN6_GT_THREAD_STATUS_CORE_MASK) == 0, 500))
168 DRM_ERROR("GT thread status wait timed out\n");
171 static void fw_domains_get_with_thread_status(struct drm_i915_private *dev_priv,
172 enum forcewake_domains fw_domains)
174 fw_domains_get(dev_priv, fw_domains);
176 /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */
177 __gen6_gt_wait_for_thread_c0(dev_priv);
180 static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
184 gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG);
185 if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg))
186 __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg);
189 static void fw_domains_put_with_fifo(struct drm_i915_private *dev_priv,
190 enum forcewake_domains fw_domains)
192 fw_domains_put(dev_priv, fw_domains);
193 gen6_gt_check_fifodbg(dev_priv);
196 static inline u32 fifo_free_entries(struct drm_i915_private *dev_priv)
198 u32 count = __raw_i915_read32(dev_priv, GTFIFOCTL);
200 return count & GT_FIFO_FREE_ENTRIES_MASK;
203 static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
207 /* On VLV, FIFO will be shared by both SW and HW.
208 * So, we need to read the FREE_ENTRIES everytime */
209 if (IS_VALLEYVIEW(dev_priv))
210 dev_priv->uncore.fifo_count = fifo_free_entries(dev_priv);
212 if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
214 u32 fifo = fifo_free_entries(dev_priv);
216 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
218 fifo = fifo_free_entries(dev_priv);
220 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
222 dev_priv->uncore.fifo_count = fifo;
224 dev_priv->uncore.fifo_count--;
229 static enum hrtimer_restart
230 intel_uncore_fw_release_timer(struct hrtimer *timer)
232 struct intel_uncore_forcewake_domain *domain =
233 container_of(timer, struct intel_uncore_forcewake_domain, timer);
234 struct drm_i915_private *dev_priv = domain->i915;
235 unsigned long irqflags;
237 assert_rpm_device_not_suspended(dev_priv);
239 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
240 if (WARN_ON(domain->wake_count == 0))
241 domain->wake_count++;
243 if (--domain->wake_count == 0) {
244 dev_priv->uncore.funcs.force_wake_put(dev_priv, domain->mask);
245 dev_priv->uncore.fw_domains_active &= ~domain->mask;
248 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
250 return HRTIMER_NORESTART;
253 void intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv,
256 unsigned long irqflags;
257 struct intel_uncore_forcewake_domain *domain;
258 int retry_count = 100;
259 enum forcewake_domains fw, active_domains;
261 /* Hold uncore.lock across reset to prevent any register access
262 * with forcewake not set correctly. Wait until all pending
263 * timers are run before holding.
268 for_each_fw_domain(domain, dev_priv) {
269 if (hrtimer_cancel(&domain->timer) == 0)
272 intel_uncore_fw_release_timer(&domain->timer);
275 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
277 for_each_fw_domain(domain, dev_priv) {
278 if (hrtimer_active(&domain->timer))
279 active_domains |= domain->mask;
282 if (active_domains == 0)
285 if (--retry_count == 0) {
286 DRM_ERROR("Timed out waiting for forcewake timers to finish\n");
290 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
294 WARN_ON(active_domains);
296 fw = dev_priv->uncore.fw_domains_active;
298 dev_priv->uncore.funcs.force_wake_put(dev_priv, fw);
300 fw_domains_reset(dev_priv, FORCEWAKE_ALL);
302 if (restore) { /* If reset with a user forcewake, try to restore */
304 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw);
306 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv))
307 dev_priv->uncore.fifo_count =
308 fifo_free_entries(dev_priv);
312 assert_forcewakes_inactive(dev_priv);
314 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
317 static u64 gen9_edram_size(struct drm_i915_private *dev_priv)
319 const unsigned int ways[8] = { 4, 8, 12, 16, 16, 16, 16, 16 };
320 const unsigned int sets[4] = { 1, 1, 2, 2 };
321 const u32 cap = dev_priv->edram_cap;
323 return EDRAM_NUM_BANKS(cap) *
324 ways[EDRAM_WAYS_IDX(cap)] *
325 sets[EDRAM_SETS_IDX(cap)] *
329 u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv)
331 if (!HAS_EDRAM(dev_priv))
334 /* The needed capability bits for size calculation
335 * are not there with pre gen9 so return 128MB always.
337 if (INTEL_GEN(dev_priv) < 9)
338 return 128 * 1024 * 1024;
340 return gen9_edram_size(dev_priv);
343 static void intel_uncore_edram_detect(struct drm_i915_private *dev_priv)
345 if (IS_HASWELL(dev_priv) ||
346 IS_BROADWELL(dev_priv) ||
347 INTEL_GEN(dev_priv) >= 9) {
348 dev_priv->edram_cap = __raw_i915_read32(dev_priv,
351 /* NB: We can't write IDICR yet because we do not have gt funcs
354 dev_priv->edram_cap = 0;
357 if (HAS_EDRAM(dev_priv))
358 DRM_INFO("Found %lluMB of eDRAM\n",
359 intel_uncore_edram_size(dev_priv) / (1024 * 1024));
363 fpga_check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
367 dbg = __raw_i915_read32(dev_priv, FPGA_DBG);
368 if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM)))
371 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
377 vlv_check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
381 cer = __raw_i915_read32(dev_priv, CLAIM_ER);
382 if (likely(!(cer & (CLAIM_ER_OVERFLOW | CLAIM_ER_CTR_MASK))))
385 __raw_i915_write32(dev_priv, CLAIM_ER, CLAIM_ER_CLR);
391 check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
393 if (HAS_FPGA_DBG_UNCLAIMED(dev_priv))
394 return fpga_check_for_unclaimed_mmio(dev_priv);
396 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
397 return vlv_check_for_unclaimed_mmio(dev_priv);
402 static void __intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
403 bool restore_forcewake)
405 struct intel_device_info *info = mkwrite_device_info(dev_priv);
407 /* clear out unclaimed reg detection bit */
408 if (check_for_unclaimed_mmio(dev_priv))
409 DRM_DEBUG("unclaimed mmio detected on uncore init, clearing\n");
411 /* clear out old GT FIFO errors */
412 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv))
413 __raw_i915_write32(dev_priv, GTFIFODBG,
414 __raw_i915_read32(dev_priv, GTFIFODBG));
416 /* WaDisableShadowRegForCpd:chv */
417 if (IS_CHERRYVIEW(dev_priv)) {
418 __raw_i915_write32(dev_priv, GTFIFOCTL,
419 __raw_i915_read32(dev_priv, GTFIFOCTL) |
420 GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
421 GT_FIFO_CTL_RC6_POLICY_STALL);
424 /* Enable Decoupled MMIO only on BXT C stepping onwards */
425 if (!IS_BXT_REVID(dev_priv, BXT_REVID_C0, REVID_FOREVER))
426 info->has_decoupled_mmio = false;
428 intel_uncore_forcewake_reset(dev_priv, restore_forcewake);
431 void intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
432 bool restore_forcewake)
434 __intel_uncore_early_sanitize(dev_priv, restore_forcewake);
435 i915_check_and_clear_faults(dev_priv);
438 void intel_uncore_sanitize(struct drm_i915_private *dev_priv)
440 i915.enable_rc6 = sanitize_rc6_option(dev_priv, i915.enable_rc6);
442 /* BIOS often leaves RC6 enabled, but disable it for hw init */
443 intel_sanitize_gt_powersave(dev_priv);
446 static void __intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
447 enum forcewake_domains fw_domains)
449 struct intel_uncore_forcewake_domain *domain;
451 fw_domains &= dev_priv->uncore.fw_domains;
453 for_each_fw_domain_masked(domain, fw_domains, dev_priv) {
454 if (domain->wake_count++)
455 fw_domains &= ~domain->mask;
459 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
460 dev_priv->uncore.fw_domains_active |= fw_domains;
465 * intel_uncore_forcewake_get - grab forcewake domain references
466 * @dev_priv: i915 device instance
467 * @fw_domains: forcewake domains to get reference on
469 * This function can be used get GT's forcewake domain references.
470 * Normal register access will handle the forcewake domains automatically.
471 * However if some sequence requires the GT to not power down a particular
472 * forcewake domains this function should be called at the beginning of the
473 * sequence. And subsequently the reference should be dropped by symmetric
474 * call to intel_unforce_forcewake_put(). Usually caller wants all the domains
475 * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL.
477 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
478 enum forcewake_domains fw_domains)
480 unsigned long irqflags;
482 if (!dev_priv->uncore.funcs.force_wake_get)
485 assert_rpm_wakelock_held(dev_priv);
487 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
488 __intel_uncore_forcewake_get(dev_priv, fw_domains);
489 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
493 * intel_uncore_forcewake_get__locked - grab forcewake domain references
494 * @dev_priv: i915 device instance
495 * @fw_domains: forcewake domains to get reference on
497 * See intel_uncore_forcewake_get(). This variant places the onus
498 * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
500 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
501 enum forcewake_domains fw_domains)
503 assert_spin_locked(&dev_priv->uncore.lock);
505 if (!dev_priv->uncore.funcs.force_wake_get)
508 __intel_uncore_forcewake_get(dev_priv, fw_domains);
511 static void __intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
512 enum forcewake_domains fw_domains)
514 struct intel_uncore_forcewake_domain *domain;
516 fw_domains &= dev_priv->uncore.fw_domains;
518 for_each_fw_domain_masked(domain, fw_domains, dev_priv) {
519 if (WARN_ON(domain->wake_count == 0))
522 if (--domain->wake_count)
525 fw_domain_arm_timer(domain);
530 * intel_uncore_forcewake_put - release a forcewake domain reference
531 * @dev_priv: i915 device instance
532 * @fw_domains: forcewake domains to put references
534 * This function drops the device-level forcewakes for specified
535 * domains obtained by intel_uncore_forcewake_get().
537 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
538 enum forcewake_domains fw_domains)
540 unsigned long irqflags;
542 if (!dev_priv->uncore.funcs.force_wake_put)
545 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
546 __intel_uncore_forcewake_put(dev_priv, fw_domains);
547 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
551 * intel_uncore_forcewake_put__locked - grab forcewake domain references
552 * @dev_priv: i915 device instance
553 * @fw_domains: forcewake domains to get reference on
555 * See intel_uncore_forcewake_put(). This variant places the onus
556 * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
558 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
559 enum forcewake_domains fw_domains)
561 assert_spin_locked(&dev_priv->uncore.lock);
563 if (!dev_priv->uncore.funcs.force_wake_put)
566 __intel_uncore_forcewake_put(dev_priv, fw_domains);
569 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv)
571 if (!dev_priv->uncore.funcs.force_wake_get)
574 WARN_ON(dev_priv->uncore.fw_domains_active);
577 /* We give fast paths for the really cool registers */
578 #define NEEDS_FORCE_WAKE(reg) ((reg) < 0x40000)
580 #define __gen6_reg_read_fw_domains(offset) \
582 enum forcewake_domains __fwd; \
583 if (NEEDS_FORCE_WAKE(offset)) \
584 __fwd = FORCEWAKE_RENDER; \
590 static int fw_range_cmp(u32 offset, const struct intel_forcewake_range *entry)
592 if (offset < entry->start)
594 else if (offset > entry->end)
600 /* Copied and "macroized" from lib/bsearch.c */
601 #define BSEARCH(key, base, num, cmp) ({ \
602 unsigned int start__ = 0, end__ = (num); \
603 typeof(base) result__ = NULL; \
604 while (start__ < end__) { \
605 unsigned int mid__ = start__ + (end__ - start__) / 2; \
606 int ret__ = (cmp)((key), (base) + mid__); \
609 } else if (ret__ > 0) { \
610 start__ = mid__ + 1; \
612 result__ = (base) + mid__; \
619 static enum forcewake_domains
620 find_fw_domain(struct drm_i915_private *dev_priv, u32 offset)
622 const struct intel_forcewake_range *entry;
624 entry = BSEARCH(offset,
625 dev_priv->uncore.fw_domains_table,
626 dev_priv->uncore.fw_domains_table_entries,
629 return entry ? entry->domains : 0;
633 intel_fw_table_check(struct drm_i915_private *dev_priv)
635 const struct intel_forcewake_range *ranges;
636 unsigned int num_ranges;
640 if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG))
643 ranges = dev_priv->uncore.fw_domains_table;
647 num_ranges = dev_priv->uncore.fw_domains_table_entries;
649 for (i = 0, prev = -1; i < num_ranges; i++, ranges++) {
650 WARN_ON_ONCE(IS_GEN9(dev_priv) &&
651 (prev + 1) != (s32)ranges->start);
652 WARN_ON_ONCE(prev >= (s32)ranges->start);
653 prev = ranges->start;
654 WARN_ON_ONCE(prev >= (s32)ranges->end);
659 #define GEN_FW_RANGE(s, e, d) \
660 { .start = (s), .end = (e), .domains = (d) }
662 #define HAS_FWTABLE(dev_priv) \
663 (IS_GEN9(dev_priv) || \
664 IS_CHERRYVIEW(dev_priv) || \
665 IS_VALLEYVIEW(dev_priv))
667 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
668 static const struct intel_forcewake_range __vlv_fw_ranges[] = {
669 GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER),
670 GEN_FW_RANGE(0x5000, 0x7fff, FORCEWAKE_RENDER),
671 GEN_FW_RANGE(0xb000, 0x11fff, FORCEWAKE_RENDER),
672 GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
673 GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_MEDIA),
674 GEN_FW_RANGE(0x2e000, 0x2ffff, FORCEWAKE_RENDER),
675 GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
678 #define __fwtable_reg_read_fw_domains(offset) \
680 enum forcewake_domains __fwd = 0; \
681 if (NEEDS_FORCE_WAKE((offset))) \
682 __fwd = find_fw_domain(dev_priv, offset); \
686 /* *Must* be sorted by offset! See intel_shadow_table_check(). */
687 static const i915_reg_t gen8_shadowed_regs[] = {
688 RING_TAIL(RENDER_RING_BASE), /* 0x2000 (base) */
689 GEN6_RPNSWREQ, /* 0xA008 */
690 GEN6_RC_VIDEO_FREQ, /* 0xA00C */
691 RING_TAIL(GEN6_BSD_RING_BASE), /* 0x12000 (base) */
692 RING_TAIL(VEBOX_RING_BASE), /* 0x1a000 (base) */
693 RING_TAIL(BLT_RING_BASE), /* 0x22000 (base) */
694 /* TODO: Other registers are not yet used */
697 static void intel_shadow_table_check(void)
699 const i915_reg_t *reg = gen8_shadowed_regs;
704 if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG))
707 for (i = 0, prev = -1; i < ARRAY_SIZE(gen8_shadowed_regs); i++, reg++) {
708 offset = i915_mmio_reg_offset(*reg);
709 WARN_ON_ONCE(prev >= (s32)offset);
714 static int mmio_reg_cmp(u32 key, const i915_reg_t *reg)
716 u32 offset = i915_mmio_reg_offset(*reg);
720 else if (key > offset)
726 static bool is_gen8_shadowed(u32 offset)
728 const i915_reg_t *regs = gen8_shadowed_regs;
730 return BSEARCH(offset, regs, ARRAY_SIZE(gen8_shadowed_regs),
734 #define __gen8_reg_write_fw_domains(offset) \
736 enum forcewake_domains __fwd; \
737 if (NEEDS_FORCE_WAKE(offset) && !is_gen8_shadowed(offset)) \
738 __fwd = FORCEWAKE_RENDER; \
744 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
745 static const struct intel_forcewake_range __chv_fw_ranges[] = {
746 GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER),
747 GEN_FW_RANGE(0x4000, 0x4fff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
748 GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
749 GEN_FW_RANGE(0x8000, 0x82ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
750 GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
751 GEN_FW_RANGE(0x8500, 0x85ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
752 GEN_FW_RANGE(0x8800, 0x88ff, FORCEWAKE_MEDIA),
753 GEN_FW_RANGE(0x9000, 0xafff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
754 GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
755 GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA),
756 GEN_FW_RANGE(0xe000, 0xe7ff, FORCEWAKE_RENDER),
757 GEN_FW_RANGE(0xf000, 0xffff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
758 GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
759 GEN_FW_RANGE(0x1a000, 0x1bfff, FORCEWAKE_MEDIA),
760 GEN_FW_RANGE(0x1e800, 0x1e9ff, FORCEWAKE_MEDIA),
761 GEN_FW_RANGE(0x30000, 0x37fff, FORCEWAKE_MEDIA),
764 #define __fwtable_reg_write_fw_domains(offset) \
766 enum forcewake_domains __fwd = 0; \
767 if (NEEDS_FORCE_WAKE((offset)) && !is_gen8_shadowed(offset)) \
768 __fwd = find_fw_domain(dev_priv, offset); \
772 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
773 static const struct intel_forcewake_range __gen9_fw_ranges[] = {
774 GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER),
775 GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */
776 GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
777 GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER),
778 GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
779 GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER),
780 GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
781 GEN_FW_RANGE(0x8000, 0x812f, FORCEWAKE_BLITTER),
782 GEN_FW_RANGE(0x8130, 0x813f, FORCEWAKE_MEDIA),
783 GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
784 GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER),
785 GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
786 GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_BLITTER),
787 GEN_FW_RANGE(0x8800, 0x89ff, FORCEWAKE_MEDIA),
788 GEN_FW_RANGE(0x8a00, 0x8bff, FORCEWAKE_BLITTER),
789 GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
790 GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER),
791 GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
792 GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER),
793 GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
794 GEN_FW_RANGE(0xb480, 0xcfff, FORCEWAKE_BLITTER),
795 GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA),
796 GEN_FW_RANGE(0xd800, 0xdfff, FORCEWAKE_BLITTER),
797 GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER),
798 GEN_FW_RANGE(0xe900, 0x11fff, FORCEWAKE_BLITTER),
799 GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
800 GEN_FW_RANGE(0x14000, 0x19fff, FORCEWAKE_BLITTER),
801 GEN_FW_RANGE(0x1a000, 0x1e9ff, FORCEWAKE_MEDIA),
802 GEN_FW_RANGE(0x1ea00, 0x243ff, FORCEWAKE_BLITTER),
803 GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER),
804 GEN_FW_RANGE(0x24800, 0x2ffff, FORCEWAKE_BLITTER),
805 GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
809 ilk_dummy_write(struct drm_i915_private *dev_priv)
811 /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
812 * the chip from rc6 before touching it for real. MI_MODE is masked,
813 * hence harmless to write 0 into. */
814 __raw_i915_write32(dev_priv, MI_MODE, 0);
818 __unclaimed_reg_debug(struct drm_i915_private *dev_priv,
819 const i915_reg_t reg,
823 if (WARN(check_for_unclaimed_mmio(dev_priv) && !before,
824 "Unclaimed %s register 0x%x\n",
825 read ? "read from" : "write to",
826 i915_mmio_reg_offset(reg)))
827 i915.mmio_debug--; /* Only report the first N failures */
831 unclaimed_reg_debug(struct drm_i915_private *dev_priv,
832 const i915_reg_t reg,
836 if (likely(!i915.mmio_debug))
839 __unclaimed_reg_debug(dev_priv, reg, read, before);
842 static const enum decoupled_power_domain fw2dpd_domain[] = {
843 GEN9_DECOUPLED_PD_RENDER,
844 GEN9_DECOUPLED_PD_BLITTER,
845 GEN9_DECOUPLED_PD_ALL,
846 GEN9_DECOUPLED_PD_MEDIA,
847 GEN9_DECOUPLED_PD_ALL,
848 GEN9_DECOUPLED_PD_ALL,
849 GEN9_DECOUPLED_PD_ALL
853 * Decoupled MMIO access for only 1 DWORD
855 static void __gen9_decoupled_mmio_access(struct drm_i915_private *dev_priv,
857 enum forcewake_domains fw_domain,
858 enum decoupled_ops operation)
860 enum decoupled_power_domain dp_domain;
861 u32 ctrl_reg_data = 0;
863 dp_domain = fw2dpd_domain[fw_domain - 1];
865 ctrl_reg_data |= reg;
866 ctrl_reg_data |= (operation << GEN9_DECOUPLED_OP_SHIFT);
867 ctrl_reg_data |= (dp_domain << GEN9_DECOUPLED_PD_SHIFT);
868 ctrl_reg_data |= GEN9_DECOUPLED_DW1_GO;
869 __raw_i915_write32(dev_priv, GEN9_DECOUPLED_REG0_DW1, ctrl_reg_data);
871 if (wait_for_atomic((__raw_i915_read32(dev_priv,
872 GEN9_DECOUPLED_REG0_DW1) &
873 GEN9_DECOUPLED_DW1_GO) == 0,
874 FORCEWAKE_ACK_TIMEOUT_MS))
875 DRM_ERROR("Decoupled MMIO wait timed out\n");
879 __gen9_decoupled_mmio_read32(struct drm_i915_private *dev_priv,
881 enum forcewake_domains fw_domain)
883 __gen9_decoupled_mmio_access(dev_priv, reg, fw_domain,
884 GEN9_DECOUPLED_OP_READ);
886 return __raw_i915_read32(dev_priv, GEN9_DECOUPLED_REG0_DW0);
890 __gen9_decoupled_mmio_write(struct drm_i915_private *dev_priv,
892 enum forcewake_domains fw_domain)
895 __raw_i915_write32(dev_priv, GEN9_DECOUPLED_REG0_DW0, data);
897 __gen9_decoupled_mmio_access(dev_priv, reg, fw_domain,
898 GEN9_DECOUPLED_OP_WRITE);
902 #define GEN2_READ_HEADER(x) \
904 assert_rpm_wakelock_held(dev_priv);
906 #define GEN2_READ_FOOTER \
907 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
910 #define __gen2_read(x) \
912 gen2_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
913 GEN2_READ_HEADER(x); \
914 val = __raw_i915_read##x(dev_priv, reg); \
918 #define __gen5_read(x) \
920 gen5_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
921 GEN2_READ_HEADER(x); \
922 ilk_dummy_write(dev_priv); \
923 val = __raw_i915_read##x(dev_priv, reg); \
939 #undef GEN2_READ_FOOTER
940 #undef GEN2_READ_HEADER
942 #define GEN6_READ_HEADER(x) \
943 u32 offset = i915_mmio_reg_offset(reg); \
944 unsigned long irqflags; \
946 assert_rpm_wakelock_held(dev_priv); \
947 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \
948 unclaimed_reg_debug(dev_priv, reg, true, true)
950 #define GEN6_READ_FOOTER \
951 unclaimed_reg_debug(dev_priv, reg, true, false); \
952 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
953 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
956 static noinline void ___force_wake_auto(struct drm_i915_private *dev_priv,
957 enum forcewake_domains fw_domains)
959 struct intel_uncore_forcewake_domain *domain;
961 for_each_fw_domain_masked(domain, fw_domains, dev_priv)
962 fw_domain_arm_timer(domain);
964 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
965 dev_priv->uncore.fw_domains_active |= fw_domains;
968 static inline void __force_wake_auto(struct drm_i915_private *dev_priv,
969 enum forcewake_domains fw_domains)
971 if (WARN_ON(!fw_domains))
974 /* Turn on all requested but inactive supported forcewake domains. */
975 fw_domains &= dev_priv->uncore.fw_domains;
976 fw_domains &= ~dev_priv->uncore.fw_domains_active;
979 ___force_wake_auto(dev_priv, fw_domains);
982 #define __gen6_read(x) \
984 gen6_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
985 enum forcewake_domains fw_engine; \
986 GEN6_READ_HEADER(x); \
987 fw_engine = __gen6_reg_read_fw_domains(offset); \
989 __force_wake_auto(dev_priv, fw_engine); \
990 val = __raw_i915_read##x(dev_priv, reg); \
994 #define __fwtable_read(x) \
996 fwtable_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
997 enum forcewake_domains fw_engine; \
998 GEN6_READ_HEADER(x); \
999 fw_engine = __fwtable_reg_read_fw_domains(offset); \
1001 __force_wake_auto(dev_priv, fw_engine); \
1002 val = __raw_i915_read##x(dev_priv, reg); \
1006 #define __gen9_decoupled_read(x) \
1008 gen9_decoupled_read##x(struct drm_i915_private *dev_priv, \
1009 i915_reg_t reg, bool trace) { \
1010 enum forcewake_domains fw_engine; \
1011 GEN6_READ_HEADER(x); \
1012 fw_engine = __fwtable_reg_read_fw_domains(offset); \
1013 if (fw_engine & ~dev_priv->uncore.fw_domains_active) { \
1015 u32 *ptr_data = (u32 *) &val; \
1016 for (i = 0; i < x/32; i++, offset += sizeof(u32), ptr_data++) \
1017 *ptr_data = __gen9_decoupled_mmio_read32(dev_priv, \
1021 val = __raw_i915_read##x(dev_priv, reg); \
1026 __gen9_decoupled_read(32)
1027 __gen9_decoupled_read(64)
1037 #undef __fwtable_read
1039 #undef GEN6_READ_FOOTER
1040 #undef GEN6_READ_HEADER
1042 #define VGPU_READ_HEADER(x) \
1043 unsigned long irqflags; \
1045 assert_rpm_device_not_suspended(dev_priv); \
1046 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
1048 #define VGPU_READ_FOOTER \
1049 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
1050 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
1053 #define __vgpu_read(x) \
1055 vgpu_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
1056 VGPU_READ_HEADER(x); \
1057 val = __raw_i915_read##x(dev_priv, reg); \
1067 #undef VGPU_READ_FOOTER
1068 #undef VGPU_READ_HEADER
1070 #define GEN2_WRITE_HEADER \
1071 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1072 assert_rpm_wakelock_held(dev_priv); \
1074 #define GEN2_WRITE_FOOTER
1076 #define __gen2_write(x) \
1078 gen2_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1079 GEN2_WRITE_HEADER; \
1080 __raw_i915_write##x(dev_priv, reg, val); \
1081 GEN2_WRITE_FOOTER; \
1084 #define __gen5_write(x) \
1086 gen5_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1087 GEN2_WRITE_HEADER; \
1088 ilk_dummy_write(dev_priv); \
1089 __raw_i915_write##x(dev_priv, reg, val); \
1090 GEN2_WRITE_FOOTER; \
1103 #undef GEN2_WRITE_FOOTER
1104 #undef GEN2_WRITE_HEADER
1106 #define GEN6_WRITE_HEADER \
1107 u32 offset = i915_mmio_reg_offset(reg); \
1108 unsigned long irqflags; \
1109 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1110 assert_rpm_wakelock_held(dev_priv); \
1111 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \
1112 unclaimed_reg_debug(dev_priv, reg, false, true)
1114 #define GEN6_WRITE_FOOTER \
1115 unclaimed_reg_debug(dev_priv, reg, false, false); \
1116 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
1118 #define __gen6_write(x) \
1120 gen6_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1121 u32 __fifo_ret = 0; \
1122 GEN6_WRITE_HEADER; \
1123 if (NEEDS_FORCE_WAKE(offset)) { \
1124 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1126 __raw_i915_write##x(dev_priv, reg, val); \
1127 if (unlikely(__fifo_ret)) { \
1128 gen6_gt_check_fifodbg(dev_priv); \
1130 GEN6_WRITE_FOOTER; \
1133 #define __gen8_write(x) \
1135 gen8_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1136 enum forcewake_domains fw_engine; \
1137 GEN6_WRITE_HEADER; \
1138 fw_engine = __gen8_reg_write_fw_domains(offset); \
1140 __force_wake_auto(dev_priv, fw_engine); \
1141 __raw_i915_write##x(dev_priv, reg, val); \
1142 GEN6_WRITE_FOOTER; \
1145 #define __fwtable_write(x) \
1147 fwtable_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1148 enum forcewake_domains fw_engine; \
1149 GEN6_WRITE_HEADER; \
1150 fw_engine = __fwtable_reg_write_fw_domains(offset); \
1152 __force_wake_auto(dev_priv, fw_engine); \
1153 __raw_i915_write##x(dev_priv, reg, val); \
1154 GEN6_WRITE_FOOTER; \
1157 #define __gen9_decoupled_write(x) \
1159 gen9_decoupled_write##x(struct drm_i915_private *dev_priv, \
1160 i915_reg_t reg, u##x val, \
1162 enum forcewake_domains fw_engine; \
1163 GEN6_WRITE_HEADER; \
1164 fw_engine = __fwtable_reg_write_fw_domains(offset); \
1165 if (fw_engine & ~dev_priv->uncore.fw_domains_active) \
1166 __gen9_decoupled_mmio_write(dev_priv, \
1171 __raw_i915_write##x(dev_priv, reg, val); \
1172 GEN6_WRITE_FOOTER; \
1175 __gen9_decoupled_write(32)
1186 #undef __fwtable_write
1189 #undef GEN6_WRITE_FOOTER
1190 #undef GEN6_WRITE_HEADER
1192 #define VGPU_WRITE_HEADER \
1193 unsigned long irqflags; \
1194 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1195 assert_rpm_device_not_suspended(dev_priv); \
1196 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
1198 #define VGPU_WRITE_FOOTER \
1199 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
1201 #define __vgpu_write(x) \
1202 static void vgpu_write##x(struct drm_i915_private *dev_priv, \
1203 i915_reg_t reg, u##x val, bool trace) { \
1204 VGPU_WRITE_HEADER; \
1205 __raw_i915_write##x(dev_priv, reg, val); \
1206 VGPU_WRITE_FOOTER; \
1214 #undef VGPU_WRITE_FOOTER
1215 #undef VGPU_WRITE_HEADER
1217 #define ASSIGN_WRITE_MMIO_VFUNCS(x) \
1219 dev_priv->uncore.funcs.mmio_writeb = x##_write8; \
1220 dev_priv->uncore.funcs.mmio_writew = x##_write16; \
1221 dev_priv->uncore.funcs.mmio_writel = x##_write32; \
1224 #define ASSIGN_READ_MMIO_VFUNCS(x) \
1226 dev_priv->uncore.funcs.mmio_readb = x##_read8; \
1227 dev_priv->uncore.funcs.mmio_readw = x##_read16; \
1228 dev_priv->uncore.funcs.mmio_readl = x##_read32; \
1229 dev_priv->uncore.funcs.mmio_readq = x##_read64; \
1233 static void fw_domain_init(struct drm_i915_private *dev_priv,
1234 enum forcewake_domain_id domain_id,
1238 struct intel_uncore_forcewake_domain *d;
1240 if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT))
1243 d = &dev_priv->uncore.fw_domain[domain_id];
1245 WARN_ON(d->wake_count);
1248 d->reg_set = reg_set;
1249 d->reg_ack = reg_ack;
1251 if (IS_GEN6(dev_priv)) {
1253 d->val_set = FORCEWAKE_KERNEL;
1256 /* WaRsClearFWBitsAtReset:bdw,skl */
1257 d->val_reset = _MASKED_BIT_DISABLE(0xffff);
1258 d->val_set = _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL);
1259 d->val_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL);
1262 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1263 d->reg_post = FORCEWAKE_ACK_VLV;
1264 else if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv) || IS_GEN8(dev_priv))
1265 d->reg_post = ECOBUS;
1270 BUILD_BUG_ON(FORCEWAKE_RENDER != (1 << FW_DOMAIN_ID_RENDER));
1271 BUILD_BUG_ON(FORCEWAKE_BLITTER != (1 << FW_DOMAIN_ID_BLITTER));
1272 BUILD_BUG_ON(FORCEWAKE_MEDIA != (1 << FW_DOMAIN_ID_MEDIA));
1274 d->mask = 1 << domain_id;
1276 hrtimer_init(&d->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1277 d->timer.function = intel_uncore_fw_release_timer;
1279 dev_priv->uncore.fw_domains |= (1 << domain_id);
1284 static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
1286 if (INTEL_INFO(dev_priv)->gen <= 5)
1289 if (IS_GEN9(dev_priv)) {
1290 dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
1291 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1292 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1293 FORCEWAKE_RENDER_GEN9,
1294 FORCEWAKE_ACK_RENDER_GEN9);
1295 fw_domain_init(dev_priv, FW_DOMAIN_ID_BLITTER,
1296 FORCEWAKE_BLITTER_GEN9,
1297 FORCEWAKE_ACK_BLITTER_GEN9);
1298 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
1299 FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
1300 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1301 dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
1302 if (!IS_CHERRYVIEW(dev_priv))
1303 dev_priv->uncore.funcs.force_wake_put =
1304 fw_domains_put_with_fifo;
1306 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1307 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1308 FORCEWAKE_VLV, FORCEWAKE_ACK_VLV);
1309 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
1310 FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV);
1311 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1312 dev_priv->uncore.funcs.force_wake_get =
1313 fw_domains_get_with_thread_status;
1314 if (IS_HASWELL(dev_priv))
1315 dev_priv->uncore.funcs.force_wake_put =
1316 fw_domains_put_with_fifo;
1318 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1319 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1320 FORCEWAKE_MT, FORCEWAKE_ACK_HSW);
1321 } else if (IS_IVYBRIDGE(dev_priv)) {
1324 /* IVB configs may use multi-threaded forcewake */
1326 /* A small trick here - if the bios hasn't configured
1327 * MT forcewake, and if the device is in RC6, then
1328 * force_wake_mt_get will not wake the device and the
1329 * ECOBUS read will return zero. Which will be
1330 * (correctly) interpreted by the test below as MT
1331 * forcewake being disabled.
1333 dev_priv->uncore.funcs.force_wake_get =
1334 fw_domains_get_with_thread_status;
1335 dev_priv->uncore.funcs.force_wake_put =
1336 fw_domains_put_with_fifo;
1338 /* We need to init first for ECOBUS access and then
1339 * determine later if we want to reinit, in case of MT access is
1340 * not working. In this stage we don't know which flavour this
1341 * ivb is, so it is better to reset also the gen6 fw registers
1342 * before the ecobus check.
1345 __raw_i915_write32(dev_priv, FORCEWAKE, 0);
1346 __raw_posting_read(dev_priv, ECOBUS);
1348 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1349 FORCEWAKE_MT, FORCEWAKE_MT_ACK);
1351 spin_lock_irq(&dev_priv->uncore.lock);
1352 fw_domains_get_with_thread_status(dev_priv, FORCEWAKE_ALL);
1353 ecobus = __raw_i915_read32(dev_priv, ECOBUS);
1354 fw_domains_put_with_fifo(dev_priv, FORCEWAKE_ALL);
1355 spin_unlock_irq(&dev_priv->uncore.lock);
1357 if (!(ecobus & FORCEWAKE_MT_ENABLE)) {
1358 DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
1359 DRM_INFO("when using vblank-synced partial screen updates.\n");
1360 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1361 FORCEWAKE, FORCEWAKE_ACK);
1363 } else if (IS_GEN6(dev_priv)) {
1364 dev_priv->uncore.funcs.force_wake_get =
1365 fw_domains_get_with_thread_status;
1366 dev_priv->uncore.funcs.force_wake_put =
1367 fw_domains_put_with_fifo;
1368 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1369 FORCEWAKE, FORCEWAKE_ACK);
1372 /* All future platforms are expected to require complex power gating */
1373 WARN_ON(dev_priv->uncore.fw_domains == 0);
1376 #define ASSIGN_FW_DOMAINS_TABLE(d) \
1378 dev_priv->uncore.fw_domains_table = \
1379 (struct intel_forcewake_range *)(d); \
1380 dev_priv->uncore.fw_domains_table_entries = ARRAY_SIZE((d)); \
1383 void intel_uncore_init(struct drm_i915_private *dev_priv)
1385 i915_check_vgpu(dev_priv);
1387 intel_uncore_edram_detect(dev_priv);
1388 intel_uncore_fw_domains_init(dev_priv);
1389 __intel_uncore_early_sanitize(dev_priv, false);
1391 dev_priv->uncore.unclaimed_mmio_check = 1;
1393 switch (INTEL_INFO(dev_priv)->gen) {
1396 ASSIGN_FW_DOMAINS_TABLE(__gen9_fw_ranges);
1397 ASSIGN_WRITE_MMIO_VFUNCS(fwtable);
1398 ASSIGN_READ_MMIO_VFUNCS(fwtable);
1399 if (HAS_DECOUPLED_MMIO(dev_priv)) {
1400 dev_priv->uncore.funcs.mmio_readl =
1401 gen9_decoupled_read32;
1402 dev_priv->uncore.funcs.mmio_readq =
1403 gen9_decoupled_read64;
1404 dev_priv->uncore.funcs.mmio_writel =
1405 gen9_decoupled_write32;
1409 if (IS_CHERRYVIEW(dev_priv)) {
1410 ASSIGN_FW_DOMAINS_TABLE(__chv_fw_ranges);
1411 ASSIGN_WRITE_MMIO_VFUNCS(fwtable);
1412 ASSIGN_READ_MMIO_VFUNCS(fwtable);
1415 ASSIGN_WRITE_MMIO_VFUNCS(gen8);
1416 ASSIGN_READ_MMIO_VFUNCS(gen6);
1421 ASSIGN_WRITE_MMIO_VFUNCS(gen6);
1423 if (IS_VALLEYVIEW(dev_priv)) {
1424 ASSIGN_FW_DOMAINS_TABLE(__vlv_fw_ranges);
1425 ASSIGN_READ_MMIO_VFUNCS(fwtable);
1427 ASSIGN_READ_MMIO_VFUNCS(gen6);
1431 ASSIGN_WRITE_MMIO_VFUNCS(gen5);
1432 ASSIGN_READ_MMIO_VFUNCS(gen5);
1437 ASSIGN_WRITE_MMIO_VFUNCS(gen2);
1438 ASSIGN_READ_MMIO_VFUNCS(gen2);
1442 intel_fw_table_check(dev_priv);
1443 if (INTEL_GEN(dev_priv) >= 8)
1444 intel_shadow_table_check();
1446 if (intel_vgpu_active(dev_priv)) {
1447 ASSIGN_WRITE_MMIO_VFUNCS(vgpu);
1448 ASSIGN_READ_MMIO_VFUNCS(vgpu);
1451 i915_check_and_clear_faults(dev_priv);
1453 #undef ASSIGN_WRITE_MMIO_VFUNCS
1454 #undef ASSIGN_READ_MMIO_VFUNCS
1456 void intel_uncore_fini(struct drm_i915_private *dev_priv)
1458 /* Paranoia: make sure we have disabled everything before we exit. */
1459 intel_uncore_sanitize(dev_priv);
1460 intel_uncore_forcewake_reset(dev_priv, false);
1463 #define GEN_RANGE(l, h) GENMASK((h) - 1, (l) - 1)
1465 static const struct register_whitelist {
1466 i915_reg_t offset_ldw, offset_udw;
1468 /* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
1469 uint32_t gen_bitmask;
1471 { .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
1472 .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
1473 .size = 8, .gen_bitmask = GEN_RANGE(4, 9) },
1476 int i915_reg_read_ioctl(struct drm_device *dev,
1477 void *data, struct drm_file *file)
1479 struct drm_i915_private *dev_priv = to_i915(dev);
1480 struct drm_i915_reg_read *reg = data;
1481 struct register_whitelist const *entry = whitelist;
1483 i915_reg_t offset_ldw, offset_udw;
1486 for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
1487 if (i915_mmio_reg_offset(entry->offset_ldw) == (reg->offset & -entry->size) &&
1488 (INTEL_INFO(dev_priv)->gen_mask & entry->gen_bitmask))
1492 if (i == ARRAY_SIZE(whitelist))
1495 /* We use the low bits to encode extra flags as the register should
1496 * be naturally aligned (and those that are not so aligned merely
1497 * limit the available flags for that register).
1499 offset_ldw = entry->offset_ldw;
1500 offset_udw = entry->offset_udw;
1502 size |= reg->offset ^ i915_mmio_reg_offset(offset_ldw);
1504 intel_runtime_pm_get(dev_priv);
1508 reg->val = I915_READ64_2x32(offset_ldw, offset_udw);
1511 reg->val = I915_READ64(offset_ldw);
1514 reg->val = I915_READ(offset_ldw);
1517 reg->val = I915_READ16(offset_ldw);
1520 reg->val = I915_READ8(offset_ldw);
1528 intel_runtime_pm_put(dev_priv);
1532 static int i915_reset_complete(struct pci_dev *pdev)
1535 pci_read_config_byte(pdev, I915_GDRST, &gdrst);
1536 return (gdrst & GRDOM_RESET_STATUS) == 0;
1539 static int i915_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask)
1541 struct pci_dev *pdev = dev_priv->drm.pdev;
1543 /* assert reset for at least 20 usec */
1544 pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1546 pci_write_config_byte(pdev, I915_GDRST, 0);
1548 return wait_for(i915_reset_complete(pdev), 500);
1551 static int g4x_reset_complete(struct pci_dev *pdev)
1554 pci_read_config_byte(pdev, I915_GDRST, &gdrst);
1555 return (gdrst & GRDOM_RESET_ENABLE) == 0;
1558 static int g33_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask)
1560 struct pci_dev *pdev = dev_priv->drm.pdev;
1561 pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1562 return wait_for(g4x_reset_complete(pdev), 500);
1565 static int g4x_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask)
1567 struct pci_dev *pdev = dev_priv->drm.pdev;
1570 pci_write_config_byte(pdev, I915_GDRST,
1571 GRDOM_RENDER | GRDOM_RESET_ENABLE);
1572 ret = wait_for(g4x_reset_complete(pdev), 500);
1576 /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1577 I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE);
1578 POSTING_READ(VDECCLK_GATE_D);
1580 pci_write_config_byte(pdev, I915_GDRST,
1581 GRDOM_MEDIA | GRDOM_RESET_ENABLE);
1582 ret = wait_for(g4x_reset_complete(pdev), 500);
1586 /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1587 I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE);
1588 POSTING_READ(VDECCLK_GATE_D);
1590 pci_write_config_byte(pdev, I915_GDRST, 0);
1595 static int ironlake_do_reset(struct drm_i915_private *dev_priv,
1596 unsigned engine_mask)
1600 I915_WRITE(ILK_GDSR,
1601 ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
1602 ret = intel_wait_for_register(dev_priv,
1603 ILK_GDSR, ILK_GRDOM_RESET_ENABLE, 0,
1608 I915_WRITE(ILK_GDSR,
1609 ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
1610 ret = intel_wait_for_register(dev_priv,
1611 ILK_GDSR, ILK_GRDOM_RESET_ENABLE, 0,
1616 I915_WRITE(ILK_GDSR, 0);
1621 /* Reset the hardware domains (GENX_GRDOM_*) specified by mask */
1622 static int gen6_hw_domain_reset(struct drm_i915_private *dev_priv,
1625 /* GEN6_GDRST is not in the gt power well, no need to check
1626 * for fifo space for the write or forcewake the chip for
1629 __raw_i915_write32(dev_priv, GEN6_GDRST, hw_domain_mask);
1631 /* Spin waiting for the device to ack the reset requests */
1632 return intel_wait_for_register_fw(dev_priv,
1633 GEN6_GDRST, hw_domain_mask, 0,
1638 * gen6_reset_engines - reset individual engines
1639 * @dev_priv: i915 device
1640 * @engine_mask: mask of intel_ring_flag() engines or ALL_ENGINES for full reset
1642 * This function will reset the individual engines that are set in engine_mask.
1643 * If you provide ALL_ENGINES as mask, full global domain reset will be issued.
1645 * Note: It is responsibility of the caller to handle the difference between
1646 * asking full domain reset versus reset for all available individual engines.
1648 * Returns 0 on success, nonzero on error.
1650 static int gen6_reset_engines(struct drm_i915_private *dev_priv,
1651 unsigned engine_mask)
1653 struct intel_engine_cs *engine;
1654 const u32 hw_engine_mask[I915_NUM_ENGINES] = {
1655 [RCS] = GEN6_GRDOM_RENDER,
1656 [BCS] = GEN6_GRDOM_BLT,
1657 [VCS] = GEN6_GRDOM_MEDIA,
1658 [VCS2] = GEN8_GRDOM_MEDIA2,
1659 [VECS] = GEN6_GRDOM_VECS,
1664 if (engine_mask == ALL_ENGINES) {
1665 hw_mask = GEN6_GRDOM_FULL;
1670 for_each_engine_masked(engine, dev_priv, engine_mask, tmp)
1671 hw_mask |= hw_engine_mask[engine->id];
1674 ret = gen6_hw_domain_reset(dev_priv, hw_mask);
1676 intel_uncore_forcewake_reset(dev_priv, true);
1682 * intel_wait_for_register_fw - wait until register matches expected state
1683 * @dev_priv: the i915 device
1684 * @reg: the register to read
1685 * @mask: mask to apply to register value
1686 * @value: expected value
1687 * @timeout_ms: timeout in millisecond
1689 * This routine waits until the target register @reg contains the expected
1690 * @value after applying the @mask, i.e. it waits until ::
1692 * (I915_READ_FW(reg) & mask) == value
1694 * Otherwise, the wait will timeout after @timeout_ms milliseconds.
1696 * Note that this routine assumes the caller holds forcewake asserted, it is
1697 * not suitable for very long waits. See intel_wait_for_register() if you
1698 * wish to wait without holding forcewake for the duration (i.e. you expect
1699 * the wait to be slow).
1701 * Returns 0 if the register matches the desired condition, or -ETIMEOUT.
1703 int intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
1707 const unsigned long timeout_ms)
1709 #define done ((I915_READ_FW(reg) & mask) == value)
1710 int ret = wait_for_us(done, 2);
1712 ret = wait_for(done, timeout_ms);
1718 * intel_wait_for_register - wait until register matches expected state
1719 * @dev_priv: the i915 device
1720 * @reg: the register to read
1721 * @mask: mask to apply to register value
1722 * @value: expected value
1723 * @timeout_ms: timeout in millisecond
1725 * This routine waits until the target register @reg contains the expected
1726 * @value after applying the @mask, i.e. it waits until ::
1728 * (I915_READ(reg) & mask) == value
1730 * Otherwise, the wait will timeout after @timeout_ms milliseconds.
1732 * Returns 0 if the register matches the desired condition, or -ETIMEOUT.
1734 int intel_wait_for_register(struct drm_i915_private *dev_priv,
1738 const unsigned long timeout_ms)
1742 intel_uncore_forcewake_for_reg(dev_priv, reg, FW_REG_READ);
1745 intel_uncore_forcewake_get(dev_priv, fw);
1746 ret = wait_for_us((I915_READ_FW(reg) & mask) == value, 2);
1747 intel_uncore_forcewake_put(dev_priv, fw);
1749 ret = wait_for((I915_READ_NOTRACE(reg) & mask) == value,
1755 static int gen8_request_engine_reset(struct intel_engine_cs *engine)
1757 struct drm_i915_private *dev_priv = engine->i915;
1760 I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base),
1761 _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET));
1763 ret = intel_wait_for_register_fw(dev_priv,
1764 RING_RESET_CTL(engine->mmio_base),
1765 RESET_CTL_READY_TO_RESET,
1766 RESET_CTL_READY_TO_RESET,
1769 DRM_ERROR("%s: reset request timeout\n", engine->name);
1774 static void gen8_unrequest_engine_reset(struct intel_engine_cs *engine)
1776 struct drm_i915_private *dev_priv = engine->i915;
1778 I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base),
1779 _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET));
1782 static int gen8_reset_engines(struct drm_i915_private *dev_priv,
1783 unsigned engine_mask)
1785 struct intel_engine_cs *engine;
1788 for_each_engine_masked(engine, dev_priv, engine_mask, tmp)
1789 if (gen8_request_engine_reset(engine))
1792 return gen6_reset_engines(dev_priv, engine_mask);
1795 for_each_engine_masked(engine, dev_priv, engine_mask, tmp)
1796 gen8_unrequest_engine_reset(engine);
1801 typedef int (*reset_func)(struct drm_i915_private *, unsigned engine_mask);
1803 static reset_func intel_get_gpu_reset(struct drm_i915_private *dev_priv)
1808 if (INTEL_INFO(dev_priv)->gen >= 8)
1809 return gen8_reset_engines;
1810 else if (INTEL_INFO(dev_priv)->gen >= 6)
1811 return gen6_reset_engines;
1812 else if (IS_GEN5(dev_priv))
1813 return ironlake_do_reset;
1814 else if (IS_G4X(dev_priv))
1815 return g4x_do_reset;
1816 else if (IS_G33(dev_priv))
1817 return g33_do_reset;
1818 else if (INTEL_INFO(dev_priv)->gen >= 3)
1819 return i915_do_reset;
1824 int intel_gpu_reset(struct drm_i915_private *dev_priv, unsigned engine_mask)
1829 reset = intel_get_gpu_reset(dev_priv);
1833 /* If the power well sleeps during the reset, the reset
1834 * request may be dropped and never completes (causing -EIO).
1836 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1837 ret = reset(dev_priv, engine_mask);
1838 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1843 bool intel_has_gpu_reset(struct drm_i915_private *dev_priv)
1845 return intel_get_gpu_reset(dev_priv) != NULL;
1848 int intel_guc_reset(struct drm_i915_private *dev_priv)
1851 unsigned long irqflags;
1853 if (!HAS_GUC(dev_priv))
1856 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1857 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1859 ret = gen6_hw_domain_reset(dev_priv, GEN9_GRDOM_GUC);
1861 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1862 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1867 bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv)
1869 return check_for_unclaimed_mmio(dev_priv);
1873 intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv)
1875 if (unlikely(i915.mmio_debug ||
1876 dev_priv->uncore.unclaimed_mmio_check <= 0))
1879 if (unlikely(intel_uncore_unclaimed_mmio(dev_priv))) {
1880 DRM_DEBUG("Unclaimed register detected, "
1881 "enabling oneshot unclaimed register reporting. "
1882 "Please use i915.mmio_debug=N for more information.\n");
1884 dev_priv->uncore.unclaimed_mmio_check--;
1891 static enum forcewake_domains
1892 intel_uncore_forcewake_for_read(struct drm_i915_private *dev_priv,
1895 u32 offset = i915_mmio_reg_offset(reg);
1896 enum forcewake_domains fw_domains;
1898 if (HAS_FWTABLE(dev_priv)) {
1899 fw_domains = __fwtable_reg_read_fw_domains(offset);
1900 } else if (INTEL_GEN(dev_priv) >= 6) {
1901 fw_domains = __gen6_reg_read_fw_domains(offset);
1903 WARN_ON(!IS_GEN(dev_priv, 2, 5));
1907 WARN_ON(fw_domains & ~dev_priv->uncore.fw_domains);
1912 static enum forcewake_domains
1913 intel_uncore_forcewake_for_write(struct drm_i915_private *dev_priv,
1916 u32 offset = i915_mmio_reg_offset(reg);
1917 enum forcewake_domains fw_domains;
1919 if (HAS_FWTABLE(dev_priv) && !IS_VALLEYVIEW(dev_priv)) {
1920 fw_domains = __fwtable_reg_write_fw_domains(offset);
1921 } else if (IS_GEN8(dev_priv)) {
1922 fw_domains = __gen8_reg_write_fw_domains(offset);
1923 } else if (IS_GEN(dev_priv, 6, 7)) {
1924 fw_domains = FORCEWAKE_RENDER;
1926 WARN_ON(!IS_GEN(dev_priv, 2, 5));
1930 WARN_ON(fw_domains & ~dev_priv->uncore.fw_domains);
1936 * intel_uncore_forcewake_for_reg - which forcewake domains are needed to access
1938 * @dev_priv: pointer to struct drm_i915_private
1939 * @reg: register in question
1940 * @op: operation bitmask of FW_REG_READ and/or FW_REG_WRITE
1942 * Returns a set of forcewake domains required to be taken with for example
1943 * intel_uncore_forcewake_get for the specified register to be accessible in the
1944 * specified mode (read, write or read/write) with raw mmio accessors.
1946 * NOTE: On Gen6 and Gen7 write forcewake domain (FORCEWAKE_RENDER) requires the
1947 * callers to do FIFO management on their own or risk losing writes.
1949 enum forcewake_domains
1950 intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
1951 i915_reg_t reg, unsigned int op)
1953 enum forcewake_domains fw_domains = 0;
1957 if (intel_vgpu_active(dev_priv))
1960 if (op & FW_REG_READ)
1961 fw_domains = intel_uncore_forcewake_for_read(dev_priv, reg);
1963 if (op & FW_REG_WRITE)
1964 fw_domains |= intel_uncore_forcewake_for_write(dev_priv, reg);