drivers/gpu/drm/i915/intel_uncore.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "i915_drv.h"
  25 #include "intel_drv.h"
  26 #include "i915_vgpu.h"
  27
  28 #include <linux/pm_runtime.h>
  29 #include <linux/bsearch.h>
  30
  31 #define FORCEWAKE_ACK_TIMEOUT_MS 50
  32
  33 #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32((dev_priv__), (reg__))
  34
  35 static const char * const forcewake_domain_names[] = {
  36         "render",
  37         "blitter",
  38         "media",
  39 };
  40
  41 const char *
  42 intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id)
  43 {
  44         BUILD_BUG_ON(ARRAY_SIZE(forcewake_domain_names) != FW_DOMAIN_ID_COUNT);
  45
  46         if (id >= 0 && id < FW_DOMAIN_ID_COUNT)
  47                 return forcewake_domain_names[id];
  48
  49         WARN_ON(id);
  50
  51         return "unknown";
  52 }
  53
  54 static inline void
  55 fw_domain_reset(const struct intel_uncore_forcewake_domain *d)
  56 {
  57         WARN_ON(!i915_mmio_reg_valid(d->reg_set));
  58         __raw_i915_write32(d->i915, d->reg_set, d->val_reset);
  59 }
  60
  61 static inline void
  62 fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d)
  63 {
  64         d->wake_count++;
  65         hrtimer_start_range_ns(&d->timer,
  66                                ktime_set(0, NSEC_PER_MSEC),
  67                                NSEC_PER_MSEC,
  68                                HRTIMER_MODE_REL);
  69 }
  70
  71 static inline void
  72 fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d)
  73 {
  74         if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) &
  75                              FORCEWAKE_KERNEL) == 0,
  76                             FORCEWAKE_ACK_TIMEOUT_MS))
  77                 DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n",
  78                           intel_uncore_forcewake_domain_to_str(d->id));
  79 }
  80
  81 static inline void
  82 fw_domain_get(const struct intel_uncore_forcewake_domain *d)
  83 {
  84         __raw_i915_write32(d->i915, d->reg_set, d->val_set);
  85 }
  86
  87 static inline void
  88 fw_domain_wait_ack(const struct intel_uncore_forcewake_domain *d)
  89 {
  90         if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) &
  91                              FORCEWAKE_KERNEL),
  92                             FORCEWAKE_ACK_TIMEOUT_MS))
  93                 DRM_ERROR("%s: timed out waiting for forcewake ack request.\n",
  94                           intel_uncore_forcewake_domain_to_str(d->id));
  95 }
  96
  97 static inline void
  98 fw_domain_put(const struct intel_uncore_forcewake_domain *d)
  99 {
 100         __raw_i915_write32(d->i915, d->reg_set, d->val_clear);
 101 }
 102
 103 static inline void
 104 fw_domain_posting_read(const struct intel_uncore_forcewake_domain *d)
 105 {
 106         /* something from same cacheline, but not from the set register */
 107         if (i915_mmio_reg_valid(d->reg_post))
 108                 __raw_posting_read(d->i915, d->reg_post);
 109 }
 110
 111 static void
 112 fw_domains_get(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
 113 {
 114         struct intel_uncore_forcewake_domain *d;
 115
 116         for_each_fw_domain_masked(d, fw_domains, dev_priv) {
 117                 fw_domain_wait_ack_clear(d);
 118                 fw_domain_get(d);
 119         }
 120
 121         for_each_fw_domain_masked(d, fw_domains, dev_priv)
 122                 fw_domain_wait_ack(d);
 123 }
 124
 125 static void
 126 fw_domains_put(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
 127 {
 128         struct intel_uncore_forcewake_domain *d;
 129
 130         for_each_fw_domain_masked(d, fw_domains, dev_priv) {
 131                 fw_domain_put(d);
 132                 fw_domain_posting_read(d);
 133         }
 134 }
 135
 136 static void
 137 fw_domains_posting_read(struct drm_i915_private *dev_priv)
 138 {
 139         struct intel_uncore_forcewake_domain *d;
 140
 141         /* No need to do for all, just do for first found */
 142         for_each_fw_domain(d, dev_priv) {
 143                 fw_domain_posting_read(d);
 144                 break;
 145         }
 146 }
 147
 148 static void
 149 fw_domains_reset(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
 150 {
 151         struct intel_uncore_forcewake_domain *d;
 152
 153         if (dev_priv->uncore.fw_domains == 0)
 154                 return;
 155
 156         for_each_fw_domain_masked(d, fw_domains, dev_priv)
 157                 fw_domain_reset(d);
 158
 159         fw_domains_posting_read(dev_priv);
 160 }
 161
 162 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
 163 {
 164         /* w/a for a sporadic read returning 0 by waiting for the GT
 165          * thread to wake up.
 166          */
 167         if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) &
 168                                 GEN6_GT_THREAD_STATUS_CORE_MASK) == 0, 500))
 169                 DRM_ERROR("GT thread status wait timed out\n");
 170 }
 171
 172 static void fw_domains_get_with_thread_status(struct drm_i915_private *dev_priv,
 173                                               enum forcewake_domains fw_domains)
 174 {
 175         fw_domains_get(dev_priv, fw_domains);
 176
 177         /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */
 178         __gen6_gt_wait_for_thread_c0(dev_priv);
 179 }
 180
 181 static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
 182 {
 183         u32 gtfifodbg;
 184
 185         gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG);
 186         if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg))
 187                 __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg);
 188 }
 189
 190 static void fw_domains_put_with_fifo(struct drm_i915_private *dev_priv,
 191                                      enum forcewake_domains fw_domains)
 192 {
 193         fw_domains_put(dev_priv, fw_domains);
 194         gen6_gt_check_fifodbg(dev_priv);
 195 }
 196
 197 static inline u32 fifo_free_entries(struct drm_i915_private *dev_priv)
 198 {
 199         u32 count = __raw_i915_read32(dev_priv, GTFIFOCTL);
 200
 201         return count & GT_FIFO_FREE_ENTRIES_MASK;
 202 }
 203
 204 static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
 205 {
 206         int ret = 0;
 207
 208         /* On VLV, FIFO will be shared by both SW and HW.
 209          * So, we need to read the FREE_ENTRIES everytime */
 210         if (IS_VALLEYVIEW(dev_priv))
 211                 dev_priv->uncore.fifo_count = fifo_free_entries(dev_priv);
 212
 213         if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
 214                 int loop = 500;
 215                 u32 fifo = fifo_free_entries(dev_priv);
 216
 217                 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
 218                         udelay(10);
 219                         fifo = fifo_free_entries(dev_priv);
 220                 }
 221                 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
 222                         ++ret;
 223                 dev_priv->uncore.fifo_count = fifo;
 224         }
 225         dev_priv->uncore.fifo_count--;
 226
 227         return ret;
 228 }
 229
 230 static enum hrtimer_restart
 231 intel_uncore_fw_release_timer(struct hrtimer *timer)
 232 {
 233         struct intel_uncore_forcewake_domain *domain =
 234                container_of(timer, struct intel_uncore_forcewake_domain, timer);
 235         struct drm_i915_private *dev_priv = domain->i915;
 236         unsigned long irqflags;
 237
 238         assert_rpm_device_not_suspended(dev_priv);
 239
 240         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 241         if (WARN_ON(domain->wake_count == 0))
 242                 domain->wake_count++;
 243
 244         if (--domain->wake_count == 0) {
 245                 dev_priv->uncore.funcs.force_wake_put(dev_priv, domain->mask);
 246                 dev_priv->uncore.fw_domains_active &= ~domain->mask;
 247         }
 248
 249         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 250
 251         return HRTIMER_NORESTART;
 252 }
 253
 254 void intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv,
 255                                   bool restore)
 256 {
 257         unsigned long irqflags;
 258         struct intel_uncore_forcewake_domain *domain;
 259         int retry_count = 100;
 260         enum forcewake_domains fw, active_domains;
 261
 262         /* Hold uncore.lock across reset to prevent any register access
 263          * with forcewake not set correctly. Wait until all pending
 264          * timers are run before holding.
 265          */
 266         while (1) {
 267                 active_domains = 0;
 268
 269                 for_each_fw_domain(domain, dev_priv) {
 270                         if (hrtimer_cancel(&domain->timer) == 0)
 271                                 continue;
 272
 273                         intel_uncore_fw_release_timer(&domain->timer);
 274                 }
 275
 276                 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 277
 278                 for_each_fw_domain(domain, dev_priv) {
 279                         if (hrtimer_active(&domain->timer))
 280                                 active_domains |= domain->mask;
 281                 }
 282
 283                 if (active_domains == 0)
 284                         break;
 285
 286                 if (--retry_count == 0) {
 287                         DRM_ERROR("Timed out waiting for forcewake timers to finish\n");
 288                         break;
 289                 }
 290
 291                 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 292                 cond_resched();
 293         }
 294
 295         WARN_ON(active_domains);
 296
 297         fw = dev_priv->uncore.fw_domains_active;
 298         if (fw)
 299                 dev_priv->uncore.funcs.force_wake_put(dev_priv, fw);
 300
 301         fw_domains_reset(dev_priv, FORCEWAKE_ALL);
 302
 303         if (restore) { /* If reset with a user forcewake, try to restore */
 304                 if (fw)
 305                         dev_priv->uncore.funcs.force_wake_get(dev_priv, fw);
 306
 307                 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv))
 308                         dev_priv->uncore.fifo_count =
 309                                 fifo_free_entries(dev_priv);
 310         }
 311
 312         if (!restore)
 313                 assert_forcewakes_inactive(dev_priv);
 314
 315         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 316 }
 317
 318 static u64 gen9_edram_size(struct drm_i915_private *dev_priv)
 319 {
 320         const unsigned int ways[8] = { 4, 8, 12, 16, 16, 16, 16, 16 };
 321         const unsigned int sets[4] = { 1, 1, 2, 2 };
 322         const u32 cap = dev_priv->edram_cap;
 323
 324         return EDRAM_NUM_BANKS(cap) *
 325                 ways[EDRAM_WAYS_IDX(cap)] *
 326                 sets[EDRAM_SETS_IDX(cap)] *
 327                 1024 * 1024;
 328 }
 329
 330 u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv)
 331 {
 332         if (!HAS_EDRAM(dev_priv))
 333                 return 0;
 334
 335         /* The needed capability bits for size calculation
 336          * are not there with pre gen9 so return 128MB always.
 337          */
 338         if (INTEL_GEN(dev_priv) < 9)
 339                 return 128 * 1024 * 1024;
 340
 341         return gen9_edram_size(dev_priv);
 342 }
 343
 344 static void intel_uncore_edram_detect(struct drm_i915_private *dev_priv)
 345 {
 346         if (IS_HASWELL(dev_priv) ||
 347             IS_BROADWELL(dev_priv) ||
 348             INTEL_GEN(dev_priv) >= 9) {
 349                 dev_priv->edram_cap = __raw_i915_read32(dev_priv,
 350                                                         HSW_EDRAM_CAP);
 351
 352                 /* NB: We can't write IDICR yet because we do not have gt funcs
 353                  * set up */
 354         } else {
 355                 dev_priv->edram_cap = 0;
 356         }
 357
 358         if (HAS_EDRAM(dev_priv))
 359                 DRM_INFO("Found %lluMB of eDRAM\n",
 360                          intel_uncore_edram_size(dev_priv) / (1024 * 1024));
 361 }
 362
 363 static bool
 364 fpga_check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
 365 {
 366         u32 dbg;
 367
 368         dbg = __raw_i915_read32(dev_priv, FPGA_DBG);
 369         if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM)))
 370                 return false;
 371
 372         __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 373
 374         return true;
 375 }
 376
 377 static bool
 378 vlv_check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
 379 {
 380         u32 cer;
 381
 382         cer = __raw_i915_read32(dev_priv, CLAIM_ER);
 383         if (likely(!(cer & (CLAIM_ER_OVERFLOW | CLAIM_ER_CTR_MASK))))
 384                 return false;
 385
 386         __raw_i915_write32(dev_priv, CLAIM_ER, CLAIM_ER_CLR);
 387
 388         return true;
 389 }
 390
 391 static bool
 392 check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
 393 {
 394         if (HAS_FPGA_DBG_UNCLAIMED(dev_priv))
 395                 return fpga_check_for_unclaimed_mmio(dev_priv);
 396
 397         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 398                 return vlv_check_for_unclaimed_mmio(dev_priv);
 399
 400         return false;
 401 }
 402
 403 static void __intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
 404                                           bool restore_forcewake)
 405 {
 406         /* clear out unclaimed reg detection bit */
 407         if (check_for_unclaimed_mmio(dev_priv))
 408                 DRM_DEBUG("unclaimed mmio detected on uncore init, clearing\n");
 409
 410         /* clear out old GT FIFO errors */
 411         if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv))
 412                 __raw_i915_write32(dev_priv, GTFIFODBG,
 413                                    __raw_i915_read32(dev_priv, GTFIFODBG));
 414
 415         /* WaDisableShadowRegForCpd:chv */
 416         if (IS_CHERRYVIEW(dev_priv)) {
 417                 __raw_i915_write32(dev_priv, GTFIFOCTL,
 418                                    __raw_i915_read32(dev_priv, GTFIFOCTL) |
 419                                    GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
 420                                    GT_FIFO_CTL_RC6_POLICY_STALL);
 421         }
 422
 423         intel_uncore_forcewake_reset(dev_priv, restore_forcewake);
 424 }
 425
 426 void intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
 427                                  bool restore_forcewake)
 428 {
 429         __intel_uncore_early_sanitize(dev_priv, restore_forcewake);
 430         i915_check_and_clear_faults(dev_priv);
 431 }
 432
 433 void intel_uncore_sanitize(struct drm_i915_private *dev_priv)
 434 {
 435         i915.enable_rc6 = sanitize_rc6_option(dev_priv, i915.enable_rc6);
 436
 437         /* BIOS often leaves RC6 enabled, but disable it for hw init */
 438         intel_sanitize_gt_powersave(dev_priv);
 439 }
 440
 441 static void __intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
 442                                          enum forcewake_domains fw_domains)
 443 {
 444         struct intel_uncore_forcewake_domain *domain;
 445
 446         fw_domains &= dev_priv->uncore.fw_domains;
 447
 448         for_each_fw_domain_masked(domain, fw_domains, dev_priv) {
 449                 if (domain->wake_count++)
 450                         fw_domains &= ~domain->mask;
 451         }
 452
 453         if (fw_domains) {
 454                 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
 455                 dev_priv->uncore.fw_domains_active |= fw_domains;
 456         }
 457 }
 458
 459 /**
 460  * intel_uncore_forcewake_get - grab forcewake domain references
 461  * @dev_priv: i915 device instance
 462  * @fw_domains: forcewake domains to get reference on
 463  *
 464  * This function can be used get GT's forcewake domain references.
 465  * Normal register access will handle the forcewake domains automatically.
 466  * However if some sequence requires the GT to not power down a particular
 467  * forcewake domains this function should be called at the beginning of the
 468  * sequence. And subsequently the reference should be dropped by symmetric
 469  * call to intel_unforce_forcewake_put(). Usually caller wants all the domains
 470  * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL.
 471  */
 472 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
 473                                 enum forcewake_domains fw_domains)
 474 {
 475         unsigned long irqflags;
 476
 477         if (!dev_priv->uncore.funcs.force_wake_get)
 478                 return;
 479
 480         assert_rpm_wakelock_held(dev_priv);
 481
 482         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 483         __intel_uncore_forcewake_get(dev_priv, fw_domains);
 484         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 485 }
 486
 487 /**
 488  * intel_uncore_forcewake_get__locked - grab forcewake domain references
 489  * @dev_priv: i915 device instance
 490  * @fw_domains: forcewake domains to get reference on
 491  *
 492  * See intel_uncore_forcewake_get(). This variant places the onus
 493  * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
 494  */
 495 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
 496                                         enum forcewake_domains fw_domains)
 497 {
 498         assert_spin_locked(&dev_priv->uncore.lock);
 499
 500         if (!dev_priv->uncore.funcs.force_wake_get)
 501                 return;
 502
 503         __intel_uncore_forcewake_get(dev_priv, fw_domains);
 504 }
 505
 506 static void __intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
 507                                          enum forcewake_domains fw_domains)
 508 {
 509         struct intel_uncore_forcewake_domain *domain;
 510
 511         fw_domains &= dev_priv->uncore.fw_domains;
 512
 513         for_each_fw_domain_masked(domain, fw_domains, dev_priv) {
 514                 if (WARN_ON(domain->wake_count == 0))
 515                         continue;
 516
 517                 if (--domain->wake_count)
 518                         continue;
 519
 520                 fw_domain_arm_timer(domain);
 521         }
 522 }
 523
 524 /**
 525  * intel_uncore_forcewake_put - release a forcewake domain reference
 526  * @dev_priv: i915 device instance
 527  * @fw_domains: forcewake domains to put references
 528  *
 529  * This function drops the device-level forcewakes for specified
 530  * domains obtained by intel_uncore_forcewake_get().
 531  */
 532 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
 533                                 enum forcewake_domains fw_domains)
 534 {
 535         unsigned long irqflags;
 536
 537         if (!dev_priv->uncore.funcs.force_wake_put)
 538                 return;
 539
 540         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 541         __intel_uncore_forcewake_put(dev_priv, fw_domains);
 542         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 543 }
 544
 545 /**
 546  * intel_uncore_forcewake_put__locked - grab forcewake domain references
 547  * @dev_priv: i915 device instance
 548  * @fw_domains: forcewake domains to get reference on
 549  *
 550  * See intel_uncore_forcewake_put(). This variant places the onus
 551  * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
 552  */
 553 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
 554                                         enum forcewake_domains fw_domains)
 555 {
 556         assert_spin_locked(&dev_priv->uncore.lock);
 557
 558         if (!dev_priv->uncore.funcs.force_wake_put)
 559                 return;
 560
 561         __intel_uncore_forcewake_put(dev_priv, fw_domains);
 562 }
 563
 564 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv)
 565 {
 566         if (!dev_priv->uncore.funcs.force_wake_get)
 567                 return;
 568
 569         WARN_ON(dev_priv->uncore.fw_domains_active);
 570 }
 571
 572 /* We give fast paths for the really cool registers */
 573 #define NEEDS_FORCE_WAKE(reg) ((reg) < 0x40000)
 574
 575 #define __gen6_reg_read_fw_domains(offset) \
 576 ({ \
 577         enum forcewake_domains __fwd; \
 578         if (NEEDS_FORCE_WAKE(offset)) \
 579                 __fwd = FORCEWAKE_RENDER; \
 580         else \
 581                 __fwd = 0; \
 582         __fwd; \
 583 })
 584
 585 static int fw_range_cmp(const void *key, const void *elt)
 586 {
 587         const struct intel_forcewake_range *entry = elt;
 588         u32 offset = (u32)((unsigned long)key);
 589
 590         if (offset < entry->start)
 591                 return -1;
 592         else if (offset > entry->end)
 593                 return 1;
 594         else
 595                 return 0;
 596 }
 597
 598 static enum forcewake_domains
 599 find_fw_domain(struct drm_i915_private *dev_priv, u32 offset)
 600 {
 601         const struct intel_forcewake_range *table, *entry;
 602         unsigned int num_entries;
 603
 604         table = dev_priv->uncore.fw_domains_table;
 605         num_entries = dev_priv->uncore.fw_domains_table_entries;
 606
 607         entry = bsearch((void *)(unsigned long)offset, (const void *)table,
 608                         num_entries, sizeof(struct intel_forcewake_range),
 609                         fw_range_cmp);
 610
 611         return entry ? entry->domains : 0;
 612 }
 613
 614 static void
 615 intel_fw_table_check(struct drm_i915_private *dev_priv)
 616 {
 617         const struct intel_forcewake_range *ranges;
 618         unsigned int num_ranges;
 619         s32 prev;
 620         unsigned int i;
 621
 622         if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG))
 623                 return;
 624
 625         ranges = dev_priv->uncore.fw_domains_table;
 626         if (!ranges)
 627                 return;
 628
 629         num_ranges = dev_priv->uncore.fw_domains_table_entries;
 630
 631         for (i = 0, prev = -1; i < num_ranges; i++, ranges++) {
 632                 WARN_ON_ONCE(prev >= (s32)ranges->start);
 633                 prev = ranges->start;
 634                 WARN_ON_ONCE(prev >= (s32)ranges->end);
 635                 prev = ranges->end;
 636         }
 637 }
 638
 639 #define GEN_FW_RANGE(s, e, d) \
 640         { .start = (s), .end = (e), .domains = (d) }
 641
 642 #define HAS_FWTABLE(dev_priv) \
 643         (IS_GEN9(dev_priv) || \
 644          IS_CHERRYVIEW(dev_priv) || \
 645          IS_VALLEYVIEW(dev_priv))
 646
 647 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
 648 static const struct intel_forcewake_range __vlv_fw_ranges[] = {
 649         GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER),
 650         GEN_FW_RANGE(0x5000, 0x7fff, FORCEWAKE_RENDER),
 651         GEN_FW_RANGE(0xb000, 0x11fff, FORCEWAKE_RENDER),
 652         GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
 653         GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_MEDIA),
 654         GEN_FW_RANGE(0x2e000, 0x2ffff, FORCEWAKE_RENDER),
 655         GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
 656 };
 657
 658 #define __fwtable_reg_read_fw_domains(offset) \
 659 ({ \
 660         enum forcewake_domains __fwd = 0; \
 661         if (NEEDS_FORCE_WAKE((offset))) \
 662                 __fwd = find_fw_domain(dev_priv, offset); \
 663         __fwd; \
 664 })
 665
 666 static const i915_reg_t gen8_shadowed_regs[] = {
 667         GEN6_RPNSWREQ,
 668         GEN6_RC_VIDEO_FREQ,
 669         RING_TAIL(RENDER_RING_BASE),
 670         RING_TAIL(GEN6_BSD_RING_BASE),
 671         RING_TAIL(VEBOX_RING_BASE),
 672         RING_TAIL(BLT_RING_BASE),
 673         /* TODO: Other registers are not yet used */
 674 };
 675
 676 static bool is_gen8_shadowed(u32 offset)
 677 {
 678         int i;
 679         for (i = 0; i < ARRAY_SIZE(gen8_shadowed_regs); i++)
 680                 if (offset == gen8_shadowed_regs[i].reg)
 681                         return true;
 682
 683         return false;
 684 }
 685
 686 #define __gen8_reg_write_fw_domains(offset) \
 687 ({ \
 688         enum forcewake_domains __fwd; \
 689         if (NEEDS_FORCE_WAKE(offset) && !is_gen8_shadowed(offset)) \
 690                 __fwd = FORCEWAKE_RENDER; \
 691         else \
 692                 __fwd = 0; \
 693         __fwd; \
 694 })
 695
 696 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
 697 static const struct intel_forcewake_range __chv_fw_ranges[] = {
 698         GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER),
 699         GEN_FW_RANGE(0x4000, 0x4fff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
 700         GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
 701         GEN_FW_RANGE(0x8000, 0x82ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
 702         GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
 703         GEN_FW_RANGE(0x8500, 0x85ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
 704         GEN_FW_RANGE(0x8800, 0x88ff, FORCEWAKE_MEDIA),
 705         GEN_FW_RANGE(0x9000, 0xafff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
 706         GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
 707         GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA),
 708         GEN_FW_RANGE(0xe000, 0xe7ff, FORCEWAKE_RENDER),
 709         GEN_FW_RANGE(0xf000, 0xffff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
 710         GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
 711         GEN_FW_RANGE(0x1a000, 0x1bfff, FORCEWAKE_MEDIA),
 712         GEN_FW_RANGE(0x1e800, 0x1e9ff, FORCEWAKE_MEDIA),
 713         GEN_FW_RANGE(0x30000, 0x37fff, FORCEWAKE_MEDIA),
 714 };
 715
 716 #define __fwtable_reg_write_fw_domains(offset) \
 717 ({ \
 718         enum forcewake_domains __fwd = 0; \
 719         if (NEEDS_FORCE_WAKE((offset)) && !is_gen8_shadowed(offset)) \
 720                 __fwd = find_fw_domain(dev_priv, offset); \
 721         __fwd; \
 722 })
 723
 724 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
 725 static const struct intel_forcewake_range __gen9_fw_ranges[] = {
 726         GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER),
 727         GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */
 728         GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
 729         GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER),
 730         GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
 731         GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER),
 732         GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
 733         GEN_FW_RANGE(0x8000, 0x812f, FORCEWAKE_BLITTER),
 734         GEN_FW_RANGE(0x8130, 0x813f, FORCEWAKE_MEDIA),
 735         GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
 736         GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER),
 737         GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
 738         GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_BLITTER),
 739         GEN_FW_RANGE(0x8800, 0x89ff, FORCEWAKE_MEDIA),
 740         GEN_FW_RANGE(0x8a00, 0x8bff, FORCEWAKE_BLITTER),
 741         GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
 742         GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER),
 743         GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
 744         GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER),
 745         GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
 746         GEN_FW_RANGE(0xb480, 0xbfff, FORCEWAKE_BLITTER),
 747         GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA),
 748         GEN_FW_RANGE(0xd800, 0xdfff, FORCEWAKE_BLITTER),
 749         GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER),
 750         GEN_FW_RANGE(0xe900, 0x11fff, FORCEWAKE_BLITTER),
 751         GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
 752         GEN_FW_RANGE(0x14000, 0x19fff, FORCEWAKE_BLITTER),
 753         GEN_FW_RANGE(0x1a000, 0x1e9ff, FORCEWAKE_MEDIA),
 754         GEN_FW_RANGE(0x1ea00, 0x243ff, FORCEWAKE_BLITTER),
 755         GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER),
 756         GEN_FW_RANGE(0x24800, 0x2ffff, FORCEWAKE_BLITTER),
 757         GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
 758 };
 759
 760 static void
 761 ilk_dummy_write(struct drm_i915_private *dev_priv)
 762 {
 763         /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
 764          * the chip from rc6 before touching it for real. MI_MODE is masked,
 765          * hence harmless to write 0 into. */
 766         __raw_i915_write32(dev_priv, MI_MODE, 0);
 767 }
 768
 769 static void
 770 __unclaimed_reg_debug(struct drm_i915_private *dev_priv,
 771                       const i915_reg_t reg,
 772                       const bool read,
 773                       const bool before)
 774 {
 775         if (WARN(check_for_unclaimed_mmio(dev_priv) && !before,
 776                  "Unclaimed %s register 0x%x\n",
 777                  read ? "read from" : "write to",
 778                  i915_mmio_reg_offset(reg)))
 779                 i915.mmio_debug--; /* Only report the first N failures */
 780 }
 781
 782 static inline void
 783 unclaimed_reg_debug(struct drm_i915_private *dev_priv,
 784                     const i915_reg_t reg,
 785                     const bool read,
 786                     const bool before)
 787 {
 788         if (likely(!i915.mmio_debug))
 789                 return;
 790
 791         __unclaimed_reg_debug(dev_priv, reg, read, before);
 792 }
 793
 794 #define GEN2_READ_HEADER(x) \
 795         u##x val = 0; \
 796         assert_rpm_wakelock_held(dev_priv);
 797
 798 #define GEN2_READ_FOOTER \
 799         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
 800         return val
 801
 802 #define __gen2_read(x) \
 803 static u##x \
 804 gen2_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 805         GEN2_READ_HEADER(x); \
 806         val = __raw_i915_read##x(dev_priv, reg); \
 807         GEN2_READ_FOOTER; \
 808 }
 809
 810 #define __gen5_read(x) \
 811 static u##x \
 812 gen5_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 813         GEN2_READ_HEADER(x); \
 814         ilk_dummy_write(dev_priv); \
 815         val = __raw_i915_read##x(dev_priv, reg); \
 816         GEN2_READ_FOOTER; \
 817 }
 818
 819 __gen5_read(8)
 820 __gen5_read(16)
 821 __gen5_read(32)
 822 __gen5_read(64)
 823 __gen2_read(8)
 824 __gen2_read(16)
 825 __gen2_read(32)
 826 __gen2_read(64)
 827
 828 #undef __gen5_read
 829 #undef __gen2_read
 830
 831 #undef GEN2_READ_FOOTER
 832 #undef GEN2_READ_HEADER
 833
 834 #define GEN6_READ_HEADER(x) \
 835         u32 offset = i915_mmio_reg_offset(reg); \
 836         unsigned long irqflags; \
 837         u##x val = 0; \
 838         assert_rpm_wakelock_held(dev_priv); \
 839         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \
 840         unclaimed_reg_debug(dev_priv, reg, true, true)
 841
 842 #define GEN6_READ_FOOTER \
 843         unclaimed_reg_debug(dev_priv, reg, true, false); \
 844         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
 845         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
 846         return val
 847
 848 static noinline void ___force_wake_auto(struct drm_i915_private *dev_priv,
 849                                         enum forcewake_domains fw_domains)
 850 {
 851         struct intel_uncore_forcewake_domain *domain;
 852
 853         for_each_fw_domain_masked(domain, fw_domains, dev_priv)
 854                 fw_domain_arm_timer(domain);
 855
 856         dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
 857         dev_priv->uncore.fw_domains_active |= fw_domains;
 858 }
 859
 860 static inline void __force_wake_auto(struct drm_i915_private *dev_priv,
 861                                      enum forcewake_domains fw_domains)
 862 {
 863         if (WARN_ON(!fw_domains))
 864                 return;
 865
 866         /* Turn on all requested but inactive supported forcewake domains. */
 867         fw_domains &= dev_priv->uncore.fw_domains;
 868         fw_domains &= ~dev_priv->uncore.fw_domains_active;
 869
 870         if (fw_domains)
 871                 ___force_wake_auto(dev_priv, fw_domains);
 872 }
 873
 874 #define __gen6_read(x) \
 875 static u##x \
 876 gen6_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 877         enum forcewake_domains fw_engine; \
 878         GEN6_READ_HEADER(x); \
 879         fw_engine = __gen6_reg_read_fw_domains(offset); \
 880         if (fw_engine) \
 881                 __force_wake_auto(dev_priv, fw_engine); \
 882         val = __raw_i915_read##x(dev_priv, reg); \
 883         GEN6_READ_FOOTER; \
 884 }
 885
 886 #define __fwtable_read(x) \
 887 static u##x \
 888 fwtable_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 889         enum forcewake_domains fw_engine; \
 890         GEN6_READ_HEADER(x); \
 891         fw_engine = __fwtable_reg_read_fw_domains(offset); \
 892         if (fw_engine) \
 893                 __force_wake_auto(dev_priv, fw_engine); \
 894         val = __raw_i915_read##x(dev_priv, reg); \
 895         GEN6_READ_FOOTER; \
 896 }
 897
 898 __fwtable_read(8)
 899 __fwtable_read(16)
 900 __fwtable_read(32)
 901 __fwtable_read(64)
 902 __gen6_read(8)
 903 __gen6_read(16)
 904 __gen6_read(32)
 905 __gen6_read(64)
 906
 907 #undef __fwtable_read
 908 #undef __gen6_read
 909 #undef GEN6_READ_FOOTER
 910 #undef GEN6_READ_HEADER
 911
 912 #define VGPU_READ_HEADER(x) \
 913         unsigned long irqflags; \
 914         u##x val = 0; \
 915         assert_rpm_device_not_suspended(dev_priv); \
 916         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
 917
 918 #define VGPU_READ_FOOTER \
 919         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
 920         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
 921         return val
 922
 923 #define __vgpu_read(x) \
 924 static u##x \
 925 vgpu_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 926         VGPU_READ_HEADER(x); \
 927         val = __raw_i915_read##x(dev_priv, reg); \
 928         VGPU_READ_FOOTER; \
 929 }
 930
 931 __vgpu_read(8)
 932 __vgpu_read(16)
 933 __vgpu_read(32)
 934 __vgpu_read(64)
 935
 936 #undef __vgpu_read
 937 #undef VGPU_READ_FOOTER
 938 #undef VGPU_READ_HEADER
 939
 940 #define GEN2_WRITE_HEADER \
 941         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
 942         assert_rpm_wakelock_held(dev_priv); \
 943
 944 #define GEN2_WRITE_FOOTER
 945
 946 #define __gen2_write(x) \
 947 static void \
 948 gen2_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
 949         GEN2_WRITE_HEADER; \
 950         __raw_i915_write##x(dev_priv, reg, val); \
 951         GEN2_WRITE_FOOTER; \
 952 }
 953
 954 #define __gen5_write(x) \
 955 static void \
 956 gen5_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
 957         GEN2_WRITE_HEADER; \
 958         ilk_dummy_write(dev_priv); \
 959         __raw_i915_write##x(dev_priv, reg, val); \
 960         GEN2_WRITE_FOOTER; \
 961 }
 962
 963 __gen5_write(8)
 964 __gen5_write(16)
 965 __gen5_write(32)
 966 __gen2_write(8)
 967 __gen2_write(16)
 968 __gen2_write(32)
 969
 970 #undef __gen5_write
 971 #undef __gen2_write
 972
 973 #undef GEN2_WRITE_FOOTER
 974 #undef GEN2_WRITE_HEADER
 975
 976 #define GEN6_WRITE_HEADER \
 977         u32 offset = i915_mmio_reg_offset(reg); \
 978         unsigned long irqflags; \
 979         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
 980         assert_rpm_wakelock_held(dev_priv); \
 981         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \
 982         unclaimed_reg_debug(dev_priv, reg, false, true)
 983
 984 #define GEN6_WRITE_FOOTER \
 985         unclaimed_reg_debug(dev_priv, reg, false, false); \
 986         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
 987
 988 #define __gen6_write(x) \
 989 static void \
 990 gen6_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
 991         u32 __fifo_ret = 0; \
 992         GEN6_WRITE_HEADER; \
 993         if (NEEDS_FORCE_WAKE(offset)) { \
 994                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
 995         } \
 996         __raw_i915_write##x(dev_priv, reg, val); \
 997         if (unlikely(__fifo_ret)) { \
 998                 gen6_gt_check_fifodbg(dev_priv); \
 999         } \
1000         GEN6_WRITE_FOOTER; \
1001 }
1002
1003 #define __gen8_write(x) \
1004 static void \
1005 gen8_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1006         enum forcewake_domains fw_engine; \
1007         GEN6_WRITE_HEADER; \
1008         fw_engine = __gen8_reg_write_fw_domains(offset); \
1009         if (fw_engine) \
1010                 __force_wake_auto(dev_priv, fw_engine); \
1011         __raw_i915_write##x(dev_priv, reg, val); \
1012         GEN6_WRITE_FOOTER; \
1013 }
1014
1015 #define __fwtable_write(x) \
1016 static void \
1017 fwtable_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1018         enum forcewake_domains fw_engine; \
1019         GEN6_WRITE_HEADER; \
1020         fw_engine = __fwtable_reg_write_fw_domains(offset); \
1021         if (fw_engine) \
1022                 __force_wake_auto(dev_priv, fw_engine); \
1023         __raw_i915_write##x(dev_priv, reg, val); \
1024         GEN6_WRITE_FOOTER; \
1025 }
1026
1027 __fwtable_write(8)
1028 __fwtable_write(16)
1029 __fwtable_write(32)
1030 __gen8_write(8)
1031 __gen8_write(16)
1032 __gen8_write(32)
1033 __gen6_write(8)
1034 __gen6_write(16)
1035 __gen6_write(32)
1036
1037 #undef __fwtable_write
1038 #undef __gen8_write
1039 #undef __gen6_write
1040 #undef GEN6_WRITE_FOOTER
1041 #undef GEN6_WRITE_HEADER
1042
1043 #define VGPU_WRITE_HEADER \
1044         unsigned long irqflags; \
1045         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1046         assert_rpm_device_not_suspended(dev_priv); \
1047         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
1048
1049 #define VGPU_WRITE_FOOTER \
1050         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
1051
1052 #define __vgpu_write(x) \
1053 static void vgpu_write##x(struct drm_i915_private *dev_priv, \
1054                           i915_reg_t reg, u##x val, bool trace) { \
1055         VGPU_WRITE_HEADER; \
1056         __raw_i915_write##x(dev_priv, reg, val); \
1057         VGPU_WRITE_FOOTER; \
1058 }
1059
1060 __vgpu_write(8)
1061 __vgpu_write(16)
1062 __vgpu_write(32)
1063
1064 #undef __vgpu_write
1065 #undef VGPU_WRITE_FOOTER
1066 #undef VGPU_WRITE_HEADER
1067
1068 #define ASSIGN_WRITE_MMIO_VFUNCS(x) \
1069 do { \
1070         dev_priv->uncore.funcs.mmio_writeb = x##_write8; \
1071         dev_priv->uncore.funcs.mmio_writew = x##_write16; \
1072         dev_priv->uncore.funcs.mmio_writel = x##_write32; \
1073 } while (0)
1074
1075 #define ASSIGN_READ_MMIO_VFUNCS(x) \
1076 do { \
1077         dev_priv->uncore.funcs.mmio_readb = x##_read8; \
1078         dev_priv->uncore.funcs.mmio_readw = x##_read16; \
1079         dev_priv->uncore.funcs.mmio_readl = x##_read32; \
1080         dev_priv->uncore.funcs.mmio_readq = x##_read64; \
1081 } while (0)
1082
1083
1084 static void fw_domain_init(struct drm_i915_private *dev_priv,
1085                            enum forcewake_domain_id domain_id,
1086                            i915_reg_t reg_set,
1087                            i915_reg_t reg_ack)
1088 {
1089         struct intel_uncore_forcewake_domain *d;
1090
1091         if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT))
1092                 return;
1093
1094         d = &dev_priv->uncore.fw_domain[domain_id];
1095
1096         WARN_ON(d->wake_count);
1097
1098         d->wake_count = 0;
1099         d->reg_set = reg_set;
1100         d->reg_ack = reg_ack;
1101
1102         if (IS_GEN6(dev_priv)) {
1103                 d->val_reset = 0;
1104                 d->val_set = FORCEWAKE_KERNEL;
1105                 d->val_clear = 0;
1106         } else {
1107                 /* WaRsClearFWBitsAtReset:bdw,skl */
1108                 d->val_reset = _MASKED_BIT_DISABLE(0xffff);
1109                 d->val_set = _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL);
1110                 d->val_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL);
1111         }
1112
1113         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1114                 d->reg_post = FORCEWAKE_ACK_VLV;
1115         else if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv) || IS_GEN8(dev_priv))
1116                 d->reg_post = ECOBUS;
1117
1118         d->i915 = dev_priv;
1119         d->id = domain_id;
1120
1121         BUILD_BUG_ON(FORCEWAKE_RENDER != (1 << FW_DOMAIN_ID_RENDER));
1122         BUILD_BUG_ON(FORCEWAKE_BLITTER != (1 << FW_DOMAIN_ID_BLITTER));
1123         BUILD_BUG_ON(FORCEWAKE_MEDIA != (1 << FW_DOMAIN_ID_MEDIA));
1124
1125         d->mask = 1 << domain_id;
1126
1127         hrtimer_init(&d->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1128         d->timer.function = intel_uncore_fw_release_timer;
1129
1130         dev_priv->uncore.fw_domains |= (1 << domain_id);
1131
1132         fw_domain_reset(d);
1133 }
1134
1135 static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
1136 {
1137         if (INTEL_INFO(dev_priv)->gen <= 5)
1138                 return;
1139
1140         if (IS_GEN9(dev_priv)) {
1141                 dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
1142                 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1143                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1144                                FORCEWAKE_RENDER_GEN9,
1145                                FORCEWAKE_ACK_RENDER_GEN9);
1146                 fw_domain_init(dev_priv, FW_DOMAIN_ID_BLITTER,
1147                                FORCEWAKE_BLITTER_GEN9,
1148                                FORCEWAKE_ACK_BLITTER_GEN9);
1149                 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
1150                                FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
1151         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1152                 dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
1153                 if (!IS_CHERRYVIEW(dev_priv))
1154                         dev_priv->uncore.funcs.force_wake_put =
1155                                 fw_domains_put_with_fifo;
1156                 else
1157                         dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1158                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1159                                FORCEWAKE_VLV, FORCEWAKE_ACK_VLV);
1160                 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
1161                                FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV);
1162         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1163                 dev_priv->uncore.funcs.force_wake_get =
1164                         fw_domains_get_with_thread_status;
1165                 if (IS_HASWELL(dev_priv))
1166                         dev_priv->uncore.funcs.force_wake_put =
1167                                 fw_domains_put_with_fifo;
1168                 else
1169                         dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1170                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1171                                FORCEWAKE_MT, FORCEWAKE_ACK_HSW);
1172         } else if (IS_IVYBRIDGE(dev_priv)) {
1173                 u32 ecobus;
1174
1175                 /* IVB configs may use multi-threaded forcewake */
1176
1177                 /* A small trick here - if the bios hasn't configured
1178                  * MT forcewake, and if the device is in RC6, then
1179                  * force_wake_mt_get will not wake the device and the
1180                  * ECOBUS read will return zero. Which will be
1181                  * (correctly) interpreted by the test below as MT
1182                  * forcewake being disabled.
1183                  */
1184                 dev_priv->uncore.funcs.force_wake_get =
1185                         fw_domains_get_with_thread_status;
1186                 dev_priv->uncore.funcs.force_wake_put =
1187                         fw_domains_put_with_fifo;
1188
1189                 /* We need to init first for ECOBUS access and then
1190                  * determine later if we want to reinit, in case of MT access is
1191                  * not working. In this stage we don't know which flavour this
1192                  * ivb is, so it is better to reset also the gen6 fw registers
1193                  * before the ecobus check.
1194                  */
1195
1196                 __raw_i915_write32(dev_priv, FORCEWAKE, 0);
1197                 __raw_posting_read(dev_priv, ECOBUS);
1198
1199                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1200                                FORCEWAKE_MT, FORCEWAKE_MT_ACK);
1201
1202                 spin_lock_irq(&dev_priv->uncore.lock);
1203                 fw_domains_get_with_thread_status(dev_priv, FORCEWAKE_ALL);
1204                 ecobus = __raw_i915_read32(dev_priv, ECOBUS);
1205                 fw_domains_put_with_fifo(dev_priv, FORCEWAKE_ALL);
1206                 spin_unlock_irq(&dev_priv->uncore.lock);
1207
1208                 if (!(ecobus & FORCEWAKE_MT_ENABLE)) {
1209                         DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
1210                         DRM_INFO("when using vblank-synced partial screen updates.\n");
1211                         fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1212                                        FORCEWAKE, FORCEWAKE_ACK);
1213                 }
1214         } else if (IS_GEN6(dev_priv)) {
1215                 dev_priv->uncore.funcs.force_wake_get =
1216                         fw_domains_get_with_thread_status;
1217                 dev_priv->uncore.funcs.force_wake_put =
1218                         fw_domains_put_with_fifo;
1219                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1220                                FORCEWAKE, FORCEWAKE_ACK);
1221         }
1222
1223         /* All future platforms are expected to require complex power gating */
1224         WARN_ON(dev_priv->uncore.fw_domains == 0);
1225 }
1226
1227 #define ASSIGN_FW_DOMAINS_TABLE(d) \
1228 { \
1229         dev_priv->uncore.fw_domains_table = \
1230                         (struct intel_forcewake_range *)(d); \
1231         dev_priv->uncore.fw_domains_table_entries = ARRAY_SIZE((d)); \
1232 }
1233
1234 void intel_uncore_init(struct drm_i915_private *dev_priv)
1235 {
1236         i915_check_vgpu(dev_priv);
1237
1238         intel_uncore_edram_detect(dev_priv);
1239         intel_uncore_fw_domains_init(dev_priv);
1240         __intel_uncore_early_sanitize(dev_priv, false);
1241
1242         dev_priv->uncore.unclaimed_mmio_check = 1;
1243
1244         switch (INTEL_INFO(dev_priv)->gen) {
1245         default:
1246         case 9:
1247                 ASSIGN_FW_DOMAINS_TABLE(__gen9_fw_ranges);
1248                 ASSIGN_WRITE_MMIO_VFUNCS(fwtable);
1249                 ASSIGN_READ_MMIO_VFUNCS(fwtable);
1250                 break;
1251         case 8:
1252                 if (IS_CHERRYVIEW(dev_priv)) {
1253                         ASSIGN_FW_DOMAINS_TABLE(__chv_fw_ranges);
1254                         ASSIGN_WRITE_MMIO_VFUNCS(fwtable);
1255                         ASSIGN_READ_MMIO_VFUNCS(fwtable);
1256
1257                 } else {
1258                         ASSIGN_WRITE_MMIO_VFUNCS(gen8);
1259                         ASSIGN_READ_MMIO_VFUNCS(gen6);
1260                 }
1261                 break;
1262         case 7:
1263         case 6:
1264                 ASSIGN_WRITE_MMIO_VFUNCS(gen6);
1265
1266                 if (IS_VALLEYVIEW(dev_priv)) {
1267                         ASSIGN_FW_DOMAINS_TABLE(__vlv_fw_ranges);
1268                         ASSIGN_READ_MMIO_VFUNCS(fwtable);
1269                 } else {
1270                         ASSIGN_READ_MMIO_VFUNCS(gen6);
1271                 }
1272                 break;
1273         case 5:
1274                 ASSIGN_WRITE_MMIO_VFUNCS(gen5);
1275                 ASSIGN_READ_MMIO_VFUNCS(gen5);
1276                 break;
1277         case 4:
1278         case 3:
1279         case 2:
1280                 ASSIGN_WRITE_MMIO_VFUNCS(gen2);
1281                 ASSIGN_READ_MMIO_VFUNCS(gen2);
1282                 break;
1283         }
1284
1285         intel_fw_table_check(dev_priv);
1286
1287         if (intel_vgpu_active(dev_priv)) {
1288                 ASSIGN_WRITE_MMIO_VFUNCS(vgpu);
1289                 ASSIGN_READ_MMIO_VFUNCS(vgpu);
1290         }
1291
1292         i915_check_and_clear_faults(dev_priv);
1293 }
1294 #undef ASSIGN_WRITE_MMIO_VFUNCS
1295 #undef ASSIGN_READ_MMIO_VFUNCS
1296
1297 void intel_uncore_fini(struct drm_i915_private *dev_priv)
1298 {
1299         /* Paranoia: make sure we have disabled everything before we exit. */
1300         intel_uncore_sanitize(dev_priv);
1301         intel_uncore_forcewake_reset(dev_priv, false);
1302 }
1303
1304 #define GEN_RANGE(l, h) GENMASK((h) - 1, (l) - 1)
1305
1306 static const struct register_whitelist {
1307         i915_reg_t offset_ldw, offset_udw;
1308         uint32_t size;
1309         /* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
1310         uint32_t gen_bitmask;
1311 } whitelist[] = {
1312         { .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
1313           .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
1314           .size = 8, .gen_bitmask = GEN_RANGE(4, 9) },
1315 };
1316
1317 int i915_reg_read_ioctl(struct drm_device *dev,
1318                         void *data, struct drm_file *file)
1319 {
1320         struct drm_i915_private *dev_priv = to_i915(dev);
1321         struct drm_i915_reg_read *reg = data;
1322         struct register_whitelist const *entry = whitelist;
1323         unsigned size;
1324         i915_reg_t offset_ldw, offset_udw;
1325         int i, ret = 0;
1326
1327         for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
1328                 if (i915_mmio_reg_offset(entry->offset_ldw) == (reg->offset & -entry->size) &&
1329                     (INTEL_INFO(dev)->gen_mask & entry->gen_bitmask))
1330                         break;
1331         }
1332
1333         if (i == ARRAY_SIZE(whitelist))
1334                 return -EINVAL;
1335
1336         /* We use the low bits to encode extra flags as the register should
1337          * be naturally aligned (and those that are not so aligned merely
1338          * limit the available flags for that register).
1339          */
1340         offset_ldw = entry->offset_ldw;
1341         offset_udw = entry->offset_udw;
1342         size = entry->size;
1343         size |= reg->offset ^ i915_mmio_reg_offset(offset_ldw);
1344
1345         intel_runtime_pm_get(dev_priv);
1346
1347         switch (size) {
1348         case 8 | 1:
1349                 reg->val = I915_READ64_2x32(offset_ldw, offset_udw);
1350                 break;
1351         case 8:
1352                 reg->val = I915_READ64(offset_ldw);
1353                 break;
1354         case 4:
1355                 reg->val = I915_READ(offset_ldw);
1356                 break;
1357         case 2:
1358                 reg->val = I915_READ16(offset_ldw);
1359                 break;
1360         case 1:
1361                 reg->val = I915_READ8(offset_ldw);
1362                 break;
1363         default:
1364                 ret = -EINVAL;
1365                 goto out;
1366         }
1367
1368 out:
1369         intel_runtime_pm_put(dev_priv);
1370         return ret;
1371 }
1372
1373 static int i915_reset_complete(struct pci_dev *pdev)
1374 {
1375         u8 gdrst;
1376         pci_read_config_byte(pdev, I915_GDRST, &gdrst);
1377         return (gdrst & GRDOM_RESET_STATUS) == 0;
1378 }
1379
1380 static int i915_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask)
1381 {
1382         struct pci_dev *pdev = dev_priv->drm.pdev;
1383
1384         /* assert reset for at least 20 usec */
1385         pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1386         udelay(20);
1387         pci_write_config_byte(pdev, I915_GDRST, 0);
1388
1389         return wait_for(i915_reset_complete(pdev), 500);
1390 }
1391
1392 static int g4x_reset_complete(struct pci_dev *pdev)
1393 {
1394         u8 gdrst;
1395         pci_read_config_byte(pdev, I915_GDRST, &gdrst);
1396         return (gdrst & GRDOM_RESET_ENABLE) == 0;
1397 }
1398
1399 static int g33_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask)
1400 {
1401         struct pci_dev *pdev = dev_priv->drm.pdev;
1402         pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1403         return wait_for(g4x_reset_complete(pdev), 500);
1404 }
1405
1406 static int g4x_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask)
1407 {
1408         struct pci_dev *pdev = dev_priv->drm.pdev;
1409         int ret;
1410
1411         pci_write_config_byte(pdev, I915_GDRST,
1412                               GRDOM_RENDER | GRDOM_RESET_ENABLE);
1413         ret =  wait_for(g4x_reset_complete(pdev), 500);
1414         if (ret)
1415                 return ret;
1416
1417         /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1418         I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE);
1419         POSTING_READ(VDECCLK_GATE_D);
1420
1421         pci_write_config_byte(pdev, I915_GDRST,
1422                               GRDOM_MEDIA | GRDOM_RESET_ENABLE);
1423         ret =  wait_for(g4x_reset_complete(pdev), 500);
1424         if (ret)
1425                 return ret;
1426
1427         /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1428         I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE);
1429         POSTING_READ(VDECCLK_GATE_D);
1430
1431         pci_write_config_byte(pdev, I915_GDRST, 0);
1432
1433         return 0;
1434 }
1435
1436 static int ironlake_do_reset(struct drm_i915_private *dev_priv,
1437                              unsigned engine_mask)
1438 {
1439         int ret;
1440
1441         I915_WRITE(ILK_GDSR,
1442                    ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
1443         ret = intel_wait_for_register(dev_priv,
1444                                       ILK_GDSR, ILK_GRDOM_RESET_ENABLE, 0,
1445                                       500);
1446         if (ret)
1447                 return ret;
1448
1449         I915_WRITE(ILK_GDSR,
1450                    ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
1451         ret = intel_wait_for_register(dev_priv,
1452                                       ILK_GDSR, ILK_GRDOM_RESET_ENABLE, 0,
1453                                       500);
1454         if (ret)
1455                 return ret;
1456
1457         I915_WRITE(ILK_GDSR, 0);
1458
1459         return 0;
1460 }
1461
1462 /* Reset the hardware domains (GENX_GRDOM_*) specified by mask */
1463 static int gen6_hw_domain_reset(struct drm_i915_private *dev_priv,
1464                                 u32 hw_domain_mask)
1465 {
1466         /* GEN6_GDRST is not in the gt power well, no need to check
1467          * for fifo space for the write or forcewake the chip for
1468          * the read
1469          */
1470         __raw_i915_write32(dev_priv, GEN6_GDRST, hw_domain_mask);
1471
1472         /* Spin waiting for the device to ack the reset requests */
1473         return intel_wait_for_register_fw(dev_priv,
1474                                           GEN6_GDRST, hw_domain_mask, 0,
1475                                           500);
1476 }
1477
1478 /**
1479  * gen6_reset_engines - reset individual engines
1480  * @dev_priv: i915 device
1481  * @engine_mask: mask of intel_ring_flag() engines or ALL_ENGINES for full reset
1482  *
1483  * This function will reset the individual engines that are set in engine_mask.
1484  * If you provide ALL_ENGINES as mask, full global domain reset will be issued.
1485  *
1486  * Note: It is responsibility of the caller to handle the difference between
1487  * asking full domain reset versus reset for all available individual engines.
1488  *
1489  * Returns 0 on success, nonzero on error.
1490  */
1491 static int gen6_reset_engines(struct drm_i915_private *dev_priv,
1492                               unsigned engine_mask)
1493 {
1494         struct intel_engine_cs *engine;
1495         const u32 hw_engine_mask[I915_NUM_ENGINES] = {
1496                 [RCS] = GEN6_GRDOM_RENDER,
1497                 [BCS] = GEN6_GRDOM_BLT,
1498                 [VCS] = GEN6_GRDOM_MEDIA,
1499                 [VCS2] = GEN8_GRDOM_MEDIA2,
1500                 [VECS] = GEN6_GRDOM_VECS,
1501         };
1502         u32 hw_mask;
1503         int ret;
1504
1505         if (engine_mask == ALL_ENGINES) {
1506                 hw_mask = GEN6_GRDOM_FULL;
1507         } else {
1508                 unsigned int tmp;
1509
1510                 hw_mask = 0;
1511                 for_each_engine_masked(engine, dev_priv, engine_mask, tmp)
1512                         hw_mask |= hw_engine_mask[engine->id];
1513         }
1514
1515         ret = gen6_hw_domain_reset(dev_priv, hw_mask);
1516
1517         intel_uncore_forcewake_reset(dev_priv, true);
1518
1519         return ret;
1520 }
1521
1522 /**
1523  * intel_wait_for_register_fw - wait until register matches expected state
1524  * @dev_priv: the i915 device
1525  * @reg: the register to read
1526  * @mask: mask to apply to register value
1527  * @value: expected value
1528  * @timeout_ms: timeout in millisecond
1529  *
1530  * This routine waits until the target register @reg contains the expected
1531  * @value after applying the @mask, i.e. it waits until ::
1532  *
1533  *     (I915_READ_FW(reg) & mask) == value
1534  *
1535  * Otherwise, the wait will timeout after @timeout_ms milliseconds.
1536  *
1537  * Note that this routine assumes the caller holds forcewake asserted, it is
1538  * not suitable for very long waits. See intel_wait_for_register() if you
1539  * wish to wait without holding forcewake for the duration (i.e. you expect
1540  * the wait to be slow).
1541  *
1542  * Returns 0 if the register matches the desired condition, or -ETIMEOUT.
1543  */
1544 int intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
1545                                i915_reg_t reg,
1546                                const u32 mask,
1547                                const u32 value,
1548                                const unsigned long timeout_ms)
1549 {
1550 #define done ((I915_READ_FW(reg) & mask) == value)
1551         int ret = wait_for_us(done, 2);
1552         if (ret)
1553                 ret = wait_for(done, timeout_ms);
1554         return ret;
1555 #undef done
1556 }
1557
1558 /**
1559  * intel_wait_for_register - wait until register matches expected state
1560  * @dev_priv: the i915 device
1561  * @reg: the register to read
1562  * @mask: mask to apply to register value
1563  * @value: expected value
1564  * @timeout_ms: timeout in millisecond
1565  *
1566  * This routine waits until the target register @reg contains the expected
1567  * @value after applying the @mask, i.e. it waits until ::
1568  *
1569  *     (I915_READ(reg) & mask) == value
1570  *
1571  * Otherwise, the wait will timeout after @timeout_ms milliseconds.
1572  *
1573  * Returns 0 if the register matches the desired condition, or -ETIMEOUT.
1574  */
1575 int intel_wait_for_register(struct drm_i915_private *dev_priv,
1576                             i915_reg_t reg,
1577                             const u32 mask,
1578                             const u32 value,
1579                             const unsigned long timeout_ms)
1580 {
1581
1582         unsigned fw =
1583                 intel_uncore_forcewake_for_reg(dev_priv, reg, FW_REG_READ);
1584         int ret;
1585
1586         intel_uncore_forcewake_get(dev_priv, fw);
1587         ret = wait_for_us((I915_READ_FW(reg) & mask) == value, 2);
1588         intel_uncore_forcewake_put(dev_priv, fw);
1589         if (ret)
1590                 ret = wait_for((I915_READ_NOTRACE(reg) & mask) == value,
1591                                timeout_ms);
1592
1593         return ret;
1594 }
1595
1596 static int gen8_request_engine_reset(struct intel_engine_cs *engine)
1597 {
1598         struct drm_i915_private *dev_priv = engine->i915;
1599         int ret;
1600
1601         I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base),
1602                       _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET));
1603
1604         ret = intel_wait_for_register_fw(dev_priv,
1605                                          RING_RESET_CTL(engine->mmio_base),
1606                                          RESET_CTL_READY_TO_RESET,
1607                                          RESET_CTL_READY_TO_RESET,
1608                                          700);
1609         if (ret)
1610                 DRM_ERROR("%s: reset request timeout\n", engine->name);
1611
1612         return ret;
1613 }
1614
1615 static void gen8_unrequest_engine_reset(struct intel_engine_cs *engine)
1616 {
1617         struct drm_i915_private *dev_priv = engine->i915;
1618
1619         I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base),
1620                       _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET));
1621 }
1622
1623 static int gen8_reset_engines(struct drm_i915_private *dev_priv,
1624                               unsigned engine_mask)
1625 {
1626         struct intel_engine_cs *engine;
1627         unsigned int tmp;
1628
1629         for_each_engine_masked(engine, dev_priv, engine_mask, tmp)
1630                 if (gen8_request_engine_reset(engine))
1631                         goto not_ready;
1632
1633         return gen6_reset_engines(dev_priv, engine_mask);
1634
1635 not_ready:
1636         for_each_engine_masked(engine, dev_priv, engine_mask, tmp)
1637                 gen8_unrequest_engine_reset(engine);
1638
1639         return -EIO;
1640 }
1641
1642 typedef int (*reset_func)(struct drm_i915_private *, unsigned engine_mask);
1643
1644 static reset_func intel_get_gpu_reset(struct drm_i915_private *dev_priv)
1645 {
1646         if (!i915.reset)
1647                 return NULL;
1648
1649         if (INTEL_INFO(dev_priv)->gen >= 8)
1650                 return gen8_reset_engines;
1651         else if (INTEL_INFO(dev_priv)->gen >= 6)
1652                 return gen6_reset_engines;
1653         else if (IS_GEN5(dev_priv))
1654                 return ironlake_do_reset;
1655         else if (IS_G4X(dev_priv))
1656                 return g4x_do_reset;
1657         else if (IS_G33(dev_priv))
1658                 return g33_do_reset;
1659         else if (INTEL_INFO(dev_priv)->gen >= 3)
1660                 return i915_do_reset;
1661         else
1662                 return NULL;
1663 }
1664
1665 int intel_gpu_reset(struct drm_i915_private *dev_priv, unsigned engine_mask)
1666 {
1667         reset_func reset;
1668         int ret;
1669
1670         reset = intel_get_gpu_reset(dev_priv);
1671         if (reset == NULL)
1672                 return -ENODEV;
1673
1674         /* If the power well sleeps during the reset, the reset
1675          * request may be dropped and never completes (causing -EIO).
1676          */
1677         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1678         ret = reset(dev_priv, engine_mask);
1679         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1680
1681         return ret;
1682 }
1683
1684 bool intel_has_gpu_reset(struct drm_i915_private *dev_priv)
1685 {
1686         return intel_get_gpu_reset(dev_priv) != NULL;
1687 }
1688
1689 int intel_guc_reset(struct drm_i915_private *dev_priv)
1690 {
1691         int ret;
1692         unsigned long irqflags;
1693
1694         if (!HAS_GUC(dev_priv))
1695                 return -EINVAL;
1696
1697         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1698         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1699
1700         ret = gen6_hw_domain_reset(dev_priv, GEN9_GRDOM_GUC);
1701
1702         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1703         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1704
1705         return ret;
1706 }
1707
1708 bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv)
1709 {
1710         return check_for_unclaimed_mmio(dev_priv);
1711 }
1712
1713 bool
1714 intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv)
1715 {
1716         if (unlikely(i915.mmio_debug ||
1717                      dev_priv->uncore.unclaimed_mmio_check <= 0))
1718                 return false;
1719
1720         if (unlikely(intel_uncore_unclaimed_mmio(dev_priv))) {
1721                 DRM_DEBUG("Unclaimed register detected, "
1722                           "enabling oneshot unclaimed register reporting. "
1723                           "Please use i915.mmio_debug=N for more information.\n");
1724                 i915.mmio_debug++;
1725                 dev_priv->uncore.unclaimed_mmio_check--;
1726                 return true;
1727         }
1728
1729         return false;
1730 }
1731
1732 static enum forcewake_domains
1733 intel_uncore_forcewake_for_read(struct drm_i915_private *dev_priv,
1734                                 i915_reg_t reg)
1735 {
1736         u32 offset = i915_mmio_reg_offset(reg);
1737         enum forcewake_domains fw_domains;
1738
1739         if (HAS_FWTABLE(dev_priv)) {
1740                 fw_domains = __fwtable_reg_read_fw_domains(offset);
1741         } else if (INTEL_GEN(dev_priv) >= 6) {
1742                 fw_domains = __gen6_reg_read_fw_domains(offset);
1743         } else {
1744                 WARN_ON(!IS_GEN(dev_priv, 2, 5));
1745                 fw_domains = 0;
1746         }
1747
1748         WARN_ON(fw_domains & ~dev_priv->uncore.fw_domains);
1749
1750         return fw_domains;
1751 }
1752
1753 static enum forcewake_domains
1754 intel_uncore_forcewake_for_write(struct drm_i915_private *dev_priv,
1755                                  i915_reg_t reg)
1756 {
1757         u32 offset = i915_mmio_reg_offset(reg);
1758         enum forcewake_domains fw_domains;
1759
1760         if (HAS_FWTABLE(dev_priv) && !IS_VALLEYVIEW(dev_priv)) {
1761                 fw_domains = __fwtable_reg_write_fw_domains(offset);
1762         } else if (IS_GEN8(dev_priv)) {
1763                 fw_domains = __gen8_reg_write_fw_domains(offset);
1764         } else if (IS_GEN(dev_priv, 6, 7)) {
1765                 fw_domains = FORCEWAKE_RENDER;
1766         } else {
1767                 WARN_ON(!IS_GEN(dev_priv, 2, 5));
1768                 fw_domains = 0;
1769         }
1770
1771         WARN_ON(fw_domains & ~dev_priv->uncore.fw_domains);
1772
1773         return fw_domains;
1774 }
1775
1776 /**
1777  * intel_uncore_forcewake_for_reg - which forcewake domains are needed to access
1778  *                                  a register
1779  * @dev_priv: pointer to struct drm_i915_private
1780  * @reg: register in question
1781  * @op: operation bitmask of FW_REG_READ and/or FW_REG_WRITE
1782  *
1783  * Returns a set of forcewake domains required to be taken with for example
1784  * intel_uncore_forcewake_get for the specified register to be accessible in the
1785  * specified mode (read, write or read/write) with raw mmio accessors.
1786  *
1787  * NOTE: On Gen6 and Gen7 write forcewake domain (FORCEWAKE_RENDER) requires the
1788  * callers to do FIFO management on their own or risk losing writes.
1789  */
1790 enum forcewake_domains
1791 intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
1792                                i915_reg_t reg, unsigned int op)
1793 {
1794         enum forcewake_domains fw_domains = 0;
1795
1796         WARN_ON(!op);
1797
1798         if (intel_vgpu_active(dev_priv))
1799                 return 0;
1800
1801         if (op & FW_REG_READ)
1802                 fw_domains = intel_uncore_forcewake_for_read(dev_priv, reg);
1803
1804         if (op & FW_REG_WRITE)
1805                 fw_domains |= intel_uncore_forcewake_for_write(dev_priv, reg);
1806
1807         return fw_domains;
1808 }