2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "intel_drv.h"
26 #include "i915_vgpu.h"
28 #include <linux/pm_runtime.h>
30 #define FORCEWAKE_ACK_TIMEOUT_MS 50
32 #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32((dev_priv__), (reg__))
34 static const char * const forcewake_domain_names[] = {
41 intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id)
43 BUILD_BUG_ON(ARRAY_SIZE(forcewake_domain_names) != FW_DOMAIN_ID_COUNT);
45 if (id >= 0 && id < FW_DOMAIN_ID_COUNT)
46 return forcewake_domain_names[id];
54 fw_domain_reset(const struct intel_uncore_forcewake_domain *d)
56 WARN_ON(!i915_mmio_reg_valid(d->reg_set));
57 __raw_i915_write32(d->i915, d->reg_set, d->val_reset);
61 fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d)
64 hrtimer_start_range_ns(&d->timer,
65 ktime_set(0, NSEC_PER_MSEC),
71 fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d)
73 if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) &
74 FORCEWAKE_KERNEL) == 0,
75 FORCEWAKE_ACK_TIMEOUT_MS))
76 DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n",
77 intel_uncore_forcewake_domain_to_str(d->id));
81 fw_domain_get(const struct intel_uncore_forcewake_domain *d)
83 __raw_i915_write32(d->i915, d->reg_set, d->val_set);
87 fw_domain_wait_ack(const struct intel_uncore_forcewake_domain *d)
89 if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) &
91 FORCEWAKE_ACK_TIMEOUT_MS))
92 DRM_ERROR("%s: timed out waiting for forcewake ack request.\n",
93 intel_uncore_forcewake_domain_to_str(d->id));
97 fw_domain_put(const struct intel_uncore_forcewake_domain *d)
99 __raw_i915_write32(d->i915, d->reg_set, d->val_clear);
103 fw_domain_posting_read(const struct intel_uncore_forcewake_domain *d)
105 /* something from same cacheline, but not from the set register */
106 if (i915_mmio_reg_valid(d->reg_post))
107 __raw_posting_read(d->i915, d->reg_post);
111 fw_domains_get(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
113 struct intel_uncore_forcewake_domain *d;
115 for_each_fw_domain_masked(d, fw_domains, dev_priv) {
116 fw_domain_wait_ack_clear(d);
120 for_each_fw_domain_masked(d, fw_domains, dev_priv)
121 fw_domain_wait_ack(d);
125 fw_domains_put(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
127 struct intel_uncore_forcewake_domain *d;
129 for_each_fw_domain_masked(d, fw_domains, dev_priv) {
131 fw_domain_posting_read(d);
136 fw_domains_posting_read(struct drm_i915_private *dev_priv)
138 struct intel_uncore_forcewake_domain *d;
140 /* No need to do for all, just do for first found */
141 for_each_fw_domain(d, dev_priv) {
142 fw_domain_posting_read(d);
148 fw_domains_reset(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
150 struct intel_uncore_forcewake_domain *d;
152 if (dev_priv->uncore.fw_domains == 0)
155 for_each_fw_domain_masked(d, fw_domains, dev_priv)
158 fw_domains_posting_read(dev_priv);
161 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
163 /* w/a for a sporadic read returning 0 by waiting for the GT
166 if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) &
167 GEN6_GT_THREAD_STATUS_CORE_MASK) == 0, 500))
168 DRM_ERROR("GT thread status wait timed out\n");
171 static void fw_domains_get_with_thread_status(struct drm_i915_private *dev_priv,
172 enum forcewake_domains fw_domains)
174 fw_domains_get(dev_priv, fw_domains);
176 /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */
177 __gen6_gt_wait_for_thread_c0(dev_priv);
180 static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
184 gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG);
185 if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg))
186 __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg);
189 static void fw_domains_put_with_fifo(struct drm_i915_private *dev_priv,
190 enum forcewake_domains fw_domains)
192 fw_domains_put(dev_priv, fw_domains);
193 gen6_gt_check_fifodbg(dev_priv);
196 static inline u32 fifo_free_entries(struct drm_i915_private *dev_priv)
198 u32 count = __raw_i915_read32(dev_priv, GTFIFOCTL);
200 return count & GT_FIFO_FREE_ENTRIES_MASK;
203 static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
207 /* On VLV, FIFO will be shared by both SW and HW.
208 * So, we need to read the FREE_ENTRIES everytime */
209 if (IS_VALLEYVIEW(dev_priv))
210 dev_priv->uncore.fifo_count = fifo_free_entries(dev_priv);
212 if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
214 u32 fifo = fifo_free_entries(dev_priv);
216 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
218 fifo = fifo_free_entries(dev_priv);
220 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
222 dev_priv->uncore.fifo_count = fifo;
224 dev_priv->uncore.fifo_count--;
229 static enum hrtimer_restart
230 intel_uncore_fw_release_timer(struct hrtimer *timer)
232 struct intel_uncore_forcewake_domain *domain =
233 container_of(timer, struct intel_uncore_forcewake_domain, timer);
234 struct drm_i915_private *dev_priv = domain->i915;
235 unsigned long irqflags;
237 assert_rpm_device_not_suspended(dev_priv);
239 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
240 if (WARN_ON(domain->wake_count == 0))
241 domain->wake_count++;
243 if (--domain->wake_count == 0) {
244 dev_priv->uncore.funcs.force_wake_put(dev_priv, domain->mask);
245 dev_priv->uncore.fw_domains_active &= ~domain->mask;
248 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
250 return HRTIMER_NORESTART;
253 void intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv,
256 unsigned long irqflags;
257 struct intel_uncore_forcewake_domain *domain;
258 int retry_count = 100;
259 enum forcewake_domains fw, active_domains;
261 /* Hold uncore.lock across reset to prevent any register access
262 * with forcewake not set correctly. Wait until all pending
263 * timers are run before holding.
268 for_each_fw_domain(domain, dev_priv) {
269 if (hrtimer_cancel(&domain->timer) == 0)
272 intel_uncore_fw_release_timer(&domain->timer);
275 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
277 for_each_fw_domain(domain, dev_priv) {
278 if (hrtimer_active(&domain->timer))
279 active_domains |= domain->mask;
282 if (active_domains == 0)
285 if (--retry_count == 0) {
286 DRM_ERROR("Timed out waiting for forcewake timers to finish\n");
290 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
294 WARN_ON(active_domains);
296 fw = dev_priv->uncore.fw_domains_active;
298 dev_priv->uncore.funcs.force_wake_put(dev_priv, fw);
300 fw_domains_reset(dev_priv, FORCEWAKE_ALL);
302 if (restore) { /* If reset with a user forcewake, try to restore */
304 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw);
306 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv))
307 dev_priv->uncore.fifo_count =
308 fifo_free_entries(dev_priv);
312 assert_forcewakes_inactive(dev_priv);
314 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
317 static u64 gen9_edram_size(struct drm_i915_private *dev_priv)
319 const unsigned int ways[8] = { 4, 8, 12, 16, 16, 16, 16, 16 };
320 const unsigned int sets[4] = { 1, 1, 2, 2 };
321 const u32 cap = dev_priv->edram_cap;
323 return EDRAM_NUM_BANKS(cap) *
324 ways[EDRAM_WAYS_IDX(cap)] *
325 sets[EDRAM_SETS_IDX(cap)] *
329 u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv)
331 if (!HAS_EDRAM(dev_priv))
334 /* The needed capability bits for size calculation
335 * are not there with pre gen9 so return 128MB always.
337 if (INTEL_GEN(dev_priv) < 9)
338 return 128 * 1024 * 1024;
340 return gen9_edram_size(dev_priv);
343 static void intel_uncore_edram_detect(struct drm_i915_private *dev_priv)
345 if (IS_HASWELL(dev_priv) ||
346 IS_BROADWELL(dev_priv) ||
347 INTEL_GEN(dev_priv) >= 9) {
348 dev_priv->edram_cap = __raw_i915_read32(dev_priv,
351 /* NB: We can't write IDICR yet because we do not have gt funcs
354 dev_priv->edram_cap = 0;
357 if (HAS_EDRAM(dev_priv))
358 DRM_INFO("Found %lluMB of eDRAM\n",
359 intel_uncore_edram_size(dev_priv) / (1024 * 1024));
363 fpga_check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
367 dbg = __raw_i915_read32(dev_priv, FPGA_DBG);
368 if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM)))
371 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
377 vlv_check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
381 cer = __raw_i915_read32(dev_priv, CLAIM_ER);
382 if (likely(!(cer & (CLAIM_ER_OVERFLOW | CLAIM_ER_CTR_MASK))))
385 __raw_i915_write32(dev_priv, CLAIM_ER, CLAIM_ER_CLR);
391 check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
393 if (HAS_FPGA_DBG_UNCLAIMED(dev_priv))
394 return fpga_check_for_unclaimed_mmio(dev_priv);
396 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
397 return vlv_check_for_unclaimed_mmio(dev_priv);
402 static void __intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
403 bool restore_forcewake)
405 /* clear out unclaimed reg detection bit */
406 if (check_for_unclaimed_mmio(dev_priv))
407 DRM_DEBUG("unclaimed mmio detected on uncore init, clearing\n");
409 /* clear out old GT FIFO errors */
410 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv))
411 __raw_i915_write32(dev_priv, GTFIFODBG,
412 __raw_i915_read32(dev_priv, GTFIFODBG));
414 /* WaDisableShadowRegForCpd:chv */
415 if (IS_CHERRYVIEW(dev_priv)) {
416 __raw_i915_write32(dev_priv, GTFIFOCTL,
417 __raw_i915_read32(dev_priv, GTFIFOCTL) |
418 GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
419 GT_FIFO_CTL_RC6_POLICY_STALL);
422 intel_uncore_forcewake_reset(dev_priv, restore_forcewake);
425 void intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
426 bool restore_forcewake)
428 __intel_uncore_early_sanitize(dev_priv, restore_forcewake);
429 i915_check_and_clear_faults(dev_priv);
432 void intel_uncore_sanitize(struct drm_i915_private *dev_priv)
434 i915.enable_rc6 = sanitize_rc6_option(dev_priv, i915.enable_rc6);
436 /* BIOS often leaves RC6 enabled, but disable it for hw init */
437 intel_sanitize_gt_powersave(dev_priv);
440 static void __intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
441 enum forcewake_domains fw_domains)
443 struct intel_uncore_forcewake_domain *domain;
445 fw_domains &= dev_priv->uncore.fw_domains;
447 for_each_fw_domain_masked(domain, fw_domains, dev_priv) {
448 if (domain->wake_count++)
449 fw_domains &= ~domain->mask;
453 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
454 dev_priv->uncore.fw_domains_active |= fw_domains;
459 * intel_uncore_forcewake_get - grab forcewake domain references
460 * @dev_priv: i915 device instance
461 * @fw_domains: forcewake domains to get reference on
463 * This function can be used get GT's forcewake domain references.
464 * Normal register access will handle the forcewake domains automatically.
465 * However if some sequence requires the GT to not power down a particular
466 * forcewake domains this function should be called at the beginning of the
467 * sequence. And subsequently the reference should be dropped by symmetric
468 * call to intel_unforce_forcewake_put(). Usually caller wants all the domains
469 * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL.
471 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
472 enum forcewake_domains fw_domains)
474 unsigned long irqflags;
476 if (!dev_priv->uncore.funcs.force_wake_get)
479 assert_rpm_wakelock_held(dev_priv);
481 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
482 __intel_uncore_forcewake_get(dev_priv, fw_domains);
483 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
487 * intel_uncore_forcewake_get__locked - grab forcewake domain references
488 * @dev_priv: i915 device instance
489 * @fw_domains: forcewake domains to get reference on
491 * See intel_uncore_forcewake_get(). This variant places the onus
492 * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
494 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
495 enum forcewake_domains fw_domains)
497 assert_spin_locked(&dev_priv->uncore.lock);
499 if (!dev_priv->uncore.funcs.force_wake_get)
502 __intel_uncore_forcewake_get(dev_priv, fw_domains);
505 static void __intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
506 enum forcewake_domains fw_domains)
508 struct intel_uncore_forcewake_domain *domain;
510 fw_domains &= dev_priv->uncore.fw_domains;
512 for_each_fw_domain_masked(domain, fw_domains, dev_priv) {
513 if (WARN_ON(domain->wake_count == 0))
516 if (--domain->wake_count)
519 fw_domain_arm_timer(domain);
524 * intel_uncore_forcewake_put - release a forcewake domain reference
525 * @dev_priv: i915 device instance
526 * @fw_domains: forcewake domains to put references
528 * This function drops the device-level forcewakes for specified
529 * domains obtained by intel_uncore_forcewake_get().
531 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
532 enum forcewake_domains fw_domains)
534 unsigned long irqflags;
536 if (!dev_priv->uncore.funcs.force_wake_put)
539 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
540 __intel_uncore_forcewake_put(dev_priv, fw_domains);
541 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
545 * intel_uncore_forcewake_put__locked - grab forcewake domain references
546 * @dev_priv: i915 device instance
547 * @fw_domains: forcewake domains to get reference on
549 * See intel_uncore_forcewake_put(). This variant places the onus
550 * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
552 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
553 enum forcewake_domains fw_domains)
555 assert_spin_locked(&dev_priv->uncore.lock);
557 if (!dev_priv->uncore.funcs.force_wake_put)
560 __intel_uncore_forcewake_put(dev_priv, fw_domains);
563 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv)
565 if (!dev_priv->uncore.funcs.force_wake_get)
568 WARN_ON(dev_priv->uncore.fw_domains_active);
571 /* We give fast paths for the really cool registers */
572 #define NEEDS_FORCE_WAKE(reg) ((reg) < 0x40000)
574 #define __gen6_reg_read_fw_domains(offset) \
576 enum forcewake_domains __fwd; \
577 if (NEEDS_FORCE_WAKE(offset)) \
578 __fwd = FORCEWAKE_RENDER; \
584 static int fw_range_cmp(u32 offset, const struct intel_forcewake_range *entry)
586 if (offset < entry->start)
588 else if (offset > entry->end)
594 /* Copied and "macroized" from lib/bsearch.c */
595 #define BSEARCH(key, base, num, cmp) ({ \
596 unsigned int start__ = 0, end__ = (num); \
597 typeof(base) result__ = NULL; \
598 while (start__ < end__) { \
599 unsigned int mid__ = start__ + (end__ - start__) / 2; \
600 int ret__ = (cmp)((key), (base) + mid__); \
603 } else if (ret__ > 0) { \
604 start__ = mid__ + 1; \
606 result__ = (base) + mid__; \
613 static enum forcewake_domains
614 find_fw_domain(struct drm_i915_private *dev_priv, u32 offset)
616 const struct intel_forcewake_range *entry;
618 entry = BSEARCH(offset,
619 dev_priv->uncore.fw_domains_table,
620 dev_priv->uncore.fw_domains_table_entries,
623 return entry ? entry->domains : 0;
627 intel_fw_table_check(struct drm_i915_private *dev_priv)
629 const struct intel_forcewake_range *ranges;
630 unsigned int num_ranges;
634 if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG))
637 ranges = dev_priv->uncore.fw_domains_table;
641 num_ranges = dev_priv->uncore.fw_domains_table_entries;
643 for (i = 0, prev = -1; i < num_ranges; i++, ranges++) {
644 WARN_ON_ONCE(prev >= (s32)ranges->start);
645 prev = ranges->start;
646 WARN_ON_ONCE(prev >= (s32)ranges->end);
651 #define GEN_FW_RANGE(s, e, d) \
652 { .start = (s), .end = (e), .domains = (d) }
654 #define HAS_FWTABLE(dev_priv) \
655 (IS_GEN9(dev_priv) || \
656 IS_CHERRYVIEW(dev_priv) || \
657 IS_VALLEYVIEW(dev_priv))
659 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
660 static const struct intel_forcewake_range __vlv_fw_ranges[] = {
661 GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER),
662 GEN_FW_RANGE(0x5000, 0x7fff, FORCEWAKE_RENDER),
663 GEN_FW_RANGE(0xb000, 0x11fff, FORCEWAKE_RENDER),
664 GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
665 GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_MEDIA),
666 GEN_FW_RANGE(0x2e000, 0x2ffff, FORCEWAKE_RENDER),
667 GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
670 #define __fwtable_reg_read_fw_domains(offset) \
672 enum forcewake_domains __fwd = 0; \
673 if (NEEDS_FORCE_WAKE((offset))) \
674 __fwd = find_fw_domain(dev_priv, offset); \
678 /* *Must* be sorted by offset! See intel_shadow_table_check(). */
679 static const i915_reg_t gen8_shadowed_regs[] = {
680 RING_TAIL(RENDER_RING_BASE), /* 0x2000 (base) */
681 GEN6_RPNSWREQ, /* 0xA008 */
682 GEN6_RC_VIDEO_FREQ, /* 0xA00C */
683 RING_TAIL(GEN6_BSD_RING_BASE), /* 0x12000 (base) */
684 RING_TAIL(VEBOX_RING_BASE), /* 0x1a000 (base) */
685 RING_TAIL(BLT_RING_BASE), /* 0x22000 (base) */
686 /* TODO: Other registers are not yet used */
689 static void intel_shadow_table_check(void)
691 const i915_reg_t *reg = gen8_shadowed_regs;
696 if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG))
699 for (i = 0, prev = -1; i < ARRAY_SIZE(gen8_shadowed_regs); i++, reg++) {
700 offset = i915_mmio_reg_offset(*reg);
701 WARN_ON_ONCE(prev >= (s32)offset);
706 static int mmio_reg_cmp(u32 key, const i915_reg_t *reg)
708 u32 offset = i915_mmio_reg_offset(*reg);
712 else if (key > offset)
718 static bool is_gen8_shadowed(u32 offset)
720 const i915_reg_t *regs = gen8_shadowed_regs;
722 return BSEARCH(offset, regs, ARRAY_SIZE(gen8_shadowed_regs),
726 #define __gen8_reg_write_fw_domains(offset) \
728 enum forcewake_domains __fwd; \
729 if (NEEDS_FORCE_WAKE(offset) && !is_gen8_shadowed(offset)) \
730 __fwd = FORCEWAKE_RENDER; \
736 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
737 static const struct intel_forcewake_range __chv_fw_ranges[] = {
738 GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER),
739 GEN_FW_RANGE(0x4000, 0x4fff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
740 GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
741 GEN_FW_RANGE(0x8000, 0x82ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
742 GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
743 GEN_FW_RANGE(0x8500, 0x85ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
744 GEN_FW_RANGE(0x8800, 0x88ff, FORCEWAKE_MEDIA),
745 GEN_FW_RANGE(0x9000, 0xafff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
746 GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
747 GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA),
748 GEN_FW_RANGE(0xe000, 0xe7ff, FORCEWAKE_RENDER),
749 GEN_FW_RANGE(0xf000, 0xffff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
750 GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
751 GEN_FW_RANGE(0x1a000, 0x1bfff, FORCEWAKE_MEDIA),
752 GEN_FW_RANGE(0x1e800, 0x1e9ff, FORCEWAKE_MEDIA),
753 GEN_FW_RANGE(0x30000, 0x37fff, FORCEWAKE_MEDIA),
756 #define __fwtable_reg_write_fw_domains(offset) \
758 enum forcewake_domains __fwd = 0; \
759 if (NEEDS_FORCE_WAKE((offset)) && !is_gen8_shadowed(offset)) \
760 __fwd = find_fw_domain(dev_priv, offset); \
764 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
765 static const struct intel_forcewake_range __gen9_fw_ranges[] = {
766 GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER),
767 GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */
768 GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
769 GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER),
770 GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
771 GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER),
772 GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
773 GEN_FW_RANGE(0x8000, 0x812f, FORCEWAKE_BLITTER),
774 GEN_FW_RANGE(0x8130, 0x813f, FORCEWAKE_MEDIA),
775 GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
776 GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER),
777 GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
778 GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_BLITTER),
779 GEN_FW_RANGE(0x8800, 0x89ff, FORCEWAKE_MEDIA),
780 GEN_FW_RANGE(0x8a00, 0x8bff, FORCEWAKE_BLITTER),
781 GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
782 GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER),
783 GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
784 GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER),
785 GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
786 GEN_FW_RANGE(0xb480, 0xbfff, FORCEWAKE_BLITTER),
787 GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA),
788 GEN_FW_RANGE(0xd800, 0xdfff, FORCEWAKE_BLITTER),
789 GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER),
790 GEN_FW_RANGE(0xe900, 0x11fff, FORCEWAKE_BLITTER),
791 GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
792 GEN_FW_RANGE(0x14000, 0x19fff, FORCEWAKE_BLITTER),
793 GEN_FW_RANGE(0x1a000, 0x1e9ff, FORCEWAKE_MEDIA),
794 GEN_FW_RANGE(0x1ea00, 0x243ff, FORCEWAKE_BLITTER),
795 GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER),
796 GEN_FW_RANGE(0x24800, 0x2ffff, FORCEWAKE_BLITTER),
797 GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
801 ilk_dummy_write(struct drm_i915_private *dev_priv)
803 /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
804 * the chip from rc6 before touching it for real. MI_MODE is masked,
805 * hence harmless to write 0 into. */
806 __raw_i915_write32(dev_priv, MI_MODE, 0);
810 __unclaimed_reg_debug(struct drm_i915_private *dev_priv,
811 const i915_reg_t reg,
815 if (WARN(check_for_unclaimed_mmio(dev_priv) && !before,
816 "Unclaimed %s register 0x%x\n",
817 read ? "read from" : "write to",
818 i915_mmio_reg_offset(reg)))
819 i915.mmio_debug--; /* Only report the first N failures */
823 unclaimed_reg_debug(struct drm_i915_private *dev_priv,
824 const i915_reg_t reg,
828 if (likely(!i915.mmio_debug))
831 __unclaimed_reg_debug(dev_priv, reg, read, before);
834 #define GEN2_READ_HEADER(x) \
836 assert_rpm_wakelock_held(dev_priv);
838 #define GEN2_READ_FOOTER \
839 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
842 #define __gen2_read(x) \
844 gen2_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
845 GEN2_READ_HEADER(x); \
846 val = __raw_i915_read##x(dev_priv, reg); \
850 #define __gen5_read(x) \
852 gen5_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
853 GEN2_READ_HEADER(x); \
854 ilk_dummy_write(dev_priv); \
855 val = __raw_i915_read##x(dev_priv, reg); \
871 #undef GEN2_READ_FOOTER
872 #undef GEN2_READ_HEADER
874 #define GEN6_READ_HEADER(x) \
875 u32 offset = i915_mmio_reg_offset(reg); \
876 unsigned long irqflags; \
878 assert_rpm_wakelock_held(dev_priv); \
879 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \
880 unclaimed_reg_debug(dev_priv, reg, true, true)
882 #define GEN6_READ_FOOTER \
883 unclaimed_reg_debug(dev_priv, reg, true, false); \
884 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
885 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
888 static noinline void ___force_wake_auto(struct drm_i915_private *dev_priv,
889 enum forcewake_domains fw_domains)
891 struct intel_uncore_forcewake_domain *domain;
893 for_each_fw_domain_masked(domain, fw_domains, dev_priv)
894 fw_domain_arm_timer(domain);
896 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
897 dev_priv->uncore.fw_domains_active |= fw_domains;
900 static inline void __force_wake_auto(struct drm_i915_private *dev_priv,
901 enum forcewake_domains fw_domains)
903 if (WARN_ON(!fw_domains))
906 /* Turn on all requested but inactive supported forcewake domains. */
907 fw_domains &= dev_priv->uncore.fw_domains;
908 fw_domains &= ~dev_priv->uncore.fw_domains_active;
911 ___force_wake_auto(dev_priv, fw_domains);
914 #define __gen6_read(x) \
916 gen6_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
917 enum forcewake_domains fw_engine; \
918 GEN6_READ_HEADER(x); \
919 fw_engine = __gen6_reg_read_fw_domains(offset); \
921 __force_wake_auto(dev_priv, fw_engine); \
922 val = __raw_i915_read##x(dev_priv, reg); \
926 #define __fwtable_read(x) \
928 fwtable_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
929 enum forcewake_domains fw_engine; \
930 GEN6_READ_HEADER(x); \
931 fw_engine = __fwtable_reg_read_fw_domains(offset); \
933 __force_wake_auto(dev_priv, fw_engine); \
934 val = __raw_i915_read##x(dev_priv, reg); \
947 #undef __fwtable_read
949 #undef GEN6_READ_FOOTER
950 #undef GEN6_READ_HEADER
952 #define VGPU_READ_HEADER(x) \
953 unsigned long irqflags; \
955 assert_rpm_device_not_suspended(dev_priv); \
956 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
958 #define VGPU_READ_FOOTER \
959 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
960 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
963 #define __vgpu_read(x) \
965 vgpu_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
966 VGPU_READ_HEADER(x); \
967 val = __raw_i915_read##x(dev_priv, reg); \
977 #undef VGPU_READ_FOOTER
978 #undef VGPU_READ_HEADER
980 #define GEN2_WRITE_HEADER \
981 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
982 assert_rpm_wakelock_held(dev_priv); \
984 #define GEN2_WRITE_FOOTER
986 #define __gen2_write(x) \
988 gen2_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
990 __raw_i915_write##x(dev_priv, reg, val); \
994 #define __gen5_write(x) \
996 gen5_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
998 ilk_dummy_write(dev_priv); \
999 __raw_i915_write##x(dev_priv, reg, val); \
1000 GEN2_WRITE_FOOTER; \
1013 #undef GEN2_WRITE_FOOTER
1014 #undef GEN2_WRITE_HEADER
1016 #define GEN6_WRITE_HEADER \
1017 u32 offset = i915_mmio_reg_offset(reg); \
1018 unsigned long irqflags; \
1019 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1020 assert_rpm_wakelock_held(dev_priv); \
1021 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \
1022 unclaimed_reg_debug(dev_priv, reg, false, true)
1024 #define GEN6_WRITE_FOOTER \
1025 unclaimed_reg_debug(dev_priv, reg, false, false); \
1026 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
1028 #define __gen6_write(x) \
1030 gen6_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1031 u32 __fifo_ret = 0; \
1032 GEN6_WRITE_HEADER; \
1033 if (NEEDS_FORCE_WAKE(offset)) { \
1034 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1036 __raw_i915_write##x(dev_priv, reg, val); \
1037 if (unlikely(__fifo_ret)) { \
1038 gen6_gt_check_fifodbg(dev_priv); \
1040 GEN6_WRITE_FOOTER; \
1043 #define __gen8_write(x) \
1045 gen8_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1046 enum forcewake_domains fw_engine; \
1047 GEN6_WRITE_HEADER; \
1048 fw_engine = __gen8_reg_write_fw_domains(offset); \
1050 __force_wake_auto(dev_priv, fw_engine); \
1051 __raw_i915_write##x(dev_priv, reg, val); \
1052 GEN6_WRITE_FOOTER; \
1055 #define __fwtable_write(x) \
1057 fwtable_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1058 enum forcewake_domains fw_engine; \
1059 GEN6_WRITE_HEADER; \
1060 fw_engine = __fwtable_reg_write_fw_domains(offset); \
1062 __force_wake_auto(dev_priv, fw_engine); \
1063 __raw_i915_write##x(dev_priv, reg, val); \
1064 GEN6_WRITE_FOOTER; \
1077 #undef __fwtable_write
1080 #undef GEN6_WRITE_FOOTER
1081 #undef GEN6_WRITE_HEADER
1083 #define VGPU_WRITE_HEADER \
1084 unsigned long irqflags; \
1085 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1086 assert_rpm_device_not_suspended(dev_priv); \
1087 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
1089 #define VGPU_WRITE_FOOTER \
1090 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
1092 #define __vgpu_write(x) \
1093 static void vgpu_write##x(struct drm_i915_private *dev_priv, \
1094 i915_reg_t reg, u##x val, bool trace) { \
1095 VGPU_WRITE_HEADER; \
1096 __raw_i915_write##x(dev_priv, reg, val); \
1097 VGPU_WRITE_FOOTER; \
1105 #undef VGPU_WRITE_FOOTER
1106 #undef VGPU_WRITE_HEADER
1108 #define ASSIGN_WRITE_MMIO_VFUNCS(x) \
1110 dev_priv->uncore.funcs.mmio_writeb = x##_write8; \
1111 dev_priv->uncore.funcs.mmio_writew = x##_write16; \
1112 dev_priv->uncore.funcs.mmio_writel = x##_write32; \
1115 #define ASSIGN_READ_MMIO_VFUNCS(x) \
1117 dev_priv->uncore.funcs.mmio_readb = x##_read8; \
1118 dev_priv->uncore.funcs.mmio_readw = x##_read16; \
1119 dev_priv->uncore.funcs.mmio_readl = x##_read32; \
1120 dev_priv->uncore.funcs.mmio_readq = x##_read64; \
1124 static void fw_domain_init(struct drm_i915_private *dev_priv,
1125 enum forcewake_domain_id domain_id,
1129 struct intel_uncore_forcewake_domain *d;
1131 if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT))
1134 d = &dev_priv->uncore.fw_domain[domain_id];
1136 WARN_ON(d->wake_count);
1139 d->reg_set = reg_set;
1140 d->reg_ack = reg_ack;
1142 if (IS_GEN6(dev_priv)) {
1144 d->val_set = FORCEWAKE_KERNEL;
1147 /* WaRsClearFWBitsAtReset:bdw,skl */
1148 d->val_reset = _MASKED_BIT_DISABLE(0xffff);
1149 d->val_set = _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL);
1150 d->val_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL);
1153 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1154 d->reg_post = FORCEWAKE_ACK_VLV;
1155 else if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv) || IS_GEN8(dev_priv))
1156 d->reg_post = ECOBUS;
1161 BUILD_BUG_ON(FORCEWAKE_RENDER != (1 << FW_DOMAIN_ID_RENDER));
1162 BUILD_BUG_ON(FORCEWAKE_BLITTER != (1 << FW_DOMAIN_ID_BLITTER));
1163 BUILD_BUG_ON(FORCEWAKE_MEDIA != (1 << FW_DOMAIN_ID_MEDIA));
1165 d->mask = 1 << domain_id;
1167 hrtimer_init(&d->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1168 d->timer.function = intel_uncore_fw_release_timer;
1170 dev_priv->uncore.fw_domains |= (1 << domain_id);
1175 static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
1177 if (INTEL_INFO(dev_priv)->gen <= 5)
1180 if (IS_GEN9(dev_priv)) {
1181 dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
1182 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1183 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1184 FORCEWAKE_RENDER_GEN9,
1185 FORCEWAKE_ACK_RENDER_GEN9);
1186 fw_domain_init(dev_priv, FW_DOMAIN_ID_BLITTER,
1187 FORCEWAKE_BLITTER_GEN9,
1188 FORCEWAKE_ACK_BLITTER_GEN9);
1189 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
1190 FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
1191 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1192 dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
1193 if (!IS_CHERRYVIEW(dev_priv))
1194 dev_priv->uncore.funcs.force_wake_put =
1195 fw_domains_put_with_fifo;
1197 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1198 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1199 FORCEWAKE_VLV, FORCEWAKE_ACK_VLV);
1200 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
1201 FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV);
1202 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1203 dev_priv->uncore.funcs.force_wake_get =
1204 fw_domains_get_with_thread_status;
1205 if (IS_HASWELL(dev_priv))
1206 dev_priv->uncore.funcs.force_wake_put =
1207 fw_domains_put_with_fifo;
1209 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1210 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1211 FORCEWAKE_MT, FORCEWAKE_ACK_HSW);
1212 } else if (IS_IVYBRIDGE(dev_priv)) {
1215 /* IVB configs may use multi-threaded forcewake */
1217 /* A small trick here - if the bios hasn't configured
1218 * MT forcewake, and if the device is in RC6, then
1219 * force_wake_mt_get will not wake the device and the
1220 * ECOBUS read will return zero. Which will be
1221 * (correctly) interpreted by the test below as MT
1222 * forcewake being disabled.
1224 dev_priv->uncore.funcs.force_wake_get =
1225 fw_domains_get_with_thread_status;
1226 dev_priv->uncore.funcs.force_wake_put =
1227 fw_domains_put_with_fifo;
1229 /* We need to init first for ECOBUS access and then
1230 * determine later if we want to reinit, in case of MT access is
1231 * not working. In this stage we don't know which flavour this
1232 * ivb is, so it is better to reset also the gen6 fw registers
1233 * before the ecobus check.
1236 __raw_i915_write32(dev_priv, FORCEWAKE, 0);
1237 __raw_posting_read(dev_priv, ECOBUS);
1239 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1240 FORCEWAKE_MT, FORCEWAKE_MT_ACK);
1242 spin_lock_irq(&dev_priv->uncore.lock);
1243 fw_domains_get_with_thread_status(dev_priv, FORCEWAKE_ALL);
1244 ecobus = __raw_i915_read32(dev_priv, ECOBUS);
1245 fw_domains_put_with_fifo(dev_priv, FORCEWAKE_ALL);
1246 spin_unlock_irq(&dev_priv->uncore.lock);
1248 if (!(ecobus & FORCEWAKE_MT_ENABLE)) {
1249 DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
1250 DRM_INFO("when using vblank-synced partial screen updates.\n");
1251 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1252 FORCEWAKE, FORCEWAKE_ACK);
1254 } else if (IS_GEN6(dev_priv)) {
1255 dev_priv->uncore.funcs.force_wake_get =
1256 fw_domains_get_with_thread_status;
1257 dev_priv->uncore.funcs.force_wake_put =
1258 fw_domains_put_with_fifo;
1259 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1260 FORCEWAKE, FORCEWAKE_ACK);
1263 /* All future platforms are expected to require complex power gating */
1264 WARN_ON(dev_priv->uncore.fw_domains == 0);
1267 #define ASSIGN_FW_DOMAINS_TABLE(d) \
1269 dev_priv->uncore.fw_domains_table = \
1270 (struct intel_forcewake_range *)(d); \
1271 dev_priv->uncore.fw_domains_table_entries = ARRAY_SIZE((d)); \
1274 void intel_uncore_init(struct drm_i915_private *dev_priv)
1276 i915_check_vgpu(dev_priv);
1278 intel_uncore_edram_detect(dev_priv);
1279 intel_uncore_fw_domains_init(dev_priv);
1280 __intel_uncore_early_sanitize(dev_priv, false);
1282 dev_priv->uncore.unclaimed_mmio_check = 1;
1284 switch (INTEL_INFO(dev_priv)->gen) {
1287 ASSIGN_FW_DOMAINS_TABLE(__gen9_fw_ranges);
1288 ASSIGN_WRITE_MMIO_VFUNCS(fwtable);
1289 ASSIGN_READ_MMIO_VFUNCS(fwtable);
1292 if (IS_CHERRYVIEW(dev_priv)) {
1293 ASSIGN_FW_DOMAINS_TABLE(__chv_fw_ranges);
1294 ASSIGN_WRITE_MMIO_VFUNCS(fwtable);
1295 ASSIGN_READ_MMIO_VFUNCS(fwtable);
1298 ASSIGN_WRITE_MMIO_VFUNCS(gen8);
1299 ASSIGN_READ_MMIO_VFUNCS(gen6);
1304 ASSIGN_WRITE_MMIO_VFUNCS(gen6);
1306 if (IS_VALLEYVIEW(dev_priv)) {
1307 ASSIGN_FW_DOMAINS_TABLE(__vlv_fw_ranges);
1308 ASSIGN_READ_MMIO_VFUNCS(fwtable);
1310 ASSIGN_READ_MMIO_VFUNCS(gen6);
1314 ASSIGN_WRITE_MMIO_VFUNCS(gen5);
1315 ASSIGN_READ_MMIO_VFUNCS(gen5);
1320 ASSIGN_WRITE_MMIO_VFUNCS(gen2);
1321 ASSIGN_READ_MMIO_VFUNCS(gen2);
1325 intel_fw_table_check(dev_priv);
1326 if (INTEL_GEN(dev_priv) >= 8)
1327 intel_shadow_table_check();
1329 if (intel_vgpu_active(dev_priv)) {
1330 ASSIGN_WRITE_MMIO_VFUNCS(vgpu);
1331 ASSIGN_READ_MMIO_VFUNCS(vgpu);
1334 i915_check_and_clear_faults(dev_priv);
1336 #undef ASSIGN_WRITE_MMIO_VFUNCS
1337 #undef ASSIGN_READ_MMIO_VFUNCS
1339 void intel_uncore_fini(struct drm_i915_private *dev_priv)
1341 /* Paranoia: make sure we have disabled everything before we exit. */
1342 intel_uncore_sanitize(dev_priv);
1343 intel_uncore_forcewake_reset(dev_priv, false);
1346 #define GEN_RANGE(l, h) GENMASK((h) - 1, (l) - 1)
1348 static const struct register_whitelist {
1349 i915_reg_t offset_ldw, offset_udw;
1351 /* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
1352 uint32_t gen_bitmask;
1354 { .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
1355 .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
1356 .size = 8, .gen_bitmask = GEN_RANGE(4, 9) },
1359 int i915_reg_read_ioctl(struct drm_device *dev,
1360 void *data, struct drm_file *file)
1362 struct drm_i915_private *dev_priv = to_i915(dev);
1363 struct drm_i915_reg_read *reg = data;
1364 struct register_whitelist const *entry = whitelist;
1366 i915_reg_t offset_ldw, offset_udw;
1369 for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
1370 if (i915_mmio_reg_offset(entry->offset_ldw) == (reg->offset & -entry->size) &&
1371 (INTEL_INFO(dev)->gen_mask & entry->gen_bitmask))
1375 if (i == ARRAY_SIZE(whitelist))
1378 /* We use the low bits to encode extra flags as the register should
1379 * be naturally aligned (and those that are not so aligned merely
1380 * limit the available flags for that register).
1382 offset_ldw = entry->offset_ldw;
1383 offset_udw = entry->offset_udw;
1385 size |= reg->offset ^ i915_mmio_reg_offset(offset_ldw);
1387 intel_runtime_pm_get(dev_priv);
1391 reg->val = I915_READ64_2x32(offset_ldw, offset_udw);
1394 reg->val = I915_READ64(offset_ldw);
1397 reg->val = I915_READ(offset_ldw);
1400 reg->val = I915_READ16(offset_ldw);
1403 reg->val = I915_READ8(offset_ldw);
1411 intel_runtime_pm_put(dev_priv);
1415 static int i915_reset_complete(struct pci_dev *pdev)
1418 pci_read_config_byte(pdev, I915_GDRST, &gdrst);
1419 return (gdrst & GRDOM_RESET_STATUS) == 0;
1422 static int i915_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask)
1424 struct pci_dev *pdev = dev_priv->drm.pdev;
1426 /* assert reset for at least 20 usec */
1427 pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1429 pci_write_config_byte(pdev, I915_GDRST, 0);
1431 return wait_for(i915_reset_complete(pdev), 500);
1434 static int g4x_reset_complete(struct pci_dev *pdev)
1437 pci_read_config_byte(pdev, I915_GDRST, &gdrst);
1438 return (gdrst & GRDOM_RESET_ENABLE) == 0;
1441 static int g33_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask)
1443 struct pci_dev *pdev = dev_priv->drm.pdev;
1444 pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1445 return wait_for(g4x_reset_complete(pdev), 500);
1448 static int g4x_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask)
1450 struct pci_dev *pdev = dev_priv->drm.pdev;
1453 pci_write_config_byte(pdev, I915_GDRST,
1454 GRDOM_RENDER | GRDOM_RESET_ENABLE);
1455 ret = wait_for(g4x_reset_complete(pdev), 500);
1459 /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1460 I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE);
1461 POSTING_READ(VDECCLK_GATE_D);
1463 pci_write_config_byte(pdev, I915_GDRST,
1464 GRDOM_MEDIA | GRDOM_RESET_ENABLE);
1465 ret = wait_for(g4x_reset_complete(pdev), 500);
1469 /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1470 I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE);
1471 POSTING_READ(VDECCLK_GATE_D);
1473 pci_write_config_byte(pdev, I915_GDRST, 0);
1478 static int ironlake_do_reset(struct drm_i915_private *dev_priv,
1479 unsigned engine_mask)
1483 I915_WRITE(ILK_GDSR,
1484 ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
1485 ret = intel_wait_for_register(dev_priv,
1486 ILK_GDSR, ILK_GRDOM_RESET_ENABLE, 0,
1491 I915_WRITE(ILK_GDSR,
1492 ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
1493 ret = intel_wait_for_register(dev_priv,
1494 ILK_GDSR, ILK_GRDOM_RESET_ENABLE, 0,
1499 I915_WRITE(ILK_GDSR, 0);
1504 /* Reset the hardware domains (GENX_GRDOM_*) specified by mask */
1505 static int gen6_hw_domain_reset(struct drm_i915_private *dev_priv,
1508 /* GEN6_GDRST is not in the gt power well, no need to check
1509 * for fifo space for the write or forcewake the chip for
1512 __raw_i915_write32(dev_priv, GEN6_GDRST, hw_domain_mask);
1514 /* Spin waiting for the device to ack the reset requests */
1515 return intel_wait_for_register_fw(dev_priv,
1516 GEN6_GDRST, hw_domain_mask, 0,
1521 * gen6_reset_engines - reset individual engines
1522 * @dev_priv: i915 device
1523 * @engine_mask: mask of intel_ring_flag() engines or ALL_ENGINES for full reset
1525 * This function will reset the individual engines that are set in engine_mask.
1526 * If you provide ALL_ENGINES as mask, full global domain reset will be issued.
1528 * Note: It is responsibility of the caller to handle the difference between
1529 * asking full domain reset versus reset for all available individual engines.
1531 * Returns 0 on success, nonzero on error.
1533 static int gen6_reset_engines(struct drm_i915_private *dev_priv,
1534 unsigned engine_mask)
1536 struct intel_engine_cs *engine;
1537 const u32 hw_engine_mask[I915_NUM_ENGINES] = {
1538 [RCS] = GEN6_GRDOM_RENDER,
1539 [BCS] = GEN6_GRDOM_BLT,
1540 [VCS] = GEN6_GRDOM_MEDIA,
1541 [VCS2] = GEN8_GRDOM_MEDIA2,
1542 [VECS] = GEN6_GRDOM_VECS,
1547 if (engine_mask == ALL_ENGINES) {
1548 hw_mask = GEN6_GRDOM_FULL;
1553 for_each_engine_masked(engine, dev_priv, engine_mask, tmp)
1554 hw_mask |= hw_engine_mask[engine->id];
1557 ret = gen6_hw_domain_reset(dev_priv, hw_mask);
1559 intel_uncore_forcewake_reset(dev_priv, true);
1565 * intel_wait_for_register_fw - wait until register matches expected state
1566 * @dev_priv: the i915 device
1567 * @reg: the register to read
1568 * @mask: mask to apply to register value
1569 * @value: expected value
1570 * @timeout_ms: timeout in millisecond
1572 * This routine waits until the target register @reg contains the expected
1573 * @value after applying the @mask, i.e. it waits until ::
1575 * (I915_READ_FW(reg) & mask) == value
1577 * Otherwise, the wait will timeout after @timeout_ms milliseconds.
1579 * Note that this routine assumes the caller holds forcewake asserted, it is
1580 * not suitable for very long waits. See intel_wait_for_register() if you
1581 * wish to wait without holding forcewake for the duration (i.e. you expect
1582 * the wait to be slow).
1584 * Returns 0 if the register matches the desired condition, or -ETIMEOUT.
1586 int intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
1590 const unsigned long timeout_ms)
1592 #define done ((I915_READ_FW(reg) & mask) == value)
1593 int ret = wait_for_us(done, 2);
1595 ret = wait_for(done, timeout_ms);
1601 * intel_wait_for_register - wait until register matches expected state
1602 * @dev_priv: the i915 device
1603 * @reg: the register to read
1604 * @mask: mask to apply to register value
1605 * @value: expected value
1606 * @timeout_ms: timeout in millisecond
1608 * This routine waits until the target register @reg contains the expected
1609 * @value after applying the @mask, i.e. it waits until ::
1611 * (I915_READ(reg) & mask) == value
1613 * Otherwise, the wait will timeout after @timeout_ms milliseconds.
1615 * Returns 0 if the register matches the desired condition, or -ETIMEOUT.
1617 int intel_wait_for_register(struct drm_i915_private *dev_priv,
1621 const unsigned long timeout_ms)
1625 intel_uncore_forcewake_for_reg(dev_priv, reg, FW_REG_READ);
1628 intel_uncore_forcewake_get(dev_priv, fw);
1629 ret = wait_for_us((I915_READ_FW(reg) & mask) == value, 2);
1630 intel_uncore_forcewake_put(dev_priv, fw);
1632 ret = wait_for((I915_READ_NOTRACE(reg) & mask) == value,
1638 static int gen8_request_engine_reset(struct intel_engine_cs *engine)
1640 struct drm_i915_private *dev_priv = engine->i915;
1643 I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base),
1644 _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET));
1646 ret = intel_wait_for_register_fw(dev_priv,
1647 RING_RESET_CTL(engine->mmio_base),
1648 RESET_CTL_READY_TO_RESET,
1649 RESET_CTL_READY_TO_RESET,
1652 DRM_ERROR("%s: reset request timeout\n", engine->name);
1657 static void gen8_unrequest_engine_reset(struct intel_engine_cs *engine)
1659 struct drm_i915_private *dev_priv = engine->i915;
1661 I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base),
1662 _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET));
1665 static int gen8_reset_engines(struct drm_i915_private *dev_priv,
1666 unsigned engine_mask)
1668 struct intel_engine_cs *engine;
1671 for_each_engine_masked(engine, dev_priv, engine_mask, tmp)
1672 if (gen8_request_engine_reset(engine))
1675 return gen6_reset_engines(dev_priv, engine_mask);
1678 for_each_engine_masked(engine, dev_priv, engine_mask, tmp)
1679 gen8_unrequest_engine_reset(engine);
1684 typedef int (*reset_func)(struct drm_i915_private *, unsigned engine_mask);
1686 static reset_func intel_get_gpu_reset(struct drm_i915_private *dev_priv)
1691 if (INTEL_INFO(dev_priv)->gen >= 8)
1692 return gen8_reset_engines;
1693 else if (INTEL_INFO(dev_priv)->gen >= 6)
1694 return gen6_reset_engines;
1695 else if (IS_GEN5(dev_priv))
1696 return ironlake_do_reset;
1697 else if (IS_G4X(dev_priv))
1698 return g4x_do_reset;
1699 else if (IS_G33(dev_priv))
1700 return g33_do_reset;
1701 else if (INTEL_INFO(dev_priv)->gen >= 3)
1702 return i915_do_reset;
1707 int intel_gpu_reset(struct drm_i915_private *dev_priv, unsigned engine_mask)
1712 reset = intel_get_gpu_reset(dev_priv);
1716 /* If the power well sleeps during the reset, the reset
1717 * request may be dropped and never completes (causing -EIO).
1719 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1720 ret = reset(dev_priv, engine_mask);
1721 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1726 bool intel_has_gpu_reset(struct drm_i915_private *dev_priv)
1728 return intel_get_gpu_reset(dev_priv) != NULL;
1731 int intel_guc_reset(struct drm_i915_private *dev_priv)
1734 unsigned long irqflags;
1736 if (!HAS_GUC(dev_priv))
1739 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1740 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1742 ret = gen6_hw_domain_reset(dev_priv, GEN9_GRDOM_GUC);
1744 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1745 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1750 bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv)
1752 return check_for_unclaimed_mmio(dev_priv);
1756 intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv)
1758 if (unlikely(i915.mmio_debug ||
1759 dev_priv->uncore.unclaimed_mmio_check <= 0))
1762 if (unlikely(intel_uncore_unclaimed_mmio(dev_priv))) {
1763 DRM_DEBUG("Unclaimed register detected, "
1764 "enabling oneshot unclaimed register reporting. "
1765 "Please use i915.mmio_debug=N for more information.\n");
1767 dev_priv->uncore.unclaimed_mmio_check--;
1774 static enum forcewake_domains
1775 intel_uncore_forcewake_for_read(struct drm_i915_private *dev_priv,
1778 u32 offset = i915_mmio_reg_offset(reg);
1779 enum forcewake_domains fw_domains;
1781 if (HAS_FWTABLE(dev_priv)) {
1782 fw_domains = __fwtable_reg_read_fw_domains(offset);
1783 } else if (INTEL_GEN(dev_priv) >= 6) {
1784 fw_domains = __gen6_reg_read_fw_domains(offset);
1786 WARN_ON(!IS_GEN(dev_priv, 2, 5));
1790 WARN_ON(fw_domains & ~dev_priv->uncore.fw_domains);
1795 static enum forcewake_domains
1796 intel_uncore_forcewake_for_write(struct drm_i915_private *dev_priv,
1799 u32 offset = i915_mmio_reg_offset(reg);
1800 enum forcewake_domains fw_domains;
1802 if (HAS_FWTABLE(dev_priv) && !IS_VALLEYVIEW(dev_priv)) {
1803 fw_domains = __fwtable_reg_write_fw_domains(offset);
1804 } else if (IS_GEN8(dev_priv)) {
1805 fw_domains = __gen8_reg_write_fw_domains(offset);
1806 } else if (IS_GEN(dev_priv, 6, 7)) {
1807 fw_domains = FORCEWAKE_RENDER;
1809 WARN_ON(!IS_GEN(dev_priv, 2, 5));
1813 WARN_ON(fw_domains & ~dev_priv->uncore.fw_domains);
1819 * intel_uncore_forcewake_for_reg - which forcewake domains are needed to access
1821 * @dev_priv: pointer to struct drm_i915_private
1822 * @reg: register in question
1823 * @op: operation bitmask of FW_REG_READ and/or FW_REG_WRITE
1825 * Returns a set of forcewake domains required to be taken with for example
1826 * intel_uncore_forcewake_get for the specified register to be accessible in the
1827 * specified mode (read, write or read/write) with raw mmio accessors.
1829 * NOTE: On Gen6 and Gen7 write forcewake domain (FORCEWAKE_RENDER) requires the
1830 * callers to do FIFO management on their own or risk losing writes.
1832 enum forcewake_domains
1833 intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
1834 i915_reg_t reg, unsigned int op)
1836 enum forcewake_domains fw_domains = 0;
1840 if (intel_vgpu_active(dev_priv))
1843 if (op & FW_REG_READ)
1844 fw_domains = intel_uncore_forcewake_for_read(dev_priv, reg);
1846 if (op & FW_REG_WRITE)
1847 fw_domains |= intel_uncore_forcewake_for_write(dev_priv, reg);