2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "intel_drv.h"
26 #include "i915_vgpu.h"
28 #include <linux/pm_runtime.h>
30 #define FORCEWAKE_ACK_TIMEOUT_MS 50
32 #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32((dev_priv__), (reg__))
34 static const char * const forcewake_domain_names[] = {
41 intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id)
43 BUILD_BUG_ON(ARRAY_SIZE(forcewake_domain_names) != FW_DOMAIN_ID_COUNT);
45 if (id >= 0 && id < FW_DOMAIN_ID_COUNT)
46 return forcewake_domain_names[id];
54 fw_domain_reset(const struct intel_uncore_forcewake_domain *d)
56 WARN_ON(!i915_mmio_reg_valid(d->reg_set));
57 __raw_i915_write32(d->i915, d->reg_set, d->val_reset);
61 fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d)
64 hrtimer_start_range_ns(&d->timer,
65 ktime_set(0, NSEC_PER_MSEC),
71 fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d)
73 if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) &
74 FORCEWAKE_KERNEL) == 0,
75 FORCEWAKE_ACK_TIMEOUT_MS))
76 DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n",
77 intel_uncore_forcewake_domain_to_str(d->id));
81 fw_domain_get(const struct intel_uncore_forcewake_domain *d)
83 __raw_i915_write32(d->i915, d->reg_set, d->val_set);
87 fw_domain_wait_ack(const struct intel_uncore_forcewake_domain *d)
89 if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) &
91 FORCEWAKE_ACK_TIMEOUT_MS))
92 DRM_ERROR("%s: timed out waiting for forcewake ack request.\n",
93 intel_uncore_forcewake_domain_to_str(d->id));
97 fw_domain_put(const struct intel_uncore_forcewake_domain *d)
99 __raw_i915_write32(d->i915, d->reg_set, d->val_clear);
103 fw_domain_posting_read(const struct intel_uncore_forcewake_domain *d)
105 /* something from same cacheline, but not from the set register */
106 if (i915_mmio_reg_valid(d->reg_post))
107 __raw_posting_read(d->i915, d->reg_post);
111 fw_domains_get(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
113 struct intel_uncore_forcewake_domain *d;
115 for_each_fw_domain_masked(d, fw_domains, dev_priv) {
116 fw_domain_wait_ack_clear(d);
120 for_each_fw_domain_masked(d, fw_domains, dev_priv)
121 fw_domain_wait_ack(d);
125 fw_domains_put(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
127 struct intel_uncore_forcewake_domain *d;
129 for_each_fw_domain_masked(d, fw_domains, dev_priv) {
131 fw_domain_posting_read(d);
136 fw_domains_posting_read(struct drm_i915_private *dev_priv)
138 struct intel_uncore_forcewake_domain *d;
140 /* No need to do for all, just do for first found */
141 for_each_fw_domain(d, dev_priv) {
142 fw_domain_posting_read(d);
148 fw_domains_reset(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
150 struct intel_uncore_forcewake_domain *d;
152 if (dev_priv->uncore.fw_domains == 0)
155 for_each_fw_domain_masked(d, fw_domains, dev_priv)
158 fw_domains_posting_read(dev_priv);
161 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
163 /* w/a for a sporadic read returning 0 by waiting for the GT
166 if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) &
167 GEN6_GT_THREAD_STATUS_CORE_MASK) == 0, 500))
168 DRM_ERROR("GT thread status wait timed out\n");
171 static void fw_domains_get_with_thread_status(struct drm_i915_private *dev_priv,
172 enum forcewake_domains fw_domains)
174 fw_domains_get(dev_priv, fw_domains);
176 /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */
177 __gen6_gt_wait_for_thread_c0(dev_priv);
180 static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
184 gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG);
185 if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg))
186 __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg);
189 static void fw_domains_put_with_fifo(struct drm_i915_private *dev_priv,
190 enum forcewake_domains fw_domains)
192 fw_domains_put(dev_priv, fw_domains);
193 gen6_gt_check_fifodbg(dev_priv);
196 static inline u32 fifo_free_entries(struct drm_i915_private *dev_priv)
198 u32 count = __raw_i915_read32(dev_priv, GTFIFOCTL);
200 return count & GT_FIFO_FREE_ENTRIES_MASK;
203 static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
207 /* On VLV, FIFO will be shared by both SW and HW.
208 * So, we need to read the FREE_ENTRIES everytime */
209 if (IS_VALLEYVIEW(dev_priv))
210 dev_priv->uncore.fifo_count = fifo_free_entries(dev_priv);
212 if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
214 u32 fifo = fifo_free_entries(dev_priv);
216 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
218 fifo = fifo_free_entries(dev_priv);
220 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
222 dev_priv->uncore.fifo_count = fifo;
224 dev_priv->uncore.fifo_count--;
229 static enum hrtimer_restart
230 intel_uncore_fw_release_timer(struct hrtimer *timer)
232 struct intel_uncore_forcewake_domain *domain =
233 container_of(timer, struct intel_uncore_forcewake_domain, timer);
234 unsigned long irqflags;
236 assert_rpm_device_not_suspended(domain->i915);
238 spin_lock_irqsave(&domain->i915->uncore.lock, irqflags);
239 if (WARN_ON(domain->wake_count == 0))
240 domain->wake_count++;
242 if (--domain->wake_count == 0)
243 domain->i915->uncore.funcs.force_wake_put(domain->i915,
246 spin_unlock_irqrestore(&domain->i915->uncore.lock, irqflags);
248 return HRTIMER_NORESTART;
251 void intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv,
254 unsigned long irqflags;
255 struct intel_uncore_forcewake_domain *domain;
256 int retry_count = 100;
257 enum forcewake_domains fw = 0, active_domains;
259 /* Hold uncore.lock across reset to prevent any register access
260 * with forcewake not set correctly. Wait until all pending
261 * timers are run before holding.
266 for_each_fw_domain(domain, dev_priv) {
267 if (hrtimer_cancel(&domain->timer) == 0)
270 intel_uncore_fw_release_timer(&domain->timer);
273 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
275 for_each_fw_domain(domain, dev_priv) {
276 if (hrtimer_active(&domain->timer))
277 active_domains |= domain->mask;
280 if (active_domains == 0)
283 if (--retry_count == 0) {
284 DRM_ERROR("Timed out waiting for forcewake timers to finish\n");
288 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
292 WARN_ON(active_domains);
294 for_each_fw_domain(domain, dev_priv)
295 if (domain->wake_count)
299 dev_priv->uncore.funcs.force_wake_put(dev_priv, fw);
301 fw_domains_reset(dev_priv, FORCEWAKE_ALL);
303 if (restore) { /* If reset with a user forcewake, try to restore */
305 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw);
307 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv))
308 dev_priv->uncore.fifo_count =
309 fifo_free_entries(dev_priv);
313 assert_forcewakes_inactive(dev_priv);
315 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
318 static u64 gen9_edram_size(struct drm_i915_private *dev_priv)
320 const unsigned int ways[8] = { 4, 8, 12, 16, 16, 16, 16, 16 };
321 const unsigned int sets[4] = { 1, 1, 2, 2 };
322 const u32 cap = dev_priv->edram_cap;
324 return EDRAM_NUM_BANKS(cap) *
325 ways[EDRAM_WAYS_IDX(cap)] *
326 sets[EDRAM_SETS_IDX(cap)] *
330 u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv)
332 if (!HAS_EDRAM(dev_priv))
335 /* The needed capability bits for size calculation
336 * are not there with pre gen9 so return 128MB always.
338 if (INTEL_GEN(dev_priv) < 9)
339 return 128 * 1024 * 1024;
341 return gen9_edram_size(dev_priv);
344 static void intel_uncore_edram_detect(struct drm_i915_private *dev_priv)
346 if (IS_HASWELL(dev_priv) ||
347 IS_BROADWELL(dev_priv) ||
348 INTEL_GEN(dev_priv) >= 9) {
349 dev_priv->edram_cap = __raw_i915_read32(dev_priv,
352 /* NB: We can't write IDICR yet because we do not have gt funcs
355 dev_priv->edram_cap = 0;
358 if (HAS_EDRAM(dev_priv))
359 DRM_INFO("Found %lluMB of eDRAM\n",
360 intel_uncore_edram_size(dev_priv) / (1024 * 1024));
364 fpga_check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
368 dbg = __raw_i915_read32(dev_priv, FPGA_DBG);
369 if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM)))
372 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
378 vlv_check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
382 cer = __raw_i915_read32(dev_priv, CLAIM_ER);
383 if (likely(!(cer & (CLAIM_ER_OVERFLOW | CLAIM_ER_CTR_MASK))))
386 __raw_i915_write32(dev_priv, CLAIM_ER, CLAIM_ER_CLR);
392 check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
394 if (HAS_FPGA_DBG_UNCLAIMED(dev_priv))
395 return fpga_check_for_unclaimed_mmio(dev_priv);
397 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
398 return vlv_check_for_unclaimed_mmio(dev_priv);
403 static void __intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
404 bool restore_forcewake)
406 /* clear out unclaimed reg detection bit */
407 if (check_for_unclaimed_mmio(dev_priv))
408 DRM_DEBUG("unclaimed mmio detected on uncore init, clearing\n");
410 /* clear out old GT FIFO errors */
411 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv))
412 __raw_i915_write32(dev_priv, GTFIFODBG,
413 __raw_i915_read32(dev_priv, GTFIFODBG));
415 /* WaDisableShadowRegForCpd:chv */
416 if (IS_CHERRYVIEW(dev_priv)) {
417 __raw_i915_write32(dev_priv, GTFIFOCTL,
418 __raw_i915_read32(dev_priv, GTFIFOCTL) |
419 GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
420 GT_FIFO_CTL_RC6_POLICY_STALL);
423 intel_uncore_forcewake_reset(dev_priv, restore_forcewake);
426 void intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
427 bool restore_forcewake)
429 __intel_uncore_early_sanitize(dev_priv, restore_forcewake);
430 i915_check_and_clear_faults(dev_priv);
433 void intel_uncore_sanitize(struct drm_i915_private *dev_priv)
435 i915.enable_rc6 = sanitize_rc6_option(dev_priv, i915.enable_rc6);
437 /* BIOS often leaves RC6 enabled, but disable it for hw init */
438 intel_sanitize_gt_powersave(dev_priv);
441 static void __intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
442 enum forcewake_domains fw_domains)
444 struct intel_uncore_forcewake_domain *domain;
446 if (!dev_priv->uncore.funcs.force_wake_get)
449 fw_domains &= dev_priv->uncore.fw_domains;
451 for_each_fw_domain_masked(domain, fw_domains, dev_priv) {
452 if (domain->wake_count++)
453 fw_domains &= ~domain->mask;
457 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
461 * intel_uncore_forcewake_get - grab forcewake domain references
462 * @dev_priv: i915 device instance
463 * @fw_domains: forcewake domains to get reference on
465 * This function can be used get GT's forcewake domain references.
466 * Normal register access will handle the forcewake domains automatically.
467 * However if some sequence requires the GT to not power down a particular
468 * forcewake domains this function should be called at the beginning of the
469 * sequence. And subsequently the reference should be dropped by symmetric
470 * call to intel_unforce_forcewake_put(). Usually caller wants all the domains
471 * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL.
473 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
474 enum forcewake_domains fw_domains)
476 unsigned long irqflags;
478 if (!dev_priv->uncore.funcs.force_wake_get)
481 assert_rpm_wakelock_held(dev_priv);
483 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
484 __intel_uncore_forcewake_get(dev_priv, fw_domains);
485 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
489 * intel_uncore_forcewake_get__locked - grab forcewake domain references
490 * @dev_priv: i915 device instance
491 * @fw_domains: forcewake domains to get reference on
493 * See intel_uncore_forcewake_get(). This variant places the onus
494 * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
496 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
497 enum forcewake_domains fw_domains)
499 assert_spin_locked(&dev_priv->uncore.lock);
501 if (!dev_priv->uncore.funcs.force_wake_get)
504 __intel_uncore_forcewake_get(dev_priv, fw_domains);
507 static void __intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
508 enum forcewake_domains fw_domains)
510 struct intel_uncore_forcewake_domain *domain;
512 if (!dev_priv->uncore.funcs.force_wake_put)
515 fw_domains &= dev_priv->uncore.fw_domains;
517 for_each_fw_domain_masked(domain, fw_domains, dev_priv) {
518 if (WARN_ON(domain->wake_count == 0))
521 if (--domain->wake_count)
524 fw_domain_arm_timer(domain);
529 * intel_uncore_forcewake_put - release a forcewake domain reference
530 * @dev_priv: i915 device instance
531 * @fw_domains: forcewake domains to put references
533 * This function drops the device-level forcewakes for specified
534 * domains obtained by intel_uncore_forcewake_get().
536 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
537 enum forcewake_domains fw_domains)
539 unsigned long irqflags;
541 if (!dev_priv->uncore.funcs.force_wake_put)
544 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
545 __intel_uncore_forcewake_put(dev_priv, fw_domains);
546 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
550 * intel_uncore_forcewake_put__locked - grab forcewake domain references
551 * @dev_priv: i915 device instance
552 * @fw_domains: forcewake domains to get reference on
554 * See intel_uncore_forcewake_put(). This variant places the onus
555 * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
557 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
558 enum forcewake_domains fw_domains)
560 assert_spin_locked(&dev_priv->uncore.lock);
562 if (!dev_priv->uncore.funcs.force_wake_put)
565 __intel_uncore_forcewake_put(dev_priv, fw_domains);
568 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv)
570 struct intel_uncore_forcewake_domain *domain;
572 if (!dev_priv->uncore.funcs.force_wake_get)
575 for_each_fw_domain(domain, dev_priv)
576 WARN_ON(domain->wake_count);
579 /* We give fast paths for the really cool registers */
580 #define NEEDS_FORCE_WAKE(reg) ((reg) < 0x40000)
582 #define __gen6_reg_read_fw_domains(offset) \
584 enum forcewake_domains __fwd; \
585 if (NEEDS_FORCE_WAKE(offset)) \
586 __fwd = FORCEWAKE_RENDER; \
592 #define REG_RANGE(reg, start, end) ((reg) >= (start) && (reg) < (end))
594 #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \
595 (REG_RANGE((reg), 0x2000, 0x4000) || \
596 REG_RANGE((reg), 0x5000, 0x8000) || \
597 REG_RANGE((reg), 0xB000, 0x12000) || \
598 REG_RANGE((reg), 0x2E000, 0x30000))
600 #define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg) \
601 (REG_RANGE((reg), 0x12000, 0x14000) || \
602 REG_RANGE((reg), 0x22000, 0x24000) || \
603 REG_RANGE((reg), 0x30000, 0x40000))
605 #define __vlv_reg_read_fw_domains(offset) \
607 enum forcewake_domains __fwd = 0; \
608 if (!NEEDS_FORCE_WAKE(offset)) \
610 else if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(offset)) \
611 __fwd = FORCEWAKE_RENDER; \
612 else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(offset)) \
613 __fwd = FORCEWAKE_MEDIA; \
617 static const i915_reg_t gen8_shadowed_regs[] = {
620 RING_TAIL(RENDER_RING_BASE),
621 RING_TAIL(GEN6_BSD_RING_BASE),
622 RING_TAIL(VEBOX_RING_BASE),
623 RING_TAIL(BLT_RING_BASE),
624 /* TODO: Other registers are not yet used */
627 static bool is_gen8_shadowed(u32 offset)
630 for (i = 0; i < ARRAY_SIZE(gen8_shadowed_regs); i++)
631 if (offset == gen8_shadowed_regs[i].reg)
637 #define __gen8_reg_write_fw_domains(offset) \
639 enum forcewake_domains __fwd; \
640 if (NEEDS_FORCE_WAKE(offset) && !is_gen8_shadowed(offset)) \
641 __fwd = FORCEWAKE_RENDER; \
647 #define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \
648 (REG_RANGE((reg), 0x2000, 0x4000) || \
649 REG_RANGE((reg), 0x5200, 0x8000) || \
650 REG_RANGE((reg), 0x8300, 0x8500) || \
651 REG_RANGE((reg), 0xB000, 0xB480) || \
652 REG_RANGE((reg), 0xE000, 0xE800))
654 #define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg) \
655 (REG_RANGE((reg), 0x8800, 0x8900) || \
656 REG_RANGE((reg), 0xD000, 0xD800) || \
657 REG_RANGE((reg), 0x12000, 0x14000) || \
658 REG_RANGE((reg), 0x1A000, 0x1C000) || \
659 REG_RANGE((reg), 0x1E800, 0x1EA00) || \
660 REG_RANGE((reg), 0x30000, 0x38000))
662 #define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg) \
663 (REG_RANGE((reg), 0x4000, 0x5000) || \
664 REG_RANGE((reg), 0x8000, 0x8300) || \
665 REG_RANGE((reg), 0x8500, 0x8600) || \
666 REG_RANGE((reg), 0x9000, 0xB000) || \
667 REG_RANGE((reg), 0xF000, 0x10000))
669 #define __chv_reg_read_fw_domains(offset) \
671 enum forcewake_domains __fwd = 0; \
672 if (!NEEDS_FORCE_WAKE(offset)) \
674 else if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(offset)) \
675 __fwd = FORCEWAKE_RENDER; \
676 else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(offset)) \
677 __fwd = FORCEWAKE_MEDIA; \
678 else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(offset)) \
679 __fwd = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
683 #define __chv_reg_write_fw_domains(offset) \
685 enum forcewake_domains __fwd = 0; \
686 if (!NEEDS_FORCE_WAKE(offset) || is_gen8_shadowed(offset)) \
688 else if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(offset)) \
689 __fwd = FORCEWAKE_RENDER; \
690 else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(offset)) \
691 __fwd = FORCEWAKE_MEDIA; \
692 else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(offset)) \
693 __fwd = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
697 #define FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) \
698 REG_RANGE((reg), 0xB00, 0x2000)
700 #define FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) \
701 (REG_RANGE((reg), 0x2000, 0x2700) || \
702 REG_RANGE((reg), 0x3000, 0x4000) || \
703 REG_RANGE((reg), 0x5200, 0x8000) || \
704 REG_RANGE((reg), 0x8140, 0x8160) || \
705 REG_RANGE((reg), 0x8300, 0x8500) || \
706 REG_RANGE((reg), 0x8C00, 0x8D00) || \
707 REG_RANGE((reg), 0xB000, 0xB480) || \
708 REG_RANGE((reg), 0xE000, 0xE900) || \
709 REG_RANGE((reg), 0x24400, 0x24800))
711 #define FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) \
712 (REG_RANGE((reg), 0x8130, 0x8140) || \
713 REG_RANGE((reg), 0x8800, 0x8A00) || \
714 REG_RANGE((reg), 0xD000, 0xD800) || \
715 REG_RANGE((reg), 0x12000, 0x14000) || \
716 REG_RANGE((reg), 0x1A000, 0x1EA00) || \
717 REG_RANGE((reg), 0x30000, 0x40000))
719 #define FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg) \
720 REG_RANGE((reg), 0x9400, 0x9800)
722 #define FORCEWAKE_GEN9_BLITTER_RANGE_OFFSET(reg) \
723 ((reg) < 0x40000 && \
724 !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) && \
725 !FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) && \
726 !FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) && \
727 !FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg))
729 #define SKL_NEEDS_FORCE_WAKE(reg) \
730 ((reg) < 0x40000 && !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg))
732 #define __gen9_reg_read_fw_domains(offset) \
734 enum forcewake_domains __fwd; \
735 if (!SKL_NEEDS_FORCE_WAKE(offset)) \
737 else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(offset)) \
738 __fwd = FORCEWAKE_RENDER; \
739 else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(offset)) \
740 __fwd = FORCEWAKE_MEDIA; \
741 else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(offset)) \
742 __fwd = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
744 __fwd = FORCEWAKE_BLITTER; \
748 static const i915_reg_t gen9_shadowed_regs[] = {
749 RING_TAIL(RENDER_RING_BASE),
750 RING_TAIL(GEN6_BSD_RING_BASE),
751 RING_TAIL(VEBOX_RING_BASE),
752 RING_TAIL(BLT_RING_BASE),
755 /* TODO: Other registers are not yet used */
758 static bool is_gen9_shadowed(u32 offset)
761 for (i = 0; i < ARRAY_SIZE(gen9_shadowed_regs); i++)
762 if (offset == gen9_shadowed_regs[i].reg)
768 #define __gen9_reg_write_fw_domains(offset) \
770 enum forcewake_domains __fwd; \
771 if (!SKL_NEEDS_FORCE_WAKE(offset) || is_gen9_shadowed(offset)) \
773 else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(offset)) \
774 __fwd = FORCEWAKE_RENDER; \
775 else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(offset)) \
776 __fwd = FORCEWAKE_MEDIA; \
777 else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(offset)) \
778 __fwd = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
780 __fwd = FORCEWAKE_BLITTER; \
785 ilk_dummy_write(struct drm_i915_private *dev_priv)
787 /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
788 * the chip from rc6 before touching it for real. MI_MODE is masked,
789 * hence harmless to write 0 into. */
790 __raw_i915_write32(dev_priv, MI_MODE, 0);
794 __unclaimed_reg_debug(struct drm_i915_private *dev_priv,
795 const i915_reg_t reg,
799 if (WARN(check_for_unclaimed_mmio(dev_priv) && !before,
800 "Unclaimed %s register 0x%x\n",
801 read ? "read from" : "write to",
802 i915_mmio_reg_offset(reg)))
803 i915.mmio_debug--; /* Only report the first N failures */
807 unclaimed_reg_debug(struct drm_i915_private *dev_priv,
808 const i915_reg_t reg,
812 if (likely(!i915.mmio_debug))
815 __unclaimed_reg_debug(dev_priv, reg, read, before);
818 #define GEN2_READ_HEADER(x) \
820 assert_rpm_wakelock_held(dev_priv);
822 #define GEN2_READ_FOOTER \
823 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
826 #define __gen2_read(x) \
828 gen2_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
829 GEN2_READ_HEADER(x); \
830 val = __raw_i915_read##x(dev_priv, reg); \
834 #define __gen5_read(x) \
836 gen5_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
837 GEN2_READ_HEADER(x); \
838 ilk_dummy_write(dev_priv); \
839 val = __raw_i915_read##x(dev_priv, reg); \
855 #undef GEN2_READ_FOOTER
856 #undef GEN2_READ_HEADER
858 #define GEN6_READ_HEADER(x) \
859 u32 offset = i915_mmio_reg_offset(reg); \
860 unsigned long irqflags; \
862 assert_rpm_wakelock_held(dev_priv); \
863 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \
864 unclaimed_reg_debug(dev_priv, reg, true, true)
866 #define GEN6_READ_FOOTER \
867 unclaimed_reg_debug(dev_priv, reg, true, false); \
868 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
869 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
872 static inline void __force_wake_auto(struct drm_i915_private *dev_priv,
873 enum forcewake_domains fw_domains)
875 struct intel_uncore_forcewake_domain *domain;
877 if (WARN_ON(!fw_domains))
880 /* Ideally GCC would be constant-fold and eliminate this loop */
881 for_each_fw_domain_masked(domain, fw_domains, dev_priv) {
882 if (domain->wake_count) {
883 fw_domains &= ~domain->mask;
887 fw_domain_arm_timer(domain);
891 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
894 #define __gen6_read(x) \
896 gen6_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
897 enum forcewake_domains fw_engine; \
898 GEN6_READ_HEADER(x); \
899 fw_engine = __gen6_reg_read_fw_domains(offset); \
901 __force_wake_auto(dev_priv, fw_engine); \
902 val = __raw_i915_read##x(dev_priv, reg); \
906 #define __vlv_read(x) \
908 vlv_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
909 enum forcewake_domains fw_engine; \
910 GEN6_READ_HEADER(x); \
911 fw_engine = __vlv_reg_read_fw_domains(offset); \
913 __force_wake_auto(dev_priv, fw_engine); \
914 val = __raw_i915_read##x(dev_priv, reg); \
918 #define __chv_read(x) \
920 chv_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
921 enum forcewake_domains fw_engine; \
922 GEN6_READ_HEADER(x); \
923 fw_engine = __chv_reg_read_fw_domains(offset); \
925 __force_wake_auto(dev_priv, fw_engine); \
926 val = __raw_i915_read##x(dev_priv, reg); \
930 #define __gen9_read(x) \
932 gen9_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
933 enum forcewake_domains fw_engine; \
934 GEN6_READ_HEADER(x); \
935 fw_engine = __gen9_reg_read_fw_domains(offset); \
937 __force_wake_auto(dev_priv, fw_engine); \
938 val = __raw_i915_read##x(dev_priv, reg); \
963 #undef GEN6_READ_FOOTER
964 #undef GEN6_READ_HEADER
966 #define VGPU_READ_HEADER(x) \
967 unsigned long irqflags; \
969 assert_rpm_device_not_suspended(dev_priv); \
970 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
972 #define VGPU_READ_FOOTER \
973 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
974 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
977 #define __vgpu_read(x) \
979 vgpu_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
980 VGPU_READ_HEADER(x); \
981 val = __raw_i915_read##x(dev_priv, reg); \
991 #undef VGPU_READ_FOOTER
992 #undef VGPU_READ_HEADER
994 #define GEN2_WRITE_HEADER \
995 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
996 assert_rpm_wakelock_held(dev_priv); \
998 #define GEN2_WRITE_FOOTER
1000 #define __gen2_write(x) \
1002 gen2_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1003 GEN2_WRITE_HEADER; \
1004 __raw_i915_write##x(dev_priv, reg, val); \
1005 GEN2_WRITE_FOOTER; \
1008 #define __gen5_write(x) \
1010 gen5_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1011 GEN2_WRITE_HEADER; \
1012 ilk_dummy_write(dev_priv); \
1013 __raw_i915_write##x(dev_priv, reg, val); \
1014 GEN2_WRITE_FOOTER; \
1027 #undef GEN2_WRITE_FOOTER
1028 #undef GEN2_WRITE_HEADER
1030 #define GEN6_WRITE_HEADER \
1031 u32 offset = i915_mmio_reg_offset(reg); \
1032 unsigned long irqflags; \
1033 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1034 assert_rpm_wakelock_held(dev_priv); \
1035 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \
1036 unclaimed_reg_debug(dev_priv, reg, false, true)
1038 #define GEN6_WRITE_FOOTER \
1039 unclaimed_reg_debug(dev_priv, reg, false, false); \
1040 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
1042 #define __gen6_write(x) \
1044 gen6_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1045 u32 __fifo_ret = 0; \
1046 GEN6_WRITE_HEADER; \
1047 if (NEEDS_FORCE_WAKE(offset)) { \
1048 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1050 __raw_i915_write##x(dev_priv, reg, val); \
1051 if (unlikely(__fifo_ret)) { \
1052 gen6_gt_check_fifodbg(dev_priv); \
1054 GEN6_WRITE_FOOTER; \
1057 #define __hsw_write(x) \
1059 hsw_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1060 u32 __fifo_ret = 0; \
1061 GEN6_WRITE_HEADER; \
1062 if (NEEDS_FORCE_WAKE(offset)) { \
1063 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1065 __raw_i915_write##x(dev_priv, reg, val); \
1066 if (unlikely(__fifo_ret)) { \
1067 gen6_gt_check_fifodbg(dev_priv); \
1069 GEN6_WRITE_FOOTER; \
1072 #define __gen8_write(x) \
1074 gen8_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1075 enum forcewake_domains fw_engine; \
1076 GEN6_WRITE_HEADER; \
1077 fw_engine = __gen8_reg_write_fw_domains(offset); \
1079 __force_wake_auto(dev_priv, fw_engine); \
1080 __raw_i915_write##x(dev_priv, reg, val); \
1081 GEN6_WRITE_FOOTER; \
1084 #define __chv_write(x) \
1086 chv_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1087 enum forcewake_domains fw_engine; \
1088 GEN6_WRITE_HEADER; \
1089 fw_engine = __chv_reg_write_fw_domains(offset); \
1091 __force_wake_auto(dev_priv, fw_engine); \
1092 __raw_i915_write##x(dev_priv, reg, val); \
1093 GEN6_WRITE_FOOTER; \
1096 #define __gen9_write(x) \
1098 gen9_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, \
1100 enum forcewake_domains fw_engine; \
1101 GEN6_WRITE_HEADER; \
1102 fw_engine = __gen9_reg_write_fw_domains(offset); \
1104 __force_wake_auto(dev_priv, fw_engine); \
1105 __raw_i915_write##x(dev_priv, reg, val); \
1106 GEN6_WRITE_FOOTER; \
1130 #undef GEN6_WRITE_FOOTER
1131 #undef GEN6_WRITE_HEADER
1133 #define VGPU_WRITE_HEADER \
1134 unsigned long irqflags; \
1135 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1136 assert_rpm_device_not_suspended(dev_priv); \
1137 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
1139 #define VGPU_WRITE_FOOTER \
1140 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
1142 #define __vgpu_write(x) \
1143 static void vgpu_write##x(struct drm_i915_private *dev_priv, \
1144 i915_reg_t reg, u##x val, bool trace) { \
1145 VGPU_WRITE_HEADER; \
1146 __raw_i915_write##x(dev_priv, reg, val); \
1147 VGPU_WRITE_FOOTER; \
1155 #undef VGPU_WRITE_FOOTER
1156 #undef VGPU_WRITE_HEADER
1158 #define ASSIGN_WRITE_MMIO_VFUNCS(x) \
1160 dev_priv->uncore.funcs.mmio_writeb = x##_write8; \
1161 dev_priv->uncore.funcs.mmio_writew = x##_write16; \
1162 dev_priv->uncore.funcs.mmio_writel = x##_write32; \
1165 #define ASSIGN_READ_MMIO_VFUNCS(x) \
1167 dev_priv->uncore.funcs.mmio_readb = x##_read8; \
1168 dev_priv->uncore.funcs.mmio_readw = x##_read16; \
1169 dev_priv->uncore.funcs.mmio_readl = x##_read32; \
1170 dev_priv->uncore.funcs.mmio_readq = x##_read64; \
1174 static void fw_domain_init(struct drm_i915_private *dev_priv,
1175 enum forcewake_domain_id domain_id,
1179 struct intel_uncore_forcewake_domain *d;
1181 if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT))
1184 d = &dev_priv->uncore.fw_domain[domain_id];
1186 WARN_ON(d->wake_count);
1189 d->reg_set = reg_set;
1190 d->reg_ack = reg_ack;
1192 if (IS_GEN6(dev_priv)) {
1194 d->val_set = FORCEWAKE_KERNEL;
1197 /* WaRsClearFWBitsAtReset:bdw,skl */
1198 d->val_reset = _MASKED_BIT_DISABLE(0xffff);
1199 d->val_set = _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL);
1200 d->val_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL);
1203 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1204 d->reg_post = FORCEWAKE_ACK_VLV;
1205 else if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv) || IS_GEN8(dev_priv))
1206 d->reg_post = ECOBUS;
1211 BUILD_BUG_ON(FORCEWAKE_RENDER != (1 << FW_DOMAIN_ID_RENDER));
1212 BUILD_BUG_ON(FORCEWAKE_BLITTER != (1 << FW_DOMAIN_ID_BLITTER));
1213 BUILD_BUG_ON(FORCEWAKE_MEDIA != (1 << FW_DOMAIN_ID_MEDIA));
1215 d->mask = 1 << domain_id;
1217 hrtimer_init(&d->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1218 d->timer.function = intel_uncore_fw_release_timer;
1220 dev_priv->uncore.fw_domains |= (1 << domain_id);
1225 static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
1227 if (INTEL_INFO(dev_priv)->gen <= 5)
1230 if (IS_GEN9(dev_priv)) {
1231 dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
1232 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1233 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1234 FORCEWAKE_RENDER_GEN9,
1235 FORCEWAKE_ACK_RENDER_GEN9);
1236 fw_domain_init(dev_priv, FW_DOMAIN_ID_BLITTER,
1237 FORCEWAKE_BLITTER_GEN9,
1238 FORCEWAKE_ACK_BLITTER_GEN9);
1239 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
1240 FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
1241 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1242 dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
1243 if (!IS_CHERRYVIEW(dev_priv))
1244 dev_priv->uncore.funcs.force_wake_put =
1245 fw_domains_put_with_fifo;
1247 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1248 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1249 FORCEWAKE_VLV, FORCEWAKE_ACK_VLV);
1250 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
1251 FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV);
1252 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1253 dev_priv->uncore.funcs.force_wake_get =
1254 fw_domains_get_with_thread_status;
1255 if (IS_HASWELL(dev_priv))
1256 dev_priv->uncore.funcs.force_wake_put =
1257 fw_domains_put_with_fifo;
1259 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1260 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1261 FORCEWAKE_MT, FORCEWAKE_ACK_HSW);
1262 } else if (IS_IVYBRIDGE(dev_priv)) {
1265 /* IVB configs may use multi-threaded forcewake */
1267 /* A small trick here - if the bios hasn't configured
1268 * MT forcewake, and if the device is in RC6, then
1269 * force_wake_mt_get will not wake the device and the
1270 * ECOBUS read will return zero. Which will be
1271 * (correctly) interpreted by the test below as MT
1272 * forcewake being disabled.
1274 dev_priv->uncore.funcs.force_wake_get =
1275 fw_domains_get_with_thread_status;
1276 dev_priv->uncore.funcs.force_wake_put =
1277 fw_domains_put_with_fifo;
1279 /* We need to init first for ECOBUS access and then
1280 * determine later if we want to reinit, in case of MT access is
1281 * not working. In this stage we don't know which flavour this
1282 * ivb is, so it is better to reset also the gen6 fw registers
1283 * before the ecobus check.
1286 __raw_i915_write32(dev_priv, FORCEWAKE, 0);
1287 __raw_posting_read(dev_priv, ECOBUS);
1289 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1290 FORCEWAKE_MT, FORCEWAKE_MT_ACK);
1292 spin_lock_irq(&dev_priv->uncore.lock);
1293 fw_domains_get_with_thread_status(dev_priv, FORCEWAKE_ALL);
1294 ecobus = __raw_i915_read32(dev_priv, ECOBUS);
1295 fw_domains_put_with_fifo(dev_priv, FORCEWAKE_ALL);
1296 spin_unlock_irq(&dev_priv->uncore.lock);
1298 if (!(ecobus & FORCEWAKE_MT_ENABLE)) {
1299 DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
1300 DRM_INFO("when using vblank-synced partial screen updates.\n");
1301 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1302 FORCEWAKE, FORCEWAKE_ACK);
1304 } else if (IS_GEN6(dev_priv)) {
1305 dev_priv->uncore.funcs.force_wake_get =
1306 fw_domains_get_with_thread_status;
1307 dev_priv->uncore.funcs.force_wake_put =
1308 fw_domains_put_with_fifo;
1309 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1310 FORCEWAKE, FORCEWAKE_ACK);
1313 /* All future platforms are expected to require complex power gating */
1314 WARN_ON(dev_priv->uncore.fw_domains == 0);
1317 void intel_uncore_init(struct drm_i915_private *dev_priv)
1319 i915_check_vgpu(dev_priv);
1321 intel_uncore_edram_detect(dev_priv);
1322 intel_uncore_fw_domains_init(dev_priv);
1323 __intel_uncore_early_sanitize(dev_priv, false);
1325 dev_priv->uncore.unclaimed_mmio_check = 1;
1327 switch (INTEL_INFO(dev_priv)->gen) {
1330 ASSIGN_WRITE_MMIO_VFUNCS(gen9);
1331 ASSIGN_READ_MMIO_VFUNCS(gen9);
1334 if (IS_CHERRYVIEW(dev_priv)) {
1335 ASSIGN_WRITE_MMIO_VFUNCS(chv);
1336 ASSIGN_READ_MMIO_VFUNCS(chv);
1339 ASSIGN_WRITE_MMIO_VFUNCS(gen8);
1340 ASSIGN_READ_MMIO_VFUNCS(gen6);
1345 if (IS_HASWELL(dev_priv)) {
1346 ASSIGN_WRITE_MMIO_VFUNCS(hsw);
1348 ASSIGN_WRITE_MMIO_VFUNCS(gen6);
1351 if (IS_VALLEYVIEW(dev_priv)) {
1352 ASSIGN_READ_MMIO_VFUNCS(vlv);
1354 ASSIGN_READ_MMIO_VFUNCS(gen6);
1358 ASSIGN_WRITE_MMIO_VFUNCS(gen5);
1359 ASSIGN_READ_MMIO_VFUNCS(gen5);
1364 ASSIGN_WRITE_MMIO_VFUNCS(gen2);
1365 ASSIGN_READ_MMIO_VFUNCS(gen2);
1369 if (intel_vgpu_active(dev_priv)) {
1370 ASSIGN_WRITE_MMIO_VFUNCS(vgpu);
1371 ASSIGN_READ_MMIO_VFUNCS(vgpu);
1374 i915_check_and_clear_faults(dev_priv);
1376 #undef ASSIGN_WRITE_MMIO_VFUNCS
1377 #undef ASSIGN_READ_MMIO_VFUNCS
1379 void intel_uncore_fini(struct drm_i915_private *dev_priv)
1381 /* Paranoia: make sure we have disabled everything before we exit. */
1382 intel_uncore_sanitize(dev_priv);
1383 intel_uncore_forcewake_reset(dev_priv, false);
1386 #define GEN_RANGE(l, h) GENMASK((h) - 1, (l) - 1)
1388 static const struct register_whitelist {
1389 i915_reg_t offset_ldw, offset_udw;
1391 /* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
1392 uint32_t gen_bitmask;
1394 { .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
1395 .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
1396 .size = 8, .gen_bitmask = GEN_RANGE(4, 9) },
1399 int i915_reg_read_ioctl(struct drm_device *dev,
1400 void *data, struct drm_file *file)
1402 struct drm_i915_private *dev_priv = to_i915(dev);
1403 struct drm_i915_reg_read *reg = data;
1404 struct register_whitelist const *entry = whitelist;
1406 i915_reg_t offset_ldw, offset_udw;
1409 for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
1410 if (i915_mmio_reg_offset(entry->offset_ldw) == (reg->offset & -entry->size) &&
1411 (INTEL_INFO(dev)->gen_mask & entry->gen_bitmask))
1415 if (i == ARRAY_SIZE(whitelist))
1418 /* We use the low bits to encode extra flags as the register should
1419 * be naturally aligned (and those that are not so aligned merely
1420 * limit the available flags for that register).
1422 offset_ldw = entry->offset_ldw;
1423 offset_udw = entry->offset_udw;
1425 size |= reg->offset ^ i915_mmio_reg_offset(offset_ldw);
1427 intel_runtime_pm_get(dev_priv);
1431 reg->val = I915_READ64_2x32(offset_ldw, offset_udw);
1434 reg->val = I915_READ64(offset_ldw);
1437 reg->val = I915_READ(offset_ldw);
1440 reg->val = I915_READ16(offset_ldw);
1443 reg->val = I915_READ8(offset_ldw);
1451 intel_runtime_pm_put(dev_priv);
1455 static int i915_reset_complete(struct pci_dev *pdev)
1458 pci_read_config_byte(pdev, I915_GDRST, &gdrst);
1459 return (gdrst & GRDOM_RESET_STATUS) == 0;
1462 static int i915_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask)
1464 struct pci_dev *pdev = dev_priv->drm.pdev;
1466 /* assert reset for at least 20 usec */
1467 pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1469 pci_write_config_byte(pdev, I915_GDRST, 0);
1471 return wait_for(i915_reset_complete(pdev), 500);
1474 static int g4x_reset_complete(struct pci_dev *pdev)
1477 pci_read_config_byte(pdev, I915_GDRST, &gdrst);
1478 return (gdrst & GRDOM_RESET_ENABLE) == 0;
1481 static int g33_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask)
1483 struct pci_dev *pdev = dev_priv->drm.pdev;
1484 pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1485 return wait_for(g4x_reset_complete(pdev), 500);
1488 static int g4x_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask)
1490 struct pci_dev *pdev = dev_priv->drm.pdev;
1493 pci_write_config_byte(pdev, I915_GDRST,
1494 GRDOM_RENDER | GRDOM_RESET_ENABLE);
1495 ret = wait_for(g4x_reset_complete(pdev), 500);
1499 /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1500 I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE);
1501 POSTING_READ(VDECCLK_GATE_D);
1503 pci_write_config_byte(pdev, I915_GDRST,
1504 GRDOM_MEDIA | GRDOM_RESET_ENABLE);
1505 ret = wait_for(g4x_reset_complete(pdev), 500);
1509 /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1510 I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE);
1511 POSTING_READ(VDECCLK_GATE_D);
1513 pci_write_config_byte(pdev, I915_GDRST, 0);
1518 static int ironlake_do_reset(struct drm_i915_private *dev_priv,
1519 unsigned engine_mask)
1523 I915_WRITE(ILK_GDSR,
1524 ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
1525 ret = intel_wait_for_register(dev_priv,
1526 ILK_GDSR, ILK_GRDOM_RESET_ENABLE, 0,
1531 I915_WRITE(ILK_GDSR,
1532 ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
1533 ret = intel_wait_for_register(dev_priv,
1534 ILK_GDSR, ILK_GRDOM_RESET_ENABLE, 0,
1539 I915_WRITE(ILK_GDSR, 0);
1544 /* Reset the hardware domains (GENX_GRDOM_*) specified by mask */
1545 static int gen6_hw_domain_reset(struct drm_i915_private *dev_priv,
1548 /* GEN6_GDRST is not in the gt power well, no need to check
1549 * for fifo space for the write or forcewake the chip for
1552 __raw_i915_write32(dev_priv, GEN6_GDRST, hw_domain_mask);
1554 /* Spin waiting for the device to ack the reset requests */
1555 return intel_wait_for_register_fw(dev_priv,
1556 GEN6_GDRST, hw_domain_mask, 0,
1561 * gen6_reset_engines - reset individual engines
1562 * @dev_priv: i915 device
1563 * @engine_mask: mask of intel_ring_flag() engines or ALL_ENGINES for full reset
1565 * This function will reset the individual engines that are set in engine_mask.
1566 * If you provide ALL_ENGINES as mask, full global domain reset will be issued.
1568 * Note: It is responsibility of the caller to handle the difference between
1569 * asking full domain reset versus reset for all available individual engines.
1571 * Returns 0 on success, nonzero on error.
1573 static int gen6_reset_engines(struct drm_i915_private *dev_priv,
1574 unsigned engine_mask)
1576 struct intel_engine_cs *engine;
1577 const u32 hw_engine_mask[I915_NUM_ENGINES] = {
1578 [RCS] = GEN6_GRDOM_RENDER,
1579 [BCS] = GEN6_GRDOM_BLT,
1580 [VCS] = GEN6_GRDOM_MEDIA,
1581 [VCS2] = GEN8_GRDOM_MEDIA2,
1582 [VECS] = GEN6_GRDOM_VECS,
1587 if (engine_mask == ALL_ENGINES) {
1588 hw_mask = GEN6_GRDOM_FULL;
1593 for_each_engine_masked(engine, dev_priv, engine_mask, tmp)
1594 hw_mask |= hw_engine_mask[engine->id];
1597 ret = gen6_hw_domain_reset(dev_priv, hw_mask);
1599 intel_uncore_forcewake_reset(dev_priv, true);
1605 * intel_wait_for_register_fw - wait until register matches expected state
1606 * @dev_priv: the i915 device
1607 * @reg: the register to read
1608 * @mask: mask to apply to register value
1609 * @value: expected value
1610 * @timeout_ms: timeout in millisecond
1612 * This routine waits until the target register @reg contains the expected
1613 * @value after applying the @mask, i.e. it waits until ::
1615 * (I915_READ_FW(reg) & mask) == value
1617 * Otherwise, the wait will timeout after @timeout_ms milliseconds.
1619 * Note that this routine assumes the caller holds forcewake asserted, it is
1620 * not suitable for very long waits. See intel_wait_for_register() if you
1621 * wish to wait without holding forcewake for the duration (i.e. you expect
1622 * the wait to be slow).
1624 * Returns 0 if the register matches the desired condition, or -ETIMEOUT.
1626 int intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
1630 const unsigned long timeout_ms)
1632 #define done ((I915_READ_FW(reg) & mask) == value)
1633 int ret = wait_for_us(done, 2);
1635 ret = wait_for(done, timeout_ms);
1641 * intel_wait_for_register - wait until register matches expected state
1642 * @dev_priv: the i915 device
1643 * @reg: the register to read
1644 * @mask: mask to apply to register value
1645 * @value: expected value
1646 * @timeout_ms: timeout in millisecond
1648 * This routine waits until the target register @reg contains the expected
1649 * @value after applying the @mask, i.e. it waits until ::
1651 * (I915_READ(reg) & mask) == value
1653 * Otherwise, the wait will timeout after @timeout_ms milliseconds.
1655 * Returns 0 if the register matches the desired condition, or -ETIMEOUT.
1657 int intel_wait_for_register(struct drm_i915_private *dev_priv,
1661 const unsigned long timeout_ms)
1665 intel_uncore_forcewake_for_reg(dev_priv, reg, FW_REG_READ);
1668 intel_uncore_forcewake_get(dev_priv, fw);
1669 ret = wait_for_us((I915_READ_FW(reg) & mask) == value, 2);
1670 intel_uncore_forcewake_put(dev_priv, fw);
1672 ret = wait_for((I915_READ_NOTRACE(reg) & mask) == value,
1678 static int gen8_request_engine_reset(struct intel_engine_cs *engine)
1680 struct drm_i915_private *dev_priv = engine->i915;
1683 I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base),
1684 _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET));
1686 ret = intel_wait_for_register_fw(dev_priv,
1687 RING_RESET_CTL(engine->mmio_base),
1688 RESET_CTL_READY_TO_RESET,
1689 RESET_CTL_READY_TO_RESET,
1692 DRM_ERROR("%s: reset request timeout\n", engine->name);
1697 static void gen8_unrequest_engine_reset(struct intel_engine_cs *engine)
1699 struct drm_i915_private *dev_priv = engine->i915;
1701 I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base),
1702 _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET));
1705 static int gen8_reset_engines(struct drm_i915_private *dev_priv,
1706 unsigned engine_mask)
1708 struct intel_engine_cs *engine;
1711 for_each_engine_masked(engine, dev_priv, engine_mask, tmp)
1712 if (gen8_request_engine_reset(engine))
1715 return gen6_reset_engines(dev_priv, engine_mask);
1718 for_each_engine_masked(engine, dev_priv, engine_mask, tmp)
1719 gen8_unrequest_engine_reset(engine);
1724 typedef int (*reset_func)(struct drm_i915_private *, unsigned engine_mask);
1726 static reset_func intel_get_gpu_reset(struct drm_i915_private *dev_priv)
1731 if (INTEL_INFO(dev_priv)->gen >= 8)
1732 return gen8_reset_engines;
1733 else if (INTEL_INFO(dev_priv)->gen >= 6)
1734 return gen6_reset_engines;
1735 else if (IS_GEN5(dev_priv))
1736 return ironlake_do_reset;
1737 else if (IS_G4X(dev_priv))
1738 return g4x_do_reset;
1739 else if (IS_G33(dev_priv))
1740 return g33_do_reset;
1741 else if (INTEL_INFO(dev_priv)->gen >= 3)
1742 return i915_do_reset;
1747 int intel_gpu_reset(struct drm_i915_private *dev_priv, unsigned engine_mask)
1752 reset = intel_get_gpu_reset(dev_priv);
1756 /* If the power well sleeps during the reset, the reset
1757 * request may be dropped and never completes (causing -EIO).
1759 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1760 ret = reset(dev_priv, engine_mask);
1761 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1766 bool intel_has_gpu_reset(struct drm_i915_private *dev_priv)
1768 return intel_get_gpu_reset(dev_priv) != NULL;
1771 int intel_guc_reset(struct drm_i915_private *dev_priv)
1774 unsigned long irqflags;
1776 if (!HAS_GUC(dev_priv))
1779 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1780 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1782 ret = gen6_hw_domain_reset(dev_priv, GEN9_GRDOM_GUC);
1784 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1785 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1790 bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv)
1792 return check_for_unclaimed_mmio(dev_priv);
1796 intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv)
1798 if (unlikely(i915.mmio_debug ||
1799 dev_priv->uncore.unclaimed_mmio_check <= 0))
1802 if (unlikely(intel_uncore_unclaimed_mmio(dev_priv))) {
1803 DRM_DEBUG("Unclaimed register detected, "
1804 "enabling oneshot unclaimed register reporting. "
1805 "Please use i915.mmio_debug=N for more information.\n");
1807 dev_priv->uncore.unclaimed_mmio_check--;
1814 static enum forcewake_domains
1815 intel_uncore_forcewake_for_read(struct drm_i915_private *dev_priv,
1818 enum forcewake_domains fw_domains;
1820 if (intel_vgpu_active(dev_priv))
1823 switch (INTEL_GEN(dev_priv)) {
1825 fw_domains = __gen9_reg_read_fw_domains(i915_mmio_reg_offset(reg));
1828 if (IS_CHERRYVIEW(dev_priv))
1829 fw_domains = __chv_reg_read_fw_domains(i915_mmio_reg_offset(reg));
1831 fw_domains = __gen6_reg_read_fw_domains(i915_mmio_reg_offset(reg));
1835 if (IS_VALLEYVIEW(dev_priv))
1836 fw_domains = __vlv_reg_read_fw_domains(i915_mmio_reg_offset(reg));
1838 fw_domains = __gen6_reg_read_fw_domains(i915_mmio_reg_offset(reg));
1841 MISSING_CASE(INTEL_INFO(dev_priv)->gen);
1842 case 5: /* forcewake was introduced with gen6 */
1849 WARN_ON(fw_domains & ~dev_priv->uncore.fw_domains);
1854 static enum forcewake_domains
1855 intel_uncore_forcewake_for_write(struct drm_i915_private *dev_priv,
1858 enum forcewake_domains fw_domains;
1860 if (intel_vgpu_active(dev_priv))
1863 switch (INTEL_GEN(dev_priv)) {
1865 fw_domains = __gen9_reg_write_fw_domains(i915_mmio_reg_offset(reg));
1868 if (IS_CHERRYVIEW(dev_priv))
1869 fw_domains = __chv_reg_write_fw_domains(i915_mmio_reg_offset(reg));
1871 fw_domains = __gen8_reg_write_fw_domains(i915_mmio_reg_offset(reg));
1875 fw_domains = FORCEWAKE_RENDER;
1878 MISSING_CASE(INTEL_INFO(dev_priv)->gen);
1886 WARN_ON(fw_domains & ~dev_priv->uncore.fw_domains);
1892 * intel_uncore_forcewake_for_reg - which forcewake domains are needed to access
1894 * @dev_priv: pointer to struct drm_i915_private
1895 * @reg: register in question
1896 * @op: operation bitmask of FW_REG_READ and/or FW_REG_WRITE
1898 * Returns a set of forcewake domains required to be taken with for example
1899 * intel_uncore_forcewake_get for the specified register to be accessible in the
1900 * specified mode (read, write or read/write) with raw mmio accessors.
1902 * NOTE: On Gen6 and Gen7 write forcewake domain (FORCEWAKE_RENDER) requires the
1903 * callers to do FIFO management on their own or risk losing writes.
1905 enum forcewake_domains
1906 intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
1907 i915_reg_t reg, unsigned int op)
1909 enum forcewake_domains fw_domains = 0;
1913 if (op & FW_REG_READ)
1914 fw_domains = intel_uncore_forcewake_for_read(dev_priv, reg);
1916 if (op & FW_REG_WRITE)
1917 fw_domains |= intel_uncore_forcewake_for_write(dev_priv, reg);