2 * i.MX drm driver - Television Encoder (TVEv2)
4 * Copyright (C) 2013 Philipp Zabel, Pengutronix
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/clk.h>
17 #include <linux/clk-provider.h>
18 #include <linux/component.h>
19 #include <linux/module.h>
20 #include <linux/i2c.h>
21 #include <linux/regmap.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/spinlock.h>
24 #include <linux/videodev2.h>
26 #include <drm/drm_atomic_helper.h>
27 #include <drm/drm_fb_helper.h>
28 #include <drm/drm_crtc_helper.h>
29 #include <video/imx-ipu-v3.h>
33 #define TVE_COM_CONF_REG 0x00
34 #define TVE_TVDAC0_CONT_REG 0x28
35 #define TVE_TVDAC1_CONT_REG 0x2c
36 #define TVE_TVDAC2_CONT_REG 0x30
37 #define TVE_CD_CONT_REG 0x34
38 #define TVE_INT_CONT_REG 0x64
39 #define TVE_STAT_REG 0x68
40 #define TVE_TST_MODE_REG 0x6c
41 #define TVE_MV_CONT_REG 0xdc
43 /* TVE_COM_CONF_REG */
44 #define TVE_SYNC_CH_2_EN BIT(22)
45 #define TVE_SYNC_CH_1_EN BIT(21)
46 #define TVE_SYNC_CH_0_EN BIT(20)
47 #define TVE_TV_OUT_MODE_MASK (0x7 << 12)
48 #define TVE_TV_OUT_DISABLE (0x0 << 12)
49 #define TVE_TV_OUT_CVBS_0 (0x1 << 12)
50 #define TVE_TV_OUT_CVBS_2 (0x2 << 12)
51 #define TVE_TV_OUT_CVBS_0_2 (0x3 << 12)
52 #define TVE_TV_OUT_SVIDEO_0_1 (0x4 << 12)
53 #define TVE_TV_OUT_SVIDEO_0_1_CVBS2_2 (0x5 << 12)
54 #define TVE_TV_OUT_YPBPR (0x6 << 12)
55 #define TVE_TV_OUT_RGB (0x7 << 12)
56 #define TVE_TV_STAND_MASK (0xf << 8)
57 #define TVE_TV_STAND_HD_1080P30 (0xc << 8)
58 #define TVE_P2I_CONV_EN BIT(7)
59 #define TVE_INP_VIDEO_FORM BIT(6)
60 #define TVE_INP_YCBCR_422 (0x0 << 6)
61 #define TVE_INP_YCBCR_444 (0x1 << 6)
62 #define TVE_DATA_SOURCE_MASK (0x3 << 4)
63 #define TVE_DATA_SOURCE_BUS1 (0x0 << 4)
64 #define TVE_DATA_SOURCE_BUS2 (0x1 << 4)
65 #define TVE_DATA_SOURCE_EXT (0x2 << 4)
66 #define TVE_DATA_SOURCE_TESTGEN (0x3 << 4)
67 #define TVE_IPU_CLK_EN_OFS 3
68 #define TVE_IPU_CLK_EN BIT(3)
69 #define TVE_DAC_SAMP_RATE_OFS 1
70 #define TVE_DAC_SAMP_RATE_WIDTH 2
71 #define TVE_DAC_SAMP_RATE_MASK (0x3 << 1)
72 #define TVE_DAC_FULL_RATE (0x0 << 1)
73 #define TVE_DAC_DIV2_RATE (0x1 << 1)
74 #define TVE_DAC_DIV4_RATE (0x2 << 1)
77 /* TVE_TVDACx_CONT_REG */
78 #define TVE_TVDAC_GAIN_MASK (0x3f << 0)
81 #define TVE_CD_CH_2_SM_EN BIT(22)
82 #define TVE_CD_CH_1_SM_EN BIT(21)
83 #define TVE_CD_CH_0_SM_EN BIT(20)
84 #define TVE_CD_CH_2_LM_EN BIT(18)
85 #define TVE_CD_CH_1_LM_EN BIT(17)
86 #define TVE_CD_CH_0_LM_EN BIT(16)
87 #define TVE_CD_CH_2_REF_LVL BIT(10)
88 #define TVE_CD_CH_1_REF_LVL BIT(9)
89 #define TVE_CD_CH_0_REF_LVL BIT(8)
90 #define TVE_CD_EN BIT(0)
92 /* TVE_INT_CONT_REG */
93 #define TVE_FRAME_END_IEN BIT(13)
94 #define TVE_CD_MON_END_IEN BIT(2)
95 #define TVE_CD_SM_IEN BIT(1)
96 #define TVE_CD_LM_IEN BIT(0)
98 /* TVE_TST_MODE_REG */
99 #define TVE_TVDAC_TEST_MODE_MASK (0x7 << 0)
107 struct drm_connector connector;
108 struct drm_encoder encoder;
110 spinlock_t lock; /* register lock */
116 struct regmap *regmap;
117 struct regulator *dac_reg;
118 struct i2c_adapter *ddc;
120 struct clk *di_sel_clk;
121 struct clk_hw clk_hw_di;
125 static inline struct imx_tve *con_to_tve(struct drm_connector *c)
127 return container_of(c, struct imx_tve, connector);
130 static inline struct imx_tve *enc_to_tve(struct drm_encoder *e)
132 return container_of(e, struct imx_tve, encoder);
135 static void tve_lock(void *__tve)
136 __acquires(&tve->lock)
138 struct imx_tve *tve = __tve;
140 spin_lock(&tve->lock);
143 static void tve_unlock(void *__tve)
144 __releases(&tve->lock)
146 struct imx_tve *tve = __tve;
148 spin_unlock(&tve->lock);
151 static void tve_enable(struct imx_tve *tve)
157 clk_prepare_enable(tve->clk);
158 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
162 /* clear interrupt status register */
163 regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
165 /* cable detection irq disabled in VGA mode, enabled in TVOUT mode */
166 if (tve->mode == TVE_MODE_VGA)
167 regmap_write(tve->regmap, TVE_INT_CONT_REG, 0);
169 regmap_write(tve->regmap, TVE_INT_CONT_REG,
175 static void tve_disable(struct imx_tve *tve)
180 tve->enabled = false;
181 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
183 clk_disable_unprepare(tve->clk);
187 static int tve_setup_tvout(struct imx_tve *tve)
192 static int tve_setup_vga(struct imx_tve *tve)
198 /* set gain to (1 + 10/128) to provide 0.7V peak-to-peak amplitude */
199 ret = regmap_update_bits(tve->regmap, TVE_TVDAC0_CONT_REG,
200 TVE_TVDAC_GAIN_MASK, 0x0a);
204 ret = regmap_update_bits(tve->regmap, TVE_TVDAC1_CONT_REG,
205 TVE_TVDAC_GAIN_MASK, 0x0a);
209 ret = regmap_update_bits(tve->regmap, TVE_TVDAC2_CONT_REG,
210 TVE_TVDAC_GAIN_MASK, 0x0a);
214 /* set configuration register */
215 mask = TVE_DATA_SOURCE_MASK | TVE_INP_VIDEO_FORM;
216 val = TVE_DATA_SOURCE_BUS2 | TVE_INP_YCBCR_444;
217 mask |= TVE_TV_STAND_MASK | TVE_P2I_CONV_EN;
218 val |= TVE_TV_STAND_HD_1080P30 | 0;
219 mask |= TVE_TV_OUT_MODE_MASK | TVE_SYNC_CH_0_EN;
220 val |= TVE_TV_OUT_RGB | TVE_SYNC_CH_0_EN;
221 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, mask, val);
225 /* set test mode (as documented) */
226 return regmap_update_bits(tve->regmap, TVE_TST_MODE_REG,
227 TVE_TVDAC_TEST_MODE_MASK, 1);
230 static int imx_tve_connector_get_modes(struct drm_connector *connector)
232 struct imx_tve *tve = con_to_tve(connector);
239 edid = drm_get_edid(connector, tve->ddc);
241 drm_mode_connector_update_edid_property(connector, edid);
242 ret = drm_add_edid_modes(connector, edid);
249 static int imx_tve_connector_mode_valid(struct drm_connector *connector,
250 struct drm_display_mode *mode)
252 struct imx_tve *tve = con_to_tve(connector);
255 /* pixel clock with 2x oversampling */
256 rate = clk_round_rate(tve->clk, 2000UL * mode->clock) / 2000;
257 if (rate == mode->clock)
260 /* pixel clock without oversampling */
261 rate = clk_round_rate(tve->clk, 1000UL * mode->clock) / 1000;
262 if (rate == mode->clock)
265 dev_warn(tve->dev, "ignoring mode %dx%d\n",
266 mode->hdisplay, mode->vdisplay);
271 static struct drm_encoder *imx_tve_connector_best_encoder(
272 struct drm_connector *connector)
274 struct imx_tve *tve = con_to_tve(connector);
276 return &tve->encoder;
279 static void imx_tve_encoder_mode_set(struct drm_encoder *encoder,
280 struct drm_display_mode *orig_mode,
281 struct drm_display_mode *mode)
283 struct imx_tve *tve = enc_to_tve(encoder);
284 unsigned long rounded_rate;
291 * we should try 4k * mode->clock first,
292 * and enable 4x oversampling for lower resolutions
294 rate = 2000UL * mode->clock;
295 clk_set_rate(tve->clk, rate);
296 rounded_rate = clk_get_rate(tve->clk);
297 if (rounded_rate >= rate)
299 clk_set_rate(tve->di_clk, rounded_rate / div);
301 ret = clk_set_parent(tve->di_sel_clk, tve->di_clk);
303 dev_err(tve->dev, "failed to set di_sel parent to tve_di: %d\n",
307 regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
308 TVE_IPU_CLK_EN, TVE_IPU_CLK_EN);
310 if (tve->mode == TVE_MODE_VGA)
311 ret = tve_setup_vga(tve);
313 ret = tve_setup_tvout(tve);
315 dev_err(tve->dev, "failed to set configuration: %d\n", ret);
318 static void imx_tve_encoder_enable(struct drm_encoder *encoder)
320 struct imx_tve *tve = enc_to_tve(encoder);
325 static void imx_tve_encoder_disable(struct drm_encoder *encoder)
327 struct imx_tve *tve = enc_to_tve(encoder);
332 static int imx_tve_atomic_check(struct drm_encoder *encoder,
333 struct drm_crtc_state *crtc_state,
334 struct drm_connector_state *conn_state)
336 struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);
337 struct imx_tve *tve = enc_to_tve(encoder);
339 imx_crtc_state->bus_format = MEDIA_BUS_FMT_GBR888_1X24;
340 imx_crtc_state->di_hsync_pin = tve->di_hsync_pin;
341 imx_crtc_state->di_vsync_pin = tve->di_vsync_pin;
346 static const struct drm_connector_funcs imx_tve_connector_funcs = {
347 .dpms = drm_atomic_helper_connector_dpms,
348 .fill_modes = drm_helper_probe_single_connector_modes,
349 .destroy = imx_drm_connector_destroy,
350 .reset = drm_atomic_helper_connector_reset,
351 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
352 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
355 static const struct drm_connector_helper_funcs imx_tve_connector_helper_funcs = {
356 .get_modes = imx_tve_connector_get_modes,
357 .best_encoder = imx_tve_connector_best_encoder,
358 .mode_valid = imx_tve_connector_mode_valid,
361 static const struct drm_encoder_funcs imx_tve_encoder_funcs = {
362 .destroy = imx_drm_encoder_destroy,
365 static const struct drm_encoder_helper_funcs imx_tve_encoder_helper_funcs = {
366 .mode_set = imx_tve_encoder_mode_set,
367 .enable = imx_tve_encoder_enable,
368 .disable = imx_tve_encoder_disable,
369 .atomic_check = imx_tve_atomic_check,
372 static irqreturn_t imx_tve_irq_handler(int irq, void *data)
374 struct imx_tve *tve = data;
377 regmap_read(tve->regmap, TVE_STAT_REG, &val);
379 /* clear interrupt status register */
380 regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
385 static unsigned long clk_tve_di_recalc_rate(struct clk_hw *hw,
386 unsigned long parent_rate)
388 struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
392 ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
396 switch (val & TVE_DAC_SAMP_RATE_MASK) {
397 case TVE_DAC_DIV4_RATE:
398 return parent_rate / 4;
399 case TVE_DAC_DIV2_RATE:
400 return parent_rate / 2;
401 case TVE_DAC_FULL_RATE:
409 static long clk_tve_di_round_rate(struct clk_hw *hw, unsigned long rate,
410 unsigned long *prate)
422 static int clk_tve_di_set_rate(struct clk_hw *hw, unsigned long rate,
423 unsigned long parent_rate)
425 struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
430 div = parent_rate / rate;
432 val = TVE_DAC_DIV4_RATE;
434 val = TVE_DAC_DIV2_RATE;
436 val = TVE_DAC_FULL_RATE;
438 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
439 TVE_DAC_SAMP_RATE_MASK, val);
442 dev_err(tve->dev, "failed to set divider: %d\n", ret);
449 static struct clk_ops clk_tve_di_ops = {
450 .round_rate = clk_tve_di_round_rate,
451 .set_rate = clk_tve_di_set_rate,
452 .recalc_rate = clk_tve_di_recalc_rate,
455 static int tve_clk_init(struct imx_tve *tve, void __iomem *base)
457 const char *tve_di_parent[1];
458 struct clk_init_data init = {
460 .ops = &clk_tve_di_ops,
465 tve_di_parent[0] = __clk_get_name(tve->clk);
466 init.parent_names = (const char **)&tve_di_parent;
468 tve->clk_hw_di.init = &init;
469 tve->di_clk = clk_register(tve->dev, &tve->clk_hw_di);
470 if (IS_ERR(tve->di_clk)) {
471 dev_err(tve->dev, "failed to register TVE output clock: %ld\n",
472 PTR_ERR(tve->di_clk));
473 return PTR_ERR(tve->di_clk);
479 static int imx_tve_register(struct drm_device *drm, struct imx_tve *tve)
484 encoder_type = tve->mode == TVE_MODE_VGA ?
485 DRM_MODE_ENCODER_DAC : DRM_MODE_ENCODER_TVDAC;
487 ret = imx_drm_encoder_parse_of(drm, &tve->encoder, tve->dev->of_node);
491 drm_encoder_helper_add(&tve->encoder, &imx_tve_encoder_helper_funcs);
492 drm_encoder_init(drm, &tve->encoder, &imx_tve_encoder_funcs,
495 drm_connector_helper_add(&tve->connector,
496 &imx_tve_connector_helper_funcs);
497 drm_connector_init(drm, &tve->connector, &imx_tve_connector_funcs,
498 DRM_MODE_CONNECTOR_VGA);
500 drm_mode_connector_attach_encoder(&tve->connector, &tve->encoder);
505 static bool imx_tve_readable_reg(struct device *dev, unsigned int reg)
507 return (reg % 4 == 0) && (reg <= 0xdc);
510 static struct regmap_config tve_regmap_config = {
515 .readable_reg = imx_tve_readable_reg,
518 .unlock = tve_unlock,
520 .max_register = 0xdc,
523 static const char * const imx_tve_modes[] = {
524 [TVE_MODE_TVOUT] = "tvout",
525 [TVE_MODE_VGA] = "vga",
528 static const int of_get_tve_mode(struct device_node *np)
533 ret = of_property_read_string(np, "fsl,tve-mode", &bm);
537 for (i = 0; i < ARRAY_SIZE(imx_tve_modes); i++)
538 if (!strcasecmp(bm, imx_tve_modes[i]))
544 static int imx_tve_bind(struct device *dev, struct device *master, void *data)
546 struct platform_device *pdev = to_platform_device(dev);
547 struct drm_device *drm = data;
548 struct device_node *np = dev->of_node;
549 struct device_node *ddc_node;
551 struct resource *res;
557 tve = devm_kzalloc(dev, sizeof(*tve), GFP_KERNEL);
562 spin_lock_init(&tve->lock);
564 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
566 tve->ddc = of_find_i2c_adapter_by_node(ddc_node);
567 of_node_put(ddc_node);
570 tve->mode = of_get_tve_mode(np);
571 if (tve->mode != TVE_MODE_VGA) {
572 dev_err(dev, "only VGA mode supported, currently\n");
576 if (tve->mode == TVE_MODE_VGA) {
577 ret = of_property_read_u32(np, "fsl,hsync-pin",
581 dev_err(dev, "failed to get hsync pin\n");
585 ret = of_property_read_u32(np, "fsl,vsync-pin",
589 dev_err(dev, "failed to get vsync pin\n");
594 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
595 base = devm_ioremap_resource(dev, res);
597 return PTR_ERR(base);
599 tve_regmap_config.lock_arg = tve;
600 tve->regmap = devm_regmap_init_mmio_clk(dev, "tve", base,
602 if (IS_ERR(tve->regmap)) {
603 dev_err(dev, "failed to init regmap: %ld\n",
604 PTR_ERR(tve->regmap));
605 return PTR_ERR(tve->regmap);
608 irq = platform_get_irq(pdev, 0);
610 dev_err(dev, "failed to get irq\n");
614 ret = devm_request_threaded_irq(dev, irq, NULL,
615 imx_tve_irq_handler, IRQF_ONESHOT,
618 dev_err(dev, "failed to request irq: %d\n", ret);
622 tve->dac_reg = devm_regulator_get(dev, "dac");
623 if (!IS_ERR(tve->dac_reg)) {
624 ret = regulator_set_voltage(tve->dac_reg, 2750000, 2750000);
627 ret = regulator_enable(tve->dac_reg);
632 tve->clk = devm_clk_get(dev, "tve");
633 if (IS_ERR(tve->clk)) {
634 dev_err(dev, "failed to get high speed tve clock: %ld\n",
636 return PTR_ERR(tve->clk);
639 /* this is the IPU DI clock input selector, can be parented to tve_di */
640 tve->di_sel_clk = devm_clk_get(dev, "di_sel");
641 if (IS_ERR(tve->di_sel_clk)) {
642 dev_err(dev, "failed to get ipu di mux clock: %ld\n",
643 PTR_ERR(tve->di_sel_clk));
644 return PTR_ERR(tve->di_sel_clk);
647 ret = tve_clk_init(tve, base);
651 ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
653 dev_err(dev, "failed to read configuration register: %d\n",
657 if (val != 0x00100000) {
658 dev_err(dev, "configuration register default value indicates this is not a TVEv2\n");
662 /* disable cable detection for VGA mode */
663 ret = regmap_write(tve->regmap, TVE_CD_CONT_REG, 0);
667 ret = imx_tve_register(drm, tve);
671 dev_set_drvdata(dev, tve);
676 static void imx_tve_unbind(struct device *dev, struct device *master,
679 struct imx_tve *tve = dev_get_drvdata(dev);
681 if (!IS_ERR(tve->dac_reg))
682 regulator_disable(tve->dac_reg);
685 static const struct component_ops imx_tve_ops = {
686 .bind = imx_tve_bind,
687 .unbind = imx_tve_unbind,
690 static int imx_tve_probe(struct platform_device *pdev)
692 return component_add(&pdev->dev, &imx_tve_ops);
695 static int imx_tve_remove(struct platform_device *pdev)
697 component_del(&pdev->dev, &imx_tve_ops);
701 static const struct of_device_id imx_tve_dt_ids[] = {
702 { .compatible = "fsl,imx53-tve", },
705 MODULE_DEVICE_TABLE(of, imx_tve_dt_ids);
707 static struct platform_driver imx_tve_driver = {
708 .probe = imx_tve_probe,
709 .remove = imx_tve_remove,
711 .of_match_table = imx_tve_dt_ids,
716 module_platform_driver(imx_tve_driver);
718 MODULE_DESCRIPTION("i.MX Television Encoder driver");
719 MODULE_AUTHOR("Philipp Zabel, Pengutronix");
720 MODULE_LICENSE("GPL");
721 MODULE_ALIAS("platform:imx-tve");