2 * Copyright 2010 Matt Turner.
3 * Copyright 2012 Red Hat
5 * This file is subject to the terms and conditions of the GNU General
6 * Public License version 2. See the file COPYING in the main
7 * directory of this archive for more details.
9 * Authors: Matthew Garrett
14 #include <linux/delay.h>
17 #include <drm/drm_crtc_helper.h>
18 #include <drm/drm_plane_helper.h>
20 #include "mgag200_drv.h"
22 #define MGAG200_LUT_SIZE 256
25 * This file contains setup code for the CRTC.
28 static void mga_crtc_load_lut(struct drm_crtc *crtc)
30 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
31 struct drm_device *dev = crtc->dev;
32 struct mga_device *mdev = dev->dev_private;
33 struct drm_framebuffer *fb = crtc->primary->fb;
39 WREG8(DAC_INDEX + MGA1064_INDEX, 0);
41 if (fb && fb->bits_per_pixel == 16) {
42 int inc = (fb->depth == 15) ? 8 : 4;
44 for (i = 0; i < MGAG200_LUT_SIZE; i += inc) {
45 if (fb->depth == 16) {
46 if (i > (MGAG200_LUT_SIZE >> 1)) {
49 r = mga_crtc->lut_r[i << 1];
50 b = mga_crtc->lut_b[i << 1];
53 r = mga_crtc->lut_r[i];
54 b = mga_crtc->lut_b[i];
57 WREG8(DAC_INDEX + MGA1064_COL_PAL, r);
58 WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_g[i]);
59 WREG8(DAC_INDEX + MGA1064_COL_PAL, b);
63 for (i = 0; i < MGAG200_LUT_SIZE; i++) {
65 WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_r[i]);
66 WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_g[i]);
67 WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_b[i]);
71 static inline void mga_wait_vsync(struct mga_device *mdev)
73 unsigned long timeout = jiffies + HZ/10;
74 unsigned int status = 0;
77 status = RREG32(MGAREG_Status);
78 } while ((status & 0x08) && time_before(jiffies, timeout));
79 timeout = jiffies + HZ/10;
82 status = RREG32(MGAREG_Status);
83 } while (!(status & 0x08) && time_before(jiffies, timeout));
86 static inline void mga_wait_busy(struct mga_device *mdev)
88 unsigned long timeout = jiffies + HZ;
89 unsigned int status = 0;
91 status = RREG8(MGAREG_Status + 2);
92 } while ((status & 0x01) && time_before(jiffies, timeout));
95 #define P_ARRAY_SIZE 9
97 static int mga_g200se_set_plls(struct mga_device *mdev, long clock)
99 unsigned int vcomax, vcomin, pllreffreq;
100 unsigned int delta, tmpdelta, permitteddelta;
101 unsigned int testp, testm, testn;
102 unsigned int p, m, n;
103 unsigned int computed;
104 unsigned int pvalues_e4[P_ARRAY_SIZE] = {16, 14, 12, 10, 8, 6, 4, 2, 1};
108 if (mdev->unique_rev_id <= 0x03) {
116 permitteddelta = clock * 5 / 1000;
118 for (testp = 8; testp > 0; testp /= 2) {
119 if (clock * testp > vcomax)
121 if (clock * testp < vcomin)
124 for (testn = 17; testn < 256; testn++) {
125 for (testm = 1; testm < 32; testm++) {
126 computed = (pllreffreq * testn) /
128 if (computed > clock)
129 tmpdelta = computed - clock;
131 tmpdelta = clock - computed;
132 if (tmpdelta < delta) {
155 /* Permited delta is 0.5% as VESA Specification */
156 permitteddelta = clock * 5 / 1000;
158 for (i = 0 ; i < P_ARRAY_SIZE ; i++) {
159 testp = pvalues_e4[i];
161 if ((clock * testp) > vcomax)
163 if ((clock * testp) < vcomin)
166 for (testn = 50; testn <= 256; testn++) {
167 for (testm = 1; testm <= 32; testm++) {
168 computed = (pllreffreq * testn) /
170 if (computed > clock)
171 tmpdelta = computed - clock;
173 tmpdelta = clock - computed;
175 if (tmpdelta < delta) {
185 fvv = pllreffreq * testn / testm;
186 fvv = (fvv - 800000) / 50000;
197 if (delta > permitteddelta) {
198 printk(KERN_WARNING "PLL delta too large\n");
202 WREG_DAC(MGA1064_PIX_PLLC_M, m);
203 WREG_DAC(MGA1064_PIX_PLLC_N, n);
204 WREG_DAC(MGA1064_PIX_PLLC_P, p);
208 static int mga_g200wb_set_plls(struct mga_device *mdev, long clock)
210 unsigned int vcomax, vcomin, pllreffreq;
211 unsigned int delta, tmpdelta;
212 unsigned int testp, testm, testn, testp2;
213 unsigned int p, m, n;
214 unsigned int computed;
215 int i, j, tmpcount, vcount;
216 bool pll_locked = false;
223 if (mdev->type == G200_EW3) {
229 for (testp = 1; testp < 8; testp++) {
230 for (testp2 = 1; testp2 < 8; testp2++) {
233 if ((clock * testp * testp2) > vcomax)
235 if ((clock * testp * testp2) < vcomin)
237 for (testm = 1; testm < 26; testm++) {
238 for (testn = 32; testn < 2048 ; testn++) {
239 computed = (pllreffreq * testn) /
240 (testm * testp * testp2);
241 if (computed > clock)
242 tmpdelta = computed - clock;
244 tmpdelta = clock - computed;
245 if (tmpdelta < delta) {
247 m = ((testn & 0x100) >> 1) |
250 p = ((testn & 0x600) >> 3) |
264 for (testp = 1; testp < 9; testp++) {
265 if (clock * testp > vcomax)
267 if (clock * testp < vcomin)
270 for (testm = 1; testm < 17; testm++) {
271 for (testn = 1; testn < 151; testn++) {
272 computed = (pllreffreq * testn) /
274 if (computed > clock)
275 tmpdelta = computed - clock;
277 tmpdelta = clock - computed;
278 if (tmpdelta < delta) {
290 for (i = 0; i <= 32 && pll_locked == false; i++) {
292 WREG8(MGAREG_CRTC_INDEX, 0x1e);
293 tmp = RREG8(MGAREG_CRTC_DATA);
295 WREG8(MGAREG_CRTC_DATA, tmp+1);
298 /* set pixclkdis to 1 */
299 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
300 tmp = RREG8(DAC_DATA);
301 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
302 WREG8(DAC_DATA, tmp);
304 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
305 tmp = RREG8(DAC_DATA);
306 tmp |= MGA1064_REMHEADCTL_CLKDIS;
307 WREG8(DAC_DATA, tmp);
309 /* select PLL Set C */
310 tmp = RREG8(MGAREG_MEM_MISC_READ);
312 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
314 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
315 tmp = RREG8(DAC_DATA);
316 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN | 0x80;
317 WREG8(DAC_DATA, tmp);
322 WREG8(DAC_INDEX, MGA1064_VREF_CTL);
323 tmp = RREG8(DAC_DATA);
325 WREG8(DAC_DATA, tmp);
329 /* program pixel pll register */
330 WREG_DAC(MGA1064_WB_PIX_PLLC_N, n);
331 WREG_DAC(MGA1064_WB_PIX_PLLC_M, m);
332 WREG_DAC(MGA1064_WB_PIX_PLLC_P, p);
337 WREG8(DAC_INDEX, MGA1064_VREF_CTL);
338 tmp = RREG8(DAC_DATA);
340 WREG_DAC(MGA1064_VREF_CTL, tmp);
344 /* select the pixel pll */
345 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
346 tmp = RREG8(DAC_DATA);
347 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
348 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
349 WREG8(DAC_DATA, tmp);
351 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
352 tmp = RREG8(DAC_DATA);
353 tmp &= ~MGA1064_REMHEADCTL_CLKSL_MSK;
354 tmp |= MGA1064_REMHEADCTL_CLKSL_PLL;
355 WREG8(DAC_DATA, tmp);
357 /* reset dotclock rate bit */
358 WREG8(MGAREG_SEQ_INDEX, 1);
359 tmp = RREG8(MGAREG_SEQ_DATA);
361 WREG8(MGAREG_SEQ_DATA, tmp);
363 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
364 tmp = RREG8(DAC_DATA);
365 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
366 WREG8(DAC_DATA, tmp);
368 vcount = RREG8(MGAREG_VCOUNT);
370 for (j = 0; j < 30 && pll_locked == false; j++) {
371 tmpcount = RREG8(MGAREG_VCOUNT);
372 if (tmpcount < vcount)
374 if ((tmpcount - vcount) > 2)
380 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
381 tmp = RREG8(DAC_DATA);
382 tmp &= ~MGA1064_REMHEADCTL_CLKDIS;
383 WREG_DAC(MGA1064_REMHEADCTL, tmp);
387 static int mga_g200ev_set_plls(struct mga_device *mdev, long clock)
389 unsigned int vcomax, vcomin, pllreffreq;
390 unsigned int delta, tmpdelta;
391 unsigned int testp, testm, testn;
392 unsigned int p, m, n;
393 unsigned int computed;
403 for (testp = 16; testp > 0; testp--) {
404 if (clock * testp > vcomax)
406 if (clock * testp < vcomin)
409 for (testn = 1; testn < 257; testn++) {
410 for (testm = 1; testm < 17; testm++) {
411 computed = (pllreffreq * testn) /
413 if (computed > clock)
414 tmpdelta = computed - clock;
416 tmpdelta = clock - computed;
417 if (tmpdelta < delta) {
427 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
428 tmp = RREG8(DAC_DATA);
429 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
430 WREG8(DAC_DATA, tmp);
432 tmp = RREG8(MGAREG_MEM_MISC_READ);
434 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
436 WREG8(DAC_INDEX, MGA1064_PIX_PLL_STAT);
437 tmp = RREG8(DAC_DATA);
438 WREG8(DAC_DATA, tmp & ~0x40);
440 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
441 tmp = RREG8(DAC_DATA);
442 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
443 WREG8(DAC_DATA, tmp);
445 WREG_DAC(MGA1064_EV_PIX_PLLC_M, m);
446 WREG_DAC(MGA1064_EV_PIX_PLLC_N, n);
447 WREG_DAC(MGA1064_EV_PIX_PLLC_P, p);
451 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
452 tmp = RREG8(DAC_DATA);
453 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
454 WREG8(DAC_DATA, tmp);
458 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
459 tmp = RREG8(DAC_DATA);
460 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
461 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
462 WREG8(DAC_DATA, tmp);
464 WREG8(DAC_INDEX, MGA1064_PIX_PLL_STAT);
465 tmp = RREG8(DAC_DATA);
466 WREG8(DAC_DATA, tmp | 0x40);
468 tmp = RREG8(MGAREG_MEM_MISC_READ);
470 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
472 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
473 tmp = RREG8(DAC_DATA);
474 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
475 WREG8(DAC_DATA, tmp);
480 static int mga_g200eh_set_plls(struct mga_device *mdev, long clock)
482 unsigned int vcomax, vcomin, pllreffreq;
483 unsigned int delta, tmpdelta;
484 unsigned int testp, testm, testn;
485 unsigned int p, m, n;
486 unsigned int computed;
487 int i, j, tmpcount, vcount;
489 bool pll_locked = false;
498 for (testp = 16; testp > 0; testp >>= 1) {
499 if (clock * testp > vcomax)
501 if (clock * testp < vcomin)
504 for (testm = 1; testm < 33; testm++) {
505 for (testn = 17; testn < 257; testn++) {
506 computed = (pllreffreq * testn) /
508 if (computed > clock)
509 tmpdelta = computed - clock;
511 tmpdelta = clock - computed;
512 if (tmpdelta < delta) {
518 if ((clock * testp) >= 600000)
523 for (i = 0; i <= 32 && pll_locked == false; i++) {
524 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
525 tmp = RREG8(DAC_DATA);
526 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
527 WREG8(DAC_DATA, tmp);
529 tmp = RREG8(MGAREG_MEM_MISC_READ);
531 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
533 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
534 tmp = RREG8(DAC_DATA);
535 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
536 WREG8(DAC_DATA, tmp);
540 WREG_DAC(MGA1064_EH_PIX_PLLC_M, m);
541 WREG_DAC(MGA1064_EH_PIX_PLLC_N, n);
542 WREG_DAC(MGA1064_EH_PIX_PLLC_P, p);
546 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
547 tmp = RREG8(DAC_DATA);
548 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
549 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
550 WREG8(DAC_DATA, tmp);
552 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
553 tmp = RREG8(DAC_DATA);
554 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
555 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
556 WREG8(DAC_DATA, tmp);
558 vcount = RREG8(MGAREG_VCOUNT);
560 for (j = 0; j < 30 && pll_locked == false; j++) {
561 tmpcount = RREG8(MGAREG_VCOUNT);
562 if (tmpcount < vcount)
564 if ((tmpcount - vcount) > 2)
574 static int mga_g200er_set_plls(struct mga_device *mdev, long clock)
576 unsigned int vcomax, vcomin, pllreffreq;
577 unsigned int delta, tmpdelta;
578 int testr, testn, testm, testo;
579 unsigned int p, m, n;
580 unsigned int computed, vco;
582 const unsigned int m_div_val[] = { 1, 2, 4, 8 };
591 for (testr = 0; testr < 4; testr++) {
594 for (testn = 5; testn < 129; testn++) {
597 for (testm = 3; testm >= 0; testm--) {
600 for (testo = 5; testo < 33; testo++) {
601 vco = pllreffreq * (testn + 1) /
607 computed = vco / (m_div_val[testm] * (testo + 1));
608 if (computed > clock)
609 tmpdelta = computed - clock;
611 tmpdelta = clock - computed;
612 if (tmpdelta < delta) {
614 m = testm | (testo << 3);
616 p = testr | (testr << 3);
623 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
624 tmp = RREG8(DAC_DATA);
625 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
626 WREG8(DAC_DATA, tmp);
628 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
629 tmp = RREG8(DAC_DATA);
630 tmp |= MGA1064_REMHEADCTL_CLKDIS;
631 WREG8(DAC_DATA, tmp);
633 tmp = RREG8(MGAREG_MEM_MISC_READ);
634 tmp |= (0x3<<2) | 0xc0;
635 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
637 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
638 tmp = RREG8(DAC_DATA);
639 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
640 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
641 WREG8(DAC_DATA, tmp);
645 WREG_DAC(MGA1064_ER_PIX_PLLC_N, n);
646 WREG_DAC(MGA1064_ER_PIX_PLLC_M, m);
647 WREG_DAC(MGA1064_ER_PIX_PLLC_P, p);
654 static int mga_crtc_set_plls(struct mga_device *mdev, long clock)
659 return mga_g200se_set_plls(mdev, clock);
663 return mga_g200wb_set_plls(mdev, clock);
666 return mga_g200ev_set_plls(mdev, clock);
669 return mga_g200eh_set_plls(mdev, clock);
672 return mga_g200er_set_plls(mdev, clock);
678 static void mga_g200wb_prepare(struct drm_crtc *crtc)
680 struct mga_device *mdev = crtc->dev->dev_private;
684 /* 1- The first step is to warn the BMC of an upcoming mode change.
685 * We are putting the misc<0> to output.*/
687 WREG8(DAC_INDEX, MGA1064_GEN_IO_CTL);
688 tmp = RREG8(DAC_DATA);
690 WREG_DAC(MGA1064_GEN_IO_CTL, tmp);
692 /* we are putting a 1 on the misc<0> line */
693 WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA);
694 tmp = RREG8(DAC_DATA);
696 WREG_DAC(MGA1064_GEN_IO_DATA, tmp);
698 /* 2- Second step to mask and further scan request
699 * This will be done by asserting the remfreqmsk bit (XSPAREREG<7>)
701 WREG8(DAC_INDEX, MGA1064_SPAREREG);
702 tmp = RREG8(DAC_DATA);
704 WREG_DAC(MGA1064_SPAREREG, tmp);
706 /* 3a- the third step is to verifu if there is an active scan
707 * We are searching for a 0 on remhsyncsts <XSPAREREG<0>)
710 while (!(tmp & 0x1) && iter_max) {
711 WREG8(DAC_INDEX, MGA1064_SPAREREG);
712 tmp = RREG8(DAC_DATA);
717 /* 3b- this step occurs only if the remove is actually scanning
718 * we are waiting for the end of the frame which is a 1 on
719 * remvsyncsts (XSPAREREG<1>)
723 while ((tmp & 0x2) && iter_max) {
724 WREG8(DAC_INDEX, MGA1064_SPAREREG);
725 tmp = RREG8(DAC_DATA);
732 static void mga_g200wb_commit(struct drm_crtc *crtc)
735 struct mga_device *mdev = crtc->dev->dev_private;
737 /* 1- The first step is to ensure that the vrsten and hrsten are set */
738 WREG8(MGAREG_CRTCEXT_INDEX, 1);
739 tmp = RREG8(MGAREG_CRTCEXT_DATA);
740 WREG8(MGAREG_CRTCEXT_DATA, tmp | 0x88);
742 /* 2- second step is to assert the rstlvl2 */
743 WREG8(DAC_INDEX, MGA1064_REMHEADCTL2);
744 tmp = RREG8(DAC_DATA);
746 WREG8(DAC_DATA, tmp);
751 /* 3- deassert rstlvl2 */
753 WREG8(DAC_INDEX, MGA1064_REMHEADCTL2);
754 WREG8(DAC_DATA, tmp);
756 /* 4- remove mask of scan request */
757 WREG8(DAC_INDEX, MGA1064_SPAREREG);
758 tmp = RREG8(DAC_DATA);
760 WREG8(DAC_DATA, tmp);
762 /* 5- put back a 0 on the misc<0> line */
763 WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA);
764 tmp = RREG8(DAC_DATA);
766 WREG_DAC(MGA1064_GEN_IO_DATA, tmp);
770 This is how the framebuffer base address is stored in g200 cards:
771 * Assume @offset is the gpu_addr variable of the framebuffer object
772 * Then addr is the number of _pixels_ (not bytes) from the start of
773 VRAM to the first pixel we want to display. (divided by 2 for 32bit
775 * addr is stored in the CRTCEXT0, CRTCC and CRTCD registers
776 addr<20> -> CRTCEXT0<6>
777 addr<19-16> -> CRTCEXT0<3-0>
778 addr<15-8> -> CRTCC<7-0>
779 addr<7-0> -> CRTCD<7-0>
780 CRTCEXT0 has to be programmed last to trigger an update and make the
781 new addr variable take effect.
783 static void mga_set_start_address(struct drm_crtc *crtc, unsigned offset)
785 struct mga_device *mdev = crtc->dev->dev_private;
790 while (RREG8(0x1fda) & 0x08);
791 while (!(RREG8(0x1fda) & 0x08));
793 count = RREG8(MGAREG_VCOUNT) + 2;
794 while (RREG8(MGAREG_VCOUNT) < count);
796 WREG8(MGAREG_CRTCEXT_INDEX, 0);
797 crtcext0 = RREG8(MGAREG_CRTCEXT_DATA);
800 /* Can't store addresses any higher than that...
801 but we also don't have more than 16MB of memory, so it should be fine. */
802 WARN_ON(addr > 0x1fffff);
803 crtcext0 |= (!!(addr & (1<<20)))<<6;
804 WREG_CRT(0x0d, (u8)(addr & 0xff));
805 WREG_CRT(0x0c, (u8)(addr >> 8) & 0xff);
806 WREG_ECRT(0x0, ((u8)(addr >> 16) & 0xf) | crtcext0);
810 /* ast is different - we will force move buffers out of VRAM */
811 static int mga_crtc_do_set_base(struct drm_crtc *crtc,
812 struct drm_framebuffer *fb,
813 int x, int y, int atomic)
815 struct mga_device *mdev = crtc->dev->dev_private;
816 struct drm_gem_object *obj;
817 struct mga_framebuffer *mga_fb;
818 struct mgag200_bo *bo;
822 /* push the previous fb to system ram */
824 mga_fb = to_mga_framebuffer(fb);
826 bo = gem_to_mga_bo(obj);
827 ret = mgag200_bo_reserve(bo, false);
830 mgag200_bo_push_sysram(bo);
831 mgag200_bo_unreserve(bo);
834 mga_fb = to_mga_framebuffer(crtc->primary->fb);
836 bo = gem_to_mga_bo(obj);
838 ret = mgag200_bo_reserve(bo, false);
842 ret = mgag200_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr);
844 mgag200_bo_unreserve(bo);
848 if (&mdev->mfbdev->mfb == mga_fb) {
849 /* if pushing console in kmap it */
850 ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &bo->kmap);
852 DRM_ERROR("failed to kmap fbcon\n");
855 mgag200_bo_unreserve(bo);
857 mga_set_start_address(crtc, (u32)gpu_addr);
862 static int mga_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
863 struct drm_framebuffer *old_fb)
865 return mga_crtc_do_set_base(crtc, old_fb, x, y, 0);
868 static int mga_crtc_mode_set(struct drm_crtc *crtc,
869 struct drm_display_mode *mode,
870 struct drm_display_mode *adjusted_mode,
871 int x, int y, struct drm_framebuffer *old_fb)
873 struct drm_device *dev = crtc->dev;
874 struct mga_device *mdev = dev->dev_private;
875 int hdisplay, hsyncstart, hsyncend, htotal;
876 int vdisplay, vsyncstart, vsyncend, vtotal;
878 int option = 0, option2 = 0;
880 unsigned char misc = 0;
881 unsigned char ext_vga[6];
884 static unsigned char dacvalue[] = {
885 /* 0x00: */ 0, 0, 0, 0, 0, 0, 0x00, 0,
886 /* 0x08: */ 0, 0, 0, 0, 0, 0, 0, 0,
887 /* 0x10: */ 0, 0, 0, 0, 0, 0, 0, 0,
888 /* 0x18: */ 0x00, 0, 0xC9, 0xFF, 0xBF, 0x20, 0x1F, 0x20,
889 /* 0x20: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
890 /* 0x28: */ 0x00, 0x00, 0x00, 0x00, 0, 0, 0, 0x40,
891 /* 0x30: */ 0x00, 0xB0, 0x00, 0xC2, 0x34, 0x14, 0x02, 0x83,
892 /* 0x38: */ 0x00, 0x93, 0x00, 0x77, 0x00, 0x00, 0x00, 0x3A,
893 /* 0x40: */ 0, 0, 0, 0, 0, 0, 0, 0,
894 /* 0x48: */ 0, 0, 0, 0, 0, 0, 0, 0
897 bppshift = mdev->bpp_shifts[(crtc->primary->fb->bits_per_pixel >> 3) - 1];
899 switch (mdev->type) {
902 dacvalue[MGA1064_VREF_CTL] = 0x03;
903 dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL;
904 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_DAC_EN |
905 MGA1064_MISC_CTL_VGA8 |
906 MGA1064_MISC_CTL_DAC_RAM_CS;
911 option2 = 0x00008000;
915 dacvalue[MGA1064_VREF_CTL] = 0x07;
917 option2 = 0x0000b000;
920 dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL;
921 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 |
922 MGA1064_MISC_CTL_DAC_RAM_CS;
924 option2 = 0x0000b000;
927 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 |
928 MGA1064_MISC_CTL_DAC_RAM_CS;
930 option2 = 0x0000b000;
936 switch (crtc->primary->fb->bits_per_pixel) {
938 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_8bits;
941 if (crtc->primary->fb->depth == 15)
942 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_15bits;
944 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_16bits;
947 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_24bits;
950 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_32_24bits;
954 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
956 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
960 for (i = 0; i < sizeof(dacvalue); i++) {
964 ((i >= 0x1f) && (i <= 0x29)) ||
965 ((i >= 0x30) && (i <= 0x37)))
967 if (IS_G200_SE(mdev) &&
968 ((i == 0x2c) || (i == 0x2d) || (i == 0x2e)))
970 if ((mdev->type == G200_EV ||
971 mdev->type == G200_WB ||
972 mdev->type == G200_EH ||
973 mdev->type == G200_EW3) &&
974 (i >= 0x44) && (i <= 0x4e))
977 WREG_DAC(i, dacvalue[i]);
980 if (mdev->type == G200_ER)
984 pci_write_config_dword(dev->pdev, PCI_MGA_OPTION, option);
986 pci_write_config_dword(dev->pdev, PCI_MGA_OPTION2, option2);
992 pitch = crtc->primary->fb->pitches[0] / (crtc->primary->fb->bits_per_pixel / 8);
993 if (crtc->primary->fb->bits_per_pixel == 24)
994 pitch = (pitch * 3) >> (4 - bppshift);
996 pitch = pitch >> (4 - bppshift);
998 hdisplay = mode->hdisplay / 8 - 1;
999 hsyncstart = mode->hsync_start / 8 - 1;
1000 hsyncend = mode->hsync_end / 8 - 1;
1001 htotal = mode->htotal / 8 - 1;
1003 /* Work around hardware quirk */
1004 if ((htotal & 0x07) == 0x06 || (htotal & 0x07) == 0x04)
1007 vdisplay = mode->vdisplay - 1;
1008 vsyncstart = mode->vsync_start - 1;
1009 vsyncend = mode->vsync_end - 1;
1010 vtotal = mode->vtotal - 2;
1022 WREG_CRT(0, htotal - 4);
1023 WREG_CRT(1, hdisplay);
1024 WREG_CRT(2, hdisplay);
1025 WREG_CRT(3, (htotal & 0x1F) | 0x80);
1026 WREG_CRT(4, hsyncstart);
1027 WREG_CRT(5, ((htotal & 0x20) << 2) | (hsyncend & 0x1F));
1028 WREG_CRT(6, vtotal & 0xFF);
1029 WREG_CRT(7, ((vtotal & 0x100) >> 8) |
1030 ((vdisplay & 0x100) >> 7) |
1031 ((vsyncstart & 0x100) >> 6) |
1032 ((vdisplay & 0x100) >> 5) |
1033 ((vdisplay & 0x100) >> 4) | /* linecomp */
1034 ((vtotal & 0x200) >> 4)|
1035 ((vdisplay & 0x200) >> 3) |
1036 ((vsyncstart & 0x200) >> 2));
1037 WREG_CRT(9, ((vdisplay & 0x200) >> 4) |
1038 ((vdisplay & 0x200) >> 3));
1045 WREG_CRT(16, vsyncstart & 0xFF);
1046 WREG_CRT(17, (vsyncend & 0x0F) | 0x20);
1047 WREG_CRT(18, vdisplay & 0xFF);
1048 WREG_CRT(19, pitch & 0xFF);
1050 WREG_CRT(21, vdisplay & 0xFF);
1051 WREG_CRT(22, (vtotal + 1) & 0xFF);
1053 WREG_CRT(24, vdisplay & 0xFF);
1058 /* TODO interlace */
1060 ext_vga[0] |= (pitch & 0x300) >> 4;
1061 ext_vga[1] = (((htotal - 4) & 0x100) >> 8) |
1062 ((hdisplay & 0x100) >> 7) |
1063 ((hsyncstart & 0x100) >> 6) |
1065 ext_vga[2] = ((vtotal & 0xc00) >> 10) |
1066 ((vdisplay & 0x400) >> 8) |
1067 ((vdisplay & 0xc00) >> 7) |
1068 ((vsyncstart & 0xc00) >> 5) |
1069 ((vdisplay & 0x400) >> 3);
1070 if (crtc->primary->fb->bits_per_pixel == 24)
1071 ext_vga[3] = (((1 << bppshift) * 3) - 1) | 0x80;
1073 ext_vga[3] = ((1 << bppshift) - 1) | 0x80;
1075 if (mdev->type == G200_WB || mdev->type == G200_EW3)
1078 /* Set pixel clocks */
1080 WREG8(MGA_MISC_OUT, misc);
1082 mga_crtc_set_plls(mdev, mode->clock);
1084 for (i = 0; i < 6; i++) {
1085 WREG_ECRT(i, ext_vga[i]);
1088 if (mdev->type == G200_ER)
1089 WREG_ECRT(0x24, 0x5);
1091 if (mdev->type == G200_EW3)
1092 WREG_ECRT(0x34, 0x5);
1094 if (mdev->type == G200_EV) {
1098 WREG_ECRT(0, ext_vga[0]);
1099 /* Enable mga pixel clock */
1102 WREG8(MGA_MISC_OUT, misc);
1105 memcpy(&mdev->mode, mode, sizeof(struct drm_display_mode));
1107 mga_crtc_do_set_base(crtc, old_fb, x, y, 0);
1110 if (mdev->type == G200_ER) {
1111 u32 mem_ctl = RREG32(MGAREG_MEMCTL);
1115 WREG8(MGAREG_SEQ_INDEX, 0x01);
1116 seq1 = RREG8(MGAREG_SEQ_DATA) | 0x20;
1117 WREG8(MGAREG_SEQ_DATA, seq1);
1119 WREG32(MGAREG_MEMCTL, mem_ctl | 0x00200000);
1121 WREG32(MGAREG_MEMCTL, mem_ctl & ~0x00200000);
1123 WREG8(MGAREG_SEQ_DATA, seq1 & ~0x20);
1127 if (IS_G200_SE(mdev)) {
1128 if (mdev->unique_rev_id >= 0x02) {
1133 if (crtc->primary->fb->bits_per_pixel > 16)
1135 else if (crtc->primary->fb->bits_per_pixel > 8)
1140 mb = (mode->clock * bpp) / 1000;
1154 WREG8(MGAREG_CRTCEXT_INDEX, 0x06);
1155 WREG8(MGAREG_CRTCEXT_DATA, hi_pri_lvl);
1157 WREG8(MGAREG_CRTCEXT_INDEX, 0x06);
1158 if (mdev->unique_rev_id >= 0x01)
1159 WREG8(MGAREG_CRTCEXT_DATA, 0x03);
1161 WREG8(MGAREG_CRTCEXT_DATA, 0x04);
1167 #if 0 /* code from mjg to attempt D3 on crtc dpms off - revisit later */
1168 static int mga_suspend(struct drm_crtc *crtc)
1170 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1171 struct drm_device *dev = crtc->dev;
1172 struct mga_device *mdev = dev->dev_private;
1173 struct pci_dev *pdev = dev->pdev;
1176 if (mdev->suspended)
1181 /* Disable the pixel clock */
1182 WREG_DAC(0x1a, 0x05);
1183 /* Power down the DAC */
1184 WREG_DAC(0x1e, 0x18);
1185 /* Power down the pixel PLL */
1186 WREG_DAC(0x1a, 0x0d);
1188 /* Disable PLLs and clocks */
1189 pci_read_config_dword(pdev, PCI_MGA_OPTION, &option);
1190 option &= ~(0x1F8024);
1191 pci_write_config_dword(pdev, PCI_MGA_OPTION, option);
1192 pci_set_power_state(pdev, PCI_D3hot);
1193 pci_disable_device(pdev);
1195 mdev->suspended = true;
1200 static int mga_resume(struct drm_crtc *crtc)
1202 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1203 struct drm_device *dev = crtc->dev;
1204 struct mga_device *mdev = dev->dev_private;
1205 struct pci_dev *pdev = dev->pdev;
1208 if (!mdev->suspended)
1211 pci_set_power_state(pdev, PCI_D0);
1212 pci_enable_device(pdev);
1214 /* Disable sysclk */
1215 pci_read_config_dword(pdev, PCI_MGA_OPTION, &option);
1217 pci_write_config_dword(pdev, PCI_MGA_OPTION, option);
1219 mdev->suspended = false;
1226 static void mga_crtc_dpms(struct drm_crtc *crtc, int mode)
1228 struct drm_device *dev = crtc->dev;
1229 struct mga_device *mdev = dev->dev_private;
1230 u8 seq1 = 0, crtcext1 = 0;
1233 case DRM_MODE_DPMS_ON:
1236 mga_crtc_load_lut(crtc);
1238 case DRM_MODE_DPMS_STANDBY:
1242 case DRM_MODE_DPMS_SUSPEND:
1246 case DRM_MODE_DPMS_OFF:
1253 if (mode == DRM_MODE_DPMS_OFF) {
1257 WREG8(MGAREG_SEQ_INDEX, 0x01);
1258 seq1 |= RREG8(MGAREG_SEQ_DATA) & ~0x20;
1259 mga_wait_vsync(mdev);
1260 mga_wait_busy(mdev);
1261 WREG8(MGAREG_SEQ_DATA, seq1);
1263 WREG8(MGAREG_CRTCEXT_INDEX, 0x01);
1264 crtcext1 |= RREG8(MGAREG_CRTCEXT_DATA) & ~0x30;
1265 WREG8(MGAREG_CRTCEXT_DATA, crtcext1);
1268 if (mode == DRM_MODE_DPMS_ON && mdev->suspended == true) {
1270 drm_helper_resume_force_mode(dev);
1276 * This is called before a mode is programmed. A typical use might be to
1277 * enable DPMS during the programming to avoid seeing intermediate stages,
1278 * but that's not relevant to us
1280 static void mga_crtc_prepare(struct drm_crtc *crtc)
1282 struct drm_device *dev = crtc->dev;
1283 struct mga_device *mdev = dev->dev_private;
1286 /* mga_resume(crtc);*/
1288 WREG8(MGAREG_CRTC_INDEX, 0x11);
1289 tmp = RREG8(MGAREG_CRTC_DATA);
1290 WREG_CRT(0x11, tmp | 0x80);
1292 if (mdev->type == G200_SE_A || mdev->type == G200_SE_B) {
1298 WREG8(MGAREG_SEQ_INDEX, 0x1);
1299 tmp = RREG8(MGAREG_SEQ_DATA);
1301 /* start sync reset */
1303 WREG_SEQ(1, tmp | 0x20);
1306 if (mdev->type == G200_WB || mdev->type == G200_EW3)
1307 mga_g200wb_prepare(crtc);
1313 * This is called after a mode is programmed. It should reverse anything done
1314 * by the prepare function
1316 static void mga_crtc_commit(struct drm_crtc *crtc)
1318 struct drm_device *dev = crtc->dev;
1319 struct mga_device *mdev = dev->dev_private;
1320 const struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1323 if (mdev->type == G200_WB || mdev->type == G200_EW3)
1324 mga_g200wb_commit(crtc);
1326 if (mdev->type == G200_SE_A || mdev->type == G200_SE_B) {
1332 WREG8(MGAREG_SEQ_INDEX, 0x1);
1333 tmp = RREG8(MGAREG_SEQ_DATA);
1339 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
1343 * The core can pass us a set of gamma values to program. We actually only
1344 * use this for 8-bit mode so can't perform smooth fades on deeper modes,
1345 * but it's a requirement that we provide the function
1347 static void mga_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
1348 u16 *blue, uint32_t start, uint32_t size)
1350 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1351 int end = (start + size > MGAG200_LUT_SIZE) ? MGAG200_LUT_SIZE : start + size;
1354 for (i = start; i < end; i++) {
1355 mga_crtc->lut_r[i] = red[i] >> 8;
1356 mga_crtc->lut_g[i] = green[i] >> 8;
1357 mga_crtc->lut_b[i] = blue[i] >> 8;
1359 mga_crtc_load_lut(crtc);
1362 /* Simple cleanup function */
1363 static void mga_crtc_destroy(struct drm_crtc *crtc)
1365 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1367 drm_crtc_cleanup(crtc);
1371 static void mga_crtc_disable(struct drm_crtc *crtc)
1374 DRM_DEBUG_KMS("\n");
1375 mga_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1376 if (crtc->primary->fb) {
1377 struct mga_framebuffer *mga_fb = to_mga_framebuffer(crtc->primary->fb);
1378 struct drm_gem_object *obj = mga_fb->obj;
1379 struct mgag200_bo *bo = gem_to_mga_bo(obj);
1380 ret = mgag200_bo_reserve(bo, false);
1383 mgag200_bo_push_sysram(bo);
1384 mgag200_bo_unreserve(bo);
1386 crtc->primary->fb = NULL;
1389 /* These provide the minimum set of functions required to handle a CRTC */
1390 static const struct drm_crtc_funcs mga_crtc_funcs = {
1391 .cursor_set = mga_crtc_cursor_set,
1392 .cursor_move = mga_crtc_cursor_move,
1393 .gamma_set = mga_crtc_gamma_set,
1394 .set_config = drm_crtc_helper_set_config,
1395 .destroy = mga_crtc_destroy,
1398 static const struct drm_crtc_helper_funcs mga_helper_funcs = {
1399 .disable = mga_crtc_disable,
1400 .dpms = mga_crtc_dpms,
1401 .mode_set = mga_crtc_mode_set,
1402 .mode_set_base = mga_crtc_mode_set_base,
1403 .prepare = mga_crtc_prepare,
1404 .commit = mga_crtc_commit,
1405 .load_lut = mga_crtc_load_lut,
1409 static void mga_crtc_init(struct mga_device *mdev)
1411 struct mga_crtc *mga_crtc;
1414 mga_crtc = kzalloc(sizeof(struct mga_crtc) +
1415 (MGAG200FB_CONN_LIMIT * sizeof(struct drm_connector *)),
1418 if (mga_crtc == NULL)
1421 drm_crtc_init(mdev->dev, &mga_crtc->base, &mga_crtc_funcs);
1423 drm_mode_crtc_set_gamma_size(&mga_crtc->base, MGAG200_LUT_SIZE);
1424 mdev->mode_info.crtc = mga_crtc;
1426 for (i = 0; i < MGAG200_LUT_SIZE; i++) {
1427 mga_crtc->lut_r[i] = i;
1428 mga_crtc->lut_g[i] = i;
1429 mga_crtc->lut_b[i] = i;
1432 drm_crtc_helper_add(&mga_crtc->base, &mga_helper_funcs);
1435 /** Sets the color ramps on behalf of fbcon */
1436 void mga_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
1437 u16 blue, int regno)
1439 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1441 mga_crtc->lut_r[regno] = red >> 8;
1442 mga_crtc->lut_g[regno] = green >> 8;
1443 mga_crtc->lut_b[regno] = blue >> 8;
1446 /** Gets the color ramps on behalf of fbcon */
1447 void mga_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
1448 u16 *blue, int regno)
1450 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1452 *red = (u16)mga_crtc->lut_r[regno] << 8;
1453 *green = (u16)mga_crtc->lut_g[regno] << 8;
1454 *blue = (u16)mga_crtc->lut_b[regno] << 8;
1458 * The encoder comes after the CRTC in the output pipeline, but before
1459 * the connector. It's responsible for ensuring that the digital
1460 * stream is appropriately converted into the output format. Setup is
1461 * very simple in this case - all we have to do is inform qemu of the
1462 * colour depth in order to ensure that it displays appropriately
1466 * These functions are analagous to those in the CRTC code, but are intended
1467 * to handle any encoder-specific limitations
1469 static void mga_encoder_mode_set(struct drm_encoder *encoder,
1470 struct drm_display_mode *mode,
1471 struct drm_display_mode *adjusted_mode)
1476 static void mga_encoder_dpms(struct drm_encoder *encoder, int state)
1481 static void mga_encoder_prepare(struct drm_encoder *encoder)
1485 static void mga_encoder_commit(struct drm_encoder *encoder)
1489 static void mga_encoder_destroy(struct drm_encoder *encoder)
1491 struct mga_encoder *mga_encoder = to_mga_encoder(encoder);
1492 drm_encoder_cleanup(encoder);
1496 static const struct drm_encoder_helper_funcs mga_encoder_helper_funcs = {
1497 .dpms = mga_encoder_dpms,
1498 .mode_set = mga_encoder_mode_set,
1499 .prepare = mga_encoder_prepare,
1500 .commit = mga_encoder_commit,
1503 static const struct drm_encoder_funcs mga_encoder_encoder_funcs = {
1504 .destroy = mga_encoder_destroy,
1507 static struct drm_encoder *mga_encoder_init(struct drm_device *dev)
1509 struct drm_encoder *encoder;
1510 struct mga_encoder *mga_encoder;
1512 mga_encoder = kzalloc(sizeof(struct mga_encoder), GFP_KERNEL);
1516 encoder = &mga_encoder->base;
1517 encoder->possible_crtcs = 0x1;
1519 drm_encoder_init(dev, encoder, &mga_encoder_encoder_funcs,
1520 DRM_MODE_ENCODER_DAC, NULL);
1521 drm_encoder_helper_add(encoder, &mga_encoder_helper_funcs);
1527 static int mga_vga_get_modes(struct drm_connector *connector)
1529 struct mga_connector *mga_connector = to_mga_connector(connector);
1533 edid = drm_get_edid(connector, &mga_connector->i2c->adapter);
1535 drm_mode_connector_update_edid_property(connector, edid);
1536 ret = drm_add_edid_modes(connector, edid);
1542 static uint32_t mga_vga_calculate_mode_bandwidth(struct drm_display_mode *mode,
1545 uint32_t total_area, divisor;
1546 uint64_t active_area, pixels_per_second, bandwidth;
1547 uint64_t bytes_per_pixel = (bits_per_pixel + 7) / 8;
1551 if (!mode->htotal || !mode->vtotal || !mode->clock)
1554 active_area = mode->hdisplay * mode->vdisplay;
1555 total_area = mode->htotal * mode->vtotal;
1557 pixels_per_second = active_area * mode->clock * 1000;
1558 do_div(pixels_per_second, total_area);
1560 bandwidth = pixels_per_second * bytes_per_pixel * 100;
1561 do_div(bandwidth, divisor);
1563 return (uint32_t)(bandwidth);
1566 #define MODE_BANDWIDTH MODE_BAD
1568 static int mga_vga_mode_valid(struct drm_connector *connector,
1569 struct drm_display_mode *mode)
1571 struct drm_device *dev = connector->dev;
1572 struct mga_device *mdev = (struct mga_device*)dev->dev_private;
1575 if (IS_G200_SE(mdev)) {
1576 if (mdev->unique_rev_id == 0x01) {
1577 if (mode->hdisplay > 1600)
1578 return MODE_VIRTUAL_X;
1579 if (mode->vdisplay > 1200)
1580 return MODE_VIRTUAL_Y;
1581 if (mga_vga_calculate_mode_bandwidth(mode, bpp)
1583 return MODE_BANDWIDTH;
1584 } else if (mdev->unique_rev_id == 0x02) {
1585 if (mode->hdisplay > 1920)
1586 return MODE_VIRTUAL_X;
1587 if (mode->vdisplay > 1200)
1588 return MODE_VIRTUAL_Y;
1589 if (mga_vga_calculate_mode_bandwidth(mode, bpp)
1591 return MODE_BANDWIDTH;
1593 } else if (mdev->type == G200_WB) {
1594 if (mode->hdisplay > 1280)
1595 return MODE_VIRTUAL_X;
1596 if (mode->vdisplay > 1024)
1597 return MODE_VIRTUAL_Y;
1598 if (mga_vga_calculate_mode_bandwidth(mode,
1599 bpp > (31877 * 1024)))
1600 return MODE_BANDWIDTH;
1601 } else if (mdev->type == G200_EV &&
1602 (mga_vga_calculate_mode_bandwidth(mode, bpp)
1603 > (32700 * 1024))) {
1604 return MODE_BANDWIDTH;
1605 } else if (mdev->type == G200_EH &&
1606 (mga_vga_calculate_mode_bandwidth(mode, bpp)
1607 > (37500 * 1024))) {
1608 return MODE_BANDWIDTH;
1609 } else if (mdev->type == G200_ER &&
1610 (mga_vga_calculate_mode_bandwidth(mode,
1611 bpp) > (55000 * 1024))) {
1612 return MODE_BANDWIDTH;
1615 if ((mode->hdisplay % 8) != 0 || (mode->hsync_start % 8) != 0 ||
1616 (mode->hsync_end % 8) != 0 || (mode->htotal % 8) != 0) {
1617 return MODE_H_ILLEGAL;
1620 if (mode->crtc_hdisplay > 2048 || mode->crtc_hsync_start > 4096 ||
1621 mode->crtc_hsync_end > 4096 || mode->crtc_htotal > 4096 ||
1622 mode->crtc_vdisplay > 2048 || mode->crtc_vsync_start > 4096 ||
1623 mode->crtc_vsync_end > 4096 || mode->crtc_vtotal > 4096) {
1627 /* Validate the mode input by the user */
1628 if (connector->cmdline_mode.specified) {
1629 if (connector->cmdline_mode.bpp_specified)
1630 bpp = connector->cmdline_mode.bpp;
1633 if ((mode->hdisplay * mode->vdisplay * (bpp/8)) > mdev->mc.vram_size) {
1634 if (connector->cmdline_mode.specified)
1635 connector->cmdline_mode.specified = false;
1642 static struct drm_encoder *mga_connector_best_encoder(struct drm_connector
1645 int enc_id = connector->encoder_ids[0];
1646 /* pick the encoder ids */
1648 return drm_encoder_find(connector->dev, enc_id);
1652 static enum drm_connector_status mga_vga_detect(struct drm_connector
1653 *connector, bool force)
1655 return connector_status_connected;
1658 static void mga_connector_destroy(struct drm_connector *connector)
1660 struct mga_connector *mga_connector = to_mga_connector(connector);
1661 mgag200_i2c_destroy(mga_connector->i2c);
1662 drm_connector_cleanup(connector);
1666 static const struct drm_connector_helper_funcs mga_vga_connector_helper_funcs = {
1667 .get_modes = mga_vga_get_modes,
1668 .mode_valid = mga_vga_mode_valid,
1669 .best_encoder = mga_connector_best_encoder,
1672 static const struct drm_connector_funcs mga_vga_connector_funcs = {
1673 .dpms = drm_helper_connector_dpms,
1674 .detect = mga_vga_detect,
1675 .fill_modes = drm_helper_probe_single_connector_modes,
1676 .destroy = mga_connector_destroy,
1679 static struct drm_connector *mga_vga_init(struct drm_device *dev)
1681 struct drm_connector *connector;
1682 struct mga_connector *mga_connector;
1684 mga_connector = kzalloc(sizeof(struct mga_connector), GFP_KERNEL);
1688 connector = &mga_connector->base;
1690 drm_connector_init(dev, connector,
1691 &mga_vga_connector_funcs, DRM_MODE_CONNECTOR_VGA);
1693 drm_connector_helper_add(connector, &mga_vga_connector_helper_funcs);
1695 drm_connector_register(connector);
1697 mga_connector->i2c = mgag200_i2c_create(dev);
1698 if (!mga_connector->i2c)
1699 DRM_ERROR("failed to add ddc bus\n");
1705 int mgag200_modeset_init(struct mga_device *mdev)
1707 struct drm_encoder *encoder;
1708 struct drm_connector *connector;
1711 mdev->mode_info.mode_config_initialized = true;
1713 mdev->dev->mode_config.max_width = MGAG200_MAX_FB_WIDTH;
1714 mdev->dev->mode_config.max_height = MGAG200_MAX_FB_HEIGHT;
1716 mdev->dev->mode_config.fb_base = mdev->mc.vram_base;
1718 mga_crtc_init(mdev);
1720 encoder = mga_encoder_init(mdev->dev);
1722 DRM_ERROR("mga_encoder_init failed\n");
1726 connector = mga_vga_init(mdev->dev);
1728 DRM_ERROR("mga_vga_init failed\n");
1732 drm_mode_connector_attach_encoder(connector, encoder);
1734 ret = mgag200_fbdev_init(mdev);
1736 DRM_ERROR("mga_fbdev_init failed\n");
1743 void mgag200_modeset_fini(struct mga_device *mdev)