2 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/clk.h>
15 #include <linux/delay.h>
16 #include <linux/err.h>
17 #include <linux/gpio.h>
18 #include <linux/gpio/consumer.h>
19 #include <linux/interrupt.h>
20 #include <linux/of_device.h>
21 #include <linux/of_gpio.h>
22 #include <linux/of_irq.h>
23 #include <linux/pinctrl/consumer.h>
24 #include <linux/of_graph.h>
25 #include <linux/regulator/consumer.h>
26 #include <linux/spinlock.h>
27 #include <video/mipi_display.h>
33 static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor)
41 /* From DSI6G(v3), addition of a 6G_HW_VERSION register at offset 0
42 * makes all other registers 4-byte shifted down.
44 ver_6g = msm_readl(base + REG_DSI_6G_HW_VERSION);
46 ver = msm_readl(base + REG_DSI_VERSION);
47 ver = FIELD(ver, DSI_VERSION_MAJOR);
48 if (ver <= MSM_DSI_VER_MAJOR_V2) {
57 ver = msm_readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION);
58 ver = FIELD(ver, DSI_VERSION_MAJOR);
59 if (ver == MSM_DSI_VER_MAJOR_6G) {
70 #define DSI_ERR_STATE_ACK 0x0000
71 #define DSI_ERR_STATE_TIMEOUT 0x0001
72 #define DSI_ERR_STATE_DLN0_PHY 0x0002
73 #define DSI_ERR_STATE_FIFO 0x0004
74 #define DSI_ERR_STATE_MDP_FIFO_UNDERFLOW 0x0008
75 #define DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION 0x0010
76 #define DSI_ERR_STATE_PLL_UNLOCKED 0x0020
78 #define DSI_CLK_CTRL_ENABLE_CLKS \
79 (DSI_CLK_CTRL_AHBS_HCLK_ON | DSI_CLK_CTRL_AHBM_SCLK_ON | \
80 DSI_CLK_CTRL_PCLK_ON | DSI_CLK_CTRL_DSICLK_ON | \
81 DSI_CLK_CTRL_BYTECLK_ON | DSI_CLK_CTRL_ESCCLK_ON | \
82 DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK)
85 struct mipi_dsi_host base;
87 struct platform_device *pdev;
88 struct drm_device *dev;
92 void __iomem *ctrl_base;
93 struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX];
94 struct clk *mdp_core_clk;
97 struct clk *mmss_misc_ahb_clk;
100 struct clk *pixel_clk;
101 struct clk *byte_clk_src;
102 struct clk *pixel_clk_src;
106 struct gpio_desc *disp_en_gpio;
107 struct gpio_desc *te_gpio;
109 const struct msm_dsi_cfg_handler *cfg_hnd;
111 struct completion dma_comp;
112 struct completion video_comp;
113 struct mutex dev_mutex;
114 struct mutex cmd_mutex;
115 struct mutex clk_mutex;
116 spinlock_t intr_lock; /* Protect interrupt ctrl register */
119 struct work_struct err_work;
120 struct workqueue_struct *workqueue;
122 struct drm_gem_object *tx_gem_obj;
125 struct drm_display_mode *mode;
127 /* connected device info */
128 struct device_node *device_node;
129 unsigned int channel;
131 enum mipi_dsi_pixel_format format;
132 unsigned long mode_flags;
134 u32 dma_cmd_ctrl_restore;
141 static u32 dsi_get_bpp(const enum mipi_dsi_pixel_format fmt)
144 case MIPI_DSI_FMT_RGB565: return 16;
145 case MIPI_DSI_FMT_RGB666_PACKED: return 18;
146 case MIPI_DSI_FMT_RGB666:
147 case MIPI_DSI_FMT_RGB888:
152 static inline u32 dsi_read(struct msm_dsi_host *msm_host, u32 reg)
154 return msm_readl(msm_host->ctrl_base + reg);
156 static inline void dsi_write(struct msm_dsi_host *msm_host, u32 reg, u32 data)
158 msm_writel(data, msm_host->ctrl_base + reg);
161 static int dsi_host_regulator_enable(struct msm_dsi_host *msm_host);
162 static void dsi_host_regulator_disable(struct msm_dsi_host *msm_host);
164 static const struct msm_dsi_cfg_handler *dsi_get_config(
165 struct msm_dsi_host *msm_host)
167 const struct msm_dsi_cfg_handler *cfg_hnd = NULL;
168 struct regulator *gdsc_reg;
170 u32 major = 0, minor = 0;
172 gdsc_reg = regulator_get(&msm_host->pdev->dev, "gdsc");
173 if (IS_ERR(gdsc_reg)) {
174 pr_err("%s: cannot get gdsc\n", __func__);
177 ret = regulator_enable(gdsc_reg);
179 pr_err("%s: unable to enable gdsc\n", __func__);
182 ret = clk_prepare_enable(msm_host->ahb_clk);
184 pr_err("%s: unable to enable ahb_clk\n", __func__);
188 ret = dsi_get_version(msm_host->ctrl_base, &major, &minor);
190 pr_err("%s: Invalid version\n", __func__);
194 cfg_hnd = msm_dsi_cfg_get(major, minor);
196 DBG("%s: Version %x:%x\n", __func__, major, minor);
199 clk_disable_unprepare(msm_host->ahb_clk);
201 regulator_disable(gdsc_reg);
203 regulator_put(gdsc_reg);
208 static inline struct msm_dsi_host *to_msm_dsi_host(struct mipi_dsi_host *host)
210 return container_of(host, struct msm_dsi_host, base);
213 static void dsi_host_regulator_disable(struct msm_dsi_host *msm_host)
215 struct regulator_bulk_data *s = msm_host->supplies;
216 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs;
217 int num = msm_host->cfg_hnd->cfg->reg_cfg.num;
221 for (i = num - 1; i >= 0; i--)
222 if (regs[i].disable_load >= 0)
223 regulator_set_load(s[i].consumer,
224 regs[i].disable_load);
226 regulator_bulk_disable(num, s);
229 static int dsi_host_regulator_enable(struct msm_dsi_host *msm_host)
231 struct regulator_bulk_data *s = msm_host->supplies;
232 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs;
233 int num = msm_host->cfg_hnd->cfg->reg_cfg.num;
237 for (i = 0; i < num; i++) {
238 if (regs[i].enable_load >= 0) {
239 ret = regulator_set_load(s[i].consumer,
240 regs[i].enable_load);
242 pr_err("regulator %d set op mode failed, %d\n",
249 ret = regulator_bulk_enable(num, s);
251 pr_err("regulator enable failed, %d\n", ret);
258 for (i--; i >= 0; i--)
259 regulator_set_load(s[i].consumer, regs[i].disable_load);
263 static int dsi_regulator_init(struct msm_dsi_host *msm_host)
265 struct regulator_bulk_data *s = msm_host->supplies;
266 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs;
267 int num = msm_host->cfg_hnd->cfg->reg_cfg.num;
270 for (i = 0; i < num; i++)
271 s[i].supply = regs[i].name;
273 ret = devm_regulator_bulk_get(&msm_host->pdev->dev, num, s);
275 pr_err("%s: failed to init regulator, ret=%d\n",
280 for (i = 0; i < num; i++) {
281 if (regulator_can_change_voltage(s[i].consumer)) {
282 ret = regulator_set_voltage(s[i].consumer,
283 regs[i].min_voltage, regs[i].max_voltage);
285 pr_err("regulator %d set voltage failed, %d\n",
295 static int dsi_clk_init(struct msm_dsi_host *msm_host)
297 struct device *dev = &msm_host->pdev->dev;
300 msm_host->mdp_core_clk = devm_clk_get(dev, "mdp_core_clk");
301 if (IS_ERR(msm_host->mdp_core_clk)) {
302 ret = PTR_ERR(msm_host->mdp_core_clk);
303 pr_err("%s: Unable to get mdp core clk. ret=%d\n",
308 msm_host->ahb_clk = devm_clk_get(dev, "iface_clk");
309 if (IS_ERR(msm_host->ahb_clk)) {
310 ret = PTR_ERR(msm_host->ahb_clk);
311 pr_err("%s: Unable to get mdss ahb clk. ret=%d\n",
316 msm_host->axi_clk = devm_clk_get(dev, "bus_clk");
317 if (IS_ERR(msm_host->axi_clk)) {
318 ret = PTR_ERR(msm_host->axi_clk);
319 pr_err("%s: Unable to get axi bus clk. ret=%d\n",
324 msm_host->mmss_misc_ahb_clk = devm_clk_get(dev, "core_mmss_clk");
325 if (IS_ERR(msm_host->mmss_misc_ahb_clk)) {
326 ret = PTR_ERR(msm_host->mmss_misc_ahb_clk);
327 pr_err("%s: Unable to get mmss misc ahb clk. ret=%d\n",
332 msm_host->byte_clk = devm_clk_get(dev, "byte_clk");
333 if (IS_ERR(msm_host->byte_clk)) {
334 ret = PTR_ERR(msm_host->byte_clk);
335 pr_err("%s: can't find dsi_byte_clk. ret=%d\n",
337 msm_host->byte_clk = NULL;
341 msm_host->pixel_clk = devm_clk_get(dev, "pixel_clk");
342 if (IS_ERR(msm_host->pixel_clk)) {
343 ret = PTR_ERR(msm_host->pixel_clk);
344 pr_err("%s: can't find dsi_pixel_clk. ret=%d\n",
346 msm_host->pixel_clk = NULL;
350 msm_host->esc_clk = devm_clk_get(dev, "core_clk");
351 if (IS_ERR(msm_host->esc_clk)) {
352 ret = PTR_ERR(msm_host->esc_clk);
353 pr_err("%s: can't find dsi_esc_clk. ret=%d\n",
355 msm_host->esc_clk = NULL;
359 msm_host->byte_clk_src = clk_get_parent(msm_host->byte_clk);
360 if (!msm_host->byte_clk_src) {
362 pr_err("%s: can't find byte_clk_src. ret=%d\n", __func__, ret);
366 msm_host->pixel_clk_src = clk_get_parent(msm_host->pixel_clk);
367 if (!msm_host->pixel_clk_src) {
369 pr_err("%s: can't find pixel_clk_src. ret=%d\n", __func__, ret);
376 static int dsi_bus_clk_enable(struct msm_dsi_host *msm_host)
380 DBG("id=%d", msm_host->id);
382 ret = clk_prepare_enable(msm_host->mdp_core_clk);
384 pr_err("%s: failed to enable mdp_core_clock, %d\n",
389 ret = clk_prepare_enable(msm_host->ahb_clk);
391 pr_err("%s: failed to enable ahb clock, %d\n", __func__, ret);
395 ret = clk_prepare_enable(msm_host->axi_clk);
397 pr_err("%s: failed to enable ahb clock, %d\n", __func__, ret);
401 ret = clk_prepare_enable(msm_host->mmss_misc_ahb_clk);
403 pr_err("%s: failed to enable mmss misc ahb clk, %d\n",
405 goto misc_ahb_clk_err;
411 clk_disable_unprepare(msm_host->axi_clk);
413 clk_disable_unprepare(msm_host->ahb_clk);
415 clk_disable_unprepare(msm_host->mdp_core_clk);
420 static void dsi_bus_clk_disable(struct msm_dsi_host *msm_host)
423 clk_disable_unprepare(msm_host->mmss_misc_ahb_clk);
424 clk_disable_unprepare(msm_host->axi_clk);
425 clk_disable_unprepare(msm_host->ahb_clk);
426 clk_disable_unprepare(msm_host->mdp_core_clk);
429 static int dsi_link_clk_enable(struct msm_dsi_host *msm_host)
433 DBG("Set clk rates: pclk=%d, byteclk=%d",
434 msm_host->mode->clock, msm_host->byte_clk_rate);
436 ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate);
438 pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret);
442 ret = clk_set_rate(msm_host->pixel_clk, msm_host->mode->clock * 1000);
444 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret);
448 ret = clk_prepare_enable(msm_host->esc_clk);
450 pr_err("%s: Failed to enable dsi esc clk\n", __func__);
454 ret = clk_prepare_enable(msm_host->byte_clk);
456 pr_err("%s: Failed to enable dsi byte clk\n", __func__);
460 ret = clk_prepare_enable(msm_host->pixel_clk);
462 pr_err("%s: Failed to enable dsi pixel clk\n", __func__);
469 clk_disable_unprepare(msm_host->byte_clk);
471 clk_disable_unprepare(msm_host->esc_clk);
476 static void dsi_link_clk_disable(struct msm_dsi_host *msm_host)
478 clk_disable_unprepare(msm_host->esc_clk);
479 clk_disable_unprepare(msm_host->pixel_clk);
480 clk_disable_unprepare(msm_host->byte_clk);
483 static int dsi_clk_ctrl(struct msm_dsi_host *msm_host, bool enable)
487 mutex_lock(&msm_host->clk_mutex);
489 ret = dsi_bus_clk_enable(msm_host);
491 pr_err("%s: Can not enable bus clk, %d\n",
495 ret = dsi_link_clk_enable(msm_host);
497 pr_err("%s: Can not enable link clk, %d\n",
499 dsi_bus_clk_disable(msm_host);
503 dsi_link_clk_disable(msm_host);
504 dsi_bus_clk_disable(msm_host);
508 mutex_unlock(&msm_host->clk_mutex);
512 static int dsi_calc_clk_rate(struct msm_dsi_host *msm_host)
514 struct drm_display_mode *mode = msm_host->mode;
515 u8 lanes = msm_host->lanes;
516 u32 bpp = dsi_get_bpp(msm_host->format);
520 pr_err("%s: mode not set\n", __func__);
524 pclk_rate = mode->clock * 1000;
526 msm_host->byte_clk_rate = (pclk_rate * bpp) / (8 * lanes);
528 pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__);
529 msm_host->byte_clk_rate = (pclk_rate * bpp) / 8;
532 DBG("pclk=%d, bclk=%d", pclk_rate, msm_host->byte_clk_rate);
537 static void dsi_phy_sw_reset(struct msm_dsi_host *msm_host)
540 dsi_write(msm_host, REG_DSI_PHY_RESET, DSI_PHY_RESET_RESET);
541 /* Make sure fully reset */
544 dsi_write(msm_host, REG_DSI_PHY_RESET, 0);
548 static void dsi_intr_ctrl(struct msm_dsi_host *msm_host, u32 mask, int enable)
553 spin_lock_irqsave(&msm_host->intr_lock, flags);
554 intr = dsi_read(msm_host, REG_DSI_INTR_CTRL);
561 DBG("intr=%x enable=%d", intr, enable);
563 dsi_write(msm_host, REG_DSI_INTR_CTRL, intr);
564 spin_unlock_irqrestore(&msm_host->intr_lock, flags);
567 static inline enum dsi_traffic_mode dsi_get_traffic_mode(const u32 mode_flags)
569 if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
571 else if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
572 return NON_BURST_SYNCH_PULSE;
574 return NON_BURST_SYNCH_EVENT;
577 static inline enum dsi_vid_dst_format dsi_get_vid_fmt(
578 const enum mipi_dsi_pixel_format mipi_fmt)
581 case MIPI_DSI_FMT_RGB888: return VID_DST_FORMAT_RGB888;
582 case MIPI_DSI_FMT_RGB666: return VID_DST_FORMAT_RGB666_LOOSE;
583 case MIPI_DSI_FMT_RGB666_PACKED: return VID_DST_FORMAT_RGB666;
584 case MIPI_DSI_FMT_RGB565: return VID_DST_FORMAT_RGB565;
585 default: return VID_DST_FORMAT_RGB888;
589 static inline enum dsi_cmd_dst_format dsi_get_cmd_fmt(
590 const enum mipi_dsi_pixel_format mipi_fmt)
593 case MIPI_DSI_FMT_RGB888: return CMD_DST_FORMAT_RGB888;
594 case MIPI_DSI_FMT_RGB666_PACKED:
595 case MIPI_DSI_FMT_RGB666: return VID_DST_FORMAT_RGB666;
596 case MIPI_DSI_FMT_RGB565: return CMD_DST_FORMAT_RGB565;
597 default: return CMD_DST_FORMAT_RGB888;
601 static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable,
602 u32 clk_pre, u32 clk_post)
604 u32 flags = msm_host->mode_flags;
605 enum mipi_dsi_pixel_format mipi_fmt = msm_host->format;
606 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
610 dsi_write(msm_host, REG_DSI_CTRL, 0);
614 if (flags & MIPI_DSI_MODE_VIDEO) {
615 if (flags & MIPI_DSI_MODE_VIDEO_HSE)
616 data |= DSI_VID_CFG0_PULSE_MODE_HSA_HE;
617 if (flags & MIPI_DSI_MODE_VIDEO_HFP)
618 data |= DSI_VID_CFG0_HFP_POWER_STOP;
619 if (flags & MIPI_DSI_MODE_VIDEO_HBP)
620 data |= DSI_VID_CFG0_HBP_POWER_STOP;
621 if (flags & MIPI_DSI_MODE_VIDEO_HSA)
622 data |= DSI_VID_CFG0_HSA_POWER_STOP;
623 /* Always set low power stop mode for BLLP
624 * to let command engine send packets
626 data |= DSI_VID_CFG0_EOF_BLLP_POWER_STOP |
627 DSI_VID_CFG0_BLLP_POWER_STOP;
628 data |= DSI_VID_CFG0_TRAFFIC_MODE(dsi_get_traffic_mode(flags));
629 data |= DSI_VID_CFG0_DST_FORMAT(dsi_get_vid_fmt(mipi_fmt));
630 data |= DSI_VID_CFG0_VIRT_CHANNEL(msm_host->channel);
631 dsi_write(msm_host, REG_DSI_VID_CFG0, data);
633 /* Do not swap RGB colors */
634 data = DSI_VID_CFG1_RGB_SWAP(SWAP_RGB);
635 dsi_write(msm_host, REG_DSI_VID_CFG1, 0);
637 /* Do not swap RGB colors */
638 data = DSI_CMD_CFG0_RGB_SWAP(SWAP_RGB);
639 data |= DSI_CMD_CFG0_DST_FORMAT(dsi_get_cmd_fmt(mipi_fmt));
640 dsi_write(msm_host, REG_DSI_CMD_CFG0, data);
642 data = DSI_CMD_CFG1_WR_MEM_START(MIPI_DCS_WRITE_MEMORY_START) |
643 DSI_CMD_CFG1_WR_MEM_CONTINUE(
644 MIPI_DCS_WRITE_MEMORY_CONTINUE);
645 /* Always insert DCS command */
646 data |= DSI_CMD_CFG1_INSERT_DCS_COMMAND;
647 dsi_write(msm_host, REG_DSI_CMD_CFG1, data);
650 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL,
651 DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER |
652 DSI_CMD_DMA_CTRL_LOW_POWER);
655 /* Always assume dedicated TE pin */
656 data |= DSI_TRIG_CTRL_TE;
657 data |= DSI_TRIG_CTRL_MDP_TRIGGER(TRIGGER_NONE);
658 data |= DSI_TRIG_CTRL_DMA_TRIGGER(TRIGGER_SW);
659 data |= DSI_TRIG_CTRL_STREAM(msm_host->channel);
660 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) &&
661 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_2))
662 data |= DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME;
663 dsi_write(msm_host, REG_DSI_TRIG_CTRL, data);
665 data = DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(clk_post) |
666 DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(clk_pre);
667 dsi_write(msm_host, REG_DSI_CLKOUT_TIMING_CTRL, data);
670 if (!(flags & MIPI_DSI_MODE_EOT_PACKET))
671 data |= DSI_EOT_PACKET_CTRL_TX_EOT_APPEND;
672 dsi_write(msm_host, REG_DSI_EOT_PACKET_CTRL, data);
674 /* allow only ack-err-status to generate interrupt */
675 dsi_write(msm_host, REG_DSI_ERR_INT_MASK0, 0x13ff3fe0);
677 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1);
679 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
681 data = DSI_CTRL_CLK_EN;
683 DBG("lane number=%d", msm_host->lanes);
684 if (msm_host->lanes == 2) {
685 data |= DSI_CTRL_LANE1 | DSI_CTRL_LANE2;
686 /* swap lanes for 2-lane panel for better performance */
687 dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL,
688 DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(LANE_SWAP_1230));
690 /* Take 4 lanes as default */
691 data |= DSI_CTRL_LANE0 | DSI_CTRL_LANE1 | DSI_CTRL_LANE2 |
693 /* Do not swap lanes for 4-lane panel */
694 dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL,
695 DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(LANE_SWAP_0123));
698 if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
699 dsi_write(msm_host, REG_DSI_LANE_CTRL,
700 DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST);
702 data |= DSI_CTRL_ENABLE;
704 dsi_write(msm_host, REG_DSI_CTRL, data);
707 static void dsi_timing_setup(struct msm_dsi_host *msm_host)
709 struct drm_display_mode *mode = msm_host->mode;
710 u32 hs_start = 0, vs_start = 0; /* take sync start as 0 */
711 u32 h_total = mode->htotal;
712 u32 v_total = mode->vtotal;
713 u32 hs_end = mode->hsync_end - mode->hsync_start;
714 u32 vs_end = mode->vsync_end - mode->vsync_start;
715 u32 ha_start = h_total - mode->hsync_start;
716 u32 ha_end = ha_start + mode->hdisplay;
717 u32 va_start = v_total - mode->vsync_start;
718 u32 va_end = va_start + mode->vdisplay;
723 if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) {
724 dsi_write(msm_host, REG_DSI_ACTIVE_H,
725 DSI_ACTIVE_H_START(ha_start) |
726 DSI_ACTIVE_H_END(ha_end));
727 dsi_write(msm_host, REG_DSI_ACTIVE_V,
728 DSI_ACTIVE_V_START(va_start) |
729 DSI_ACTIVE_V_END(va_end));
730 dsi_write(msm_host, REG_DSI_TOTAL,
731 DSI_TOTAL_H_TOTAL(h_total - 1) |
732 DSI_TOTAL_V_TOTAL(v_total - 1));
734 dsi_write(msm_host, REG_DSI_ACTIVE_HSYNC,
735 DSI_ACTIVE_HSYNC_START(hs_start) |
736 DSI_ACTIVE_HSYNC_END(hs_end));
737 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_HPOS, 0);
738 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_VPOS,
739 DSI_ACTIVE_VSYNC_VPOS_START(vs_start) |
740 DSI_ACTIVE_VSYNC_VPOS_END(vs_end));
741 } else { /* command mode */
742 /* image data and 1 byte write_memory_start cmd */
743 wc = mode->hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1;
745 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM_CTRL,
746 DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT(wc) |
747 DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL(
749 DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE(
750 MIPI_DSI_DCS_LONG_WRITE));
752 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM_TOTAL,
753 DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL(mode->hdisplay) |
754 DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL(mode->vdisplay));
758 static void dsi_sw_reset(struct msm_dsi_host *msm_host)
760 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
761 wmb(); /* clocks need to be enabled before reset */
763 dsi_write(msm_host, REG_DSI_RESET, 1);
764 wmb(); /* make sure reset happen */
765 dsi_write(msm_host, REG_DSI_RESET, 0);
768 static void dsi_op_mode_config(struct msm_dsi_host *msm_host,
769 bool video_mode, bool enable)
773 dsi_ctrl = dsi_read(msm_host, REG_DSI_CTRL);
776 dsi_ctrl &= ~(DSI_CTRL_ENABLE | DSI_CTRL_VID_MODE_EN |
777 DSI_CTRL_CMD_MODE_EN);
778 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE |
779 DSI_IRQ_MASK_VIDEO_DONE, 0);
782 dsi_ctrl |= DSI_CTRL_VID_MODE_EN;
783 } else { /* command mode */
784 dsi_ctrl |= DSI_CTRL_CMD_MODE_EN;
785 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE, 1);
787 dsi_ctrl |= DSI_CTRL_ENABLE;
790 dsi_write(msm_host, REG_DSI_CTRL, dsi_ctrl);
793 static void dsi_set_tx_power_mode(int mode, struct msm_dsi_host *msm_host)
797 data = dsi_read(msm_host, REG_DSI_CMD_DMA_CTRL);
800 data &= ~DSI_CMD_DMA_CTRL_LOW_POWER;
802 data |= DSI_CMD_DMA_CTRL_LOW_POWER;
804 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, data);
807 static void dsi_wait4video_done(struct msm_dsi_host *msm_host)
809 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 1);
811 reinit_completion(&msm_host->video_comp);
813 wait_for_completion_timeout(&msm_host->video_comp,
814 msecs_to_jiffies(70));
816 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 0);
819 static void dsi_wait4video_eng_busy(struct msm_dsi_host *msm_host)
821 if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO))
824 if (msm_host->power_on) {
825 dsi_wait4video_done(msm_host);
826 /* delay 4 ms to skip BLLP */
827 usleep_range(2000, 4000);
832 static int dsi_tx_buf_alloc(struct msm_dsi_host *msm_host, int size)
834 struct drm_device *dev = msm_host->dev;
838 mutex_lock(&dev->struct_mutex);
839 msm_host->tx_gem_obj = msm_gem_new(dev, size, MSM_BO_UNCACHED);
840 if (IS_ERR(msm_host->tx_gem_obj)) {
841 ret = PTR_ERR(msm_host->tx_gem_obj);
842 pr_err("%s: failed to allocate gem, %d\n", __func__, ret);
843 msm_host->tx_gem_obj = NULL;
844 mutex_unlock(&dev->struct_mutex);
848 ret = msm_gem_get_iova_locked(msm_host->tx_gem_obj, 0, &iova);
850 pr_err("%s: failed to get iova, %d\n", __func__, ret);
853 mutex_unlock(&dev->struct_mutex);
856 pr_err("%s: buf NOT 8 bytes aligned\n", __func__);
863 static void dsi_tx_buf_free(struct msm_dsi_host *msm_host)
865 struct drm_device *dev = msm_host->dev;
867 if (msm_host->tx_gem_obj) {
868 msm_gem_put_iova(msm_host->tx_gem_obj, 0);
869 mutex_lock(&dev->struct_mutex);
870 msm_gem_free_object(msm_host->tx_gem_obj);
871 msm_host->tx_gem_obj = NULL;
872 mutex_unlock(&dev->struct_mutex);
877 * prepare cmd buffer to be txed
879 static int dsi_cmd_dma_add(struct drm_gem_object *tx_gem,
880 const struct mipi_dsi_msg *msg)
882 struct mipi_dsi_packet packet;
887 ret = mipi_dsi_create_packet(&packet, msg);
889 pr_err("%s: create packet failed, %d\n", __func__, ret);
892 len = (packet.size + 3) & (~0x3);
894 if (len > tx_gem->size) {
895 pr_err("%s: packet size is too big\n", __func__);
899 data = msm_gem_vaddr(tx_gem);
903 pr_err("%s: get vaddr failed, %d\n", __func__, ret);
907 /* MSM specific command format in memory */
908 data[0] = packet.header[1];
909 data[1] = packet.header[2];
910 data[2] = packet.header[0];
911 data[3] = BIT(7); /* Last packet */
912 if (mipi_dsi_packet_format_is_long(msg->type))
914 if (msg->rx_buf && msg->rx_len)
918 if (packet.payload && packet.payload_length)
919 memcpy(data + 4, packet.payload, packet.payload_length);
921 /* Append 0xff to the end */
922 if (packet.size < len)
923 memset(data + packet.size, 0xff, len - packet.size);
929 * dsi_short_read1_resp: 1 parameter
931 static int dsi_short_read1_resp(u8 *buf, const struct mipi_dsi_msg *msg)
933 u8 *data = msg->rx_buf;
934 if (data && (msg->rx_len >= 1)) {
935 *data = buf[1]; /* strip out dcs type */
938 pr_err("%s: read data does not match with rx_buf len %zu\n",
939 __func__, msg->rx_len);
945 * dsi_short_read2_resp: 2 parameter
947 static int dsi_short_read2_resp(u8 *buf, const struct mipi_dsi_msg *msg)
949 u8 *data = msg->rx_buf;
950 if (data && (msg->rx_len >= 2)) {
951 data[0] = buf[1]; /* strip out dcs type */
955 pr_err("%s: read data does not match with rx_buf len %zu\n",
956 __func__, msg->rx_len);
961 static int dsi_long_read_resp(u8 *buf, const struct mipi_dsi_msg *msg)
963 /* strip out 4 byte dcs header */
964 if (msg->rx_buf && msg->rx_len)
965 memcpy(msg->rx_buf, buf + 4, msg->rx_len);
971 static int dsi_cmd_dma_tx(struct msm_dsi_host *msm_host, int len)
977 ret = msm_gem_get_iova(msm_host->tx_gem_obj, 0, &iova);
979 pr_err("%s: failed to get iova: %d\n", __func__, ret);
983 reinit_completion(&msm_host->dma_comp);
985 dsi_wait4video_eng_busy(msm_host);
987 triggered = msm_dsi_manager_cmd_xfer_trigger(
988 msm_host->id, iova, len);
990 ret = wait_for_completion_timeout(&msm_host->dma_comp,
991 msecs_to_jiffies(200));
1003 static int dsi_cmd_dma_rx(struct msm_dsi_host *msm_host,
1004 u8 *buf, int rx_byte, int pkt_size)
1006 u32 *lp, *temp, data;
1010 int repeated_bytes = 0;
1011 int buf_offset = buf - msm_host->rx_buf;
1015 cnt = (rx_byte + 3) >> 2;
1017 cnt = 4; /* 4 x 32 bits registers only */
1022 read_cnt = pkt_size + 6;
1025 * In case of multiple reads from the panel, after the first read, there
1026 * is possibility that there are some bytes in the payload repeating in
1027 * the RDBK_DATA registers. Since we read all the parameters from the
1028 * panel right from the first byte for every pass. We need to skip the
1029 * repeating bytes and then append the new parameters to the rx buffer.
1031 if (read_cnt > 16) {
1033 /* Any data more than 16 bytes will be shifted out.
1034 * The temp read buffer should already contain these bytes.
1035 * The remaining bytes in read buffer are the repeated bytes.
1037 bytes_shifted = read_cnt - 16;
1038 repeated_bytes = buf_offset - bytes_shifted;
1041 for (i = cnt - 1; i >= 0; i--) {
1042 data = dsi_read(msm_host, REG_DSI_RDBK_DATA(i));
1043 *temp++ = ntohl(data); /* to host byte order */
1044 DBG("data = 0x%x and ntohl(data) = 0x%x", data, ntohl(data));
1047 for (i = repeated_bytes; i < 16; i++)
1053 static int dsi_cmds2buf_tx(struct msm_dsi_host *msm_host,
1054 const struct mipi_dsi_msg *msg)
1057 int bllp_len = msm_host->mode->hdisplay *
1058 dsi_get_bpp(msm_host->format) / 8;
1060 len = dsi_cmd_dma_add(msm_host->tx_gem_obj, msg);
1062 pr_err("%s: failed to add cmd type = 0x%x\n",
1063 __func__, msg->type);
1067 /* for video mode, do not send cmds more than
1068 * one pixel line, since it only transmit it
1071 /* TODO: if the command is sent in LP mode, the bit rate is only
1072 * half of esc clk rate. In this case, if the video is already
1073 * actively streaming, we need to check more carefully if the
1074 * command can be fit into one BLLP.
1076 if ((msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) && (len > bllp_len)) {
1077 pr_err("%s: cmd cannot fit into BLLP period, len=%d\n",
1082 ret = dsi_cmd_dma_tx(msm_host, len);
1084 pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, len=%d\n",
1085 __func__, msg->type, (*(u8 *)(msg->tx_buf)), len);
1092 static void dsi_sw_reset_restore(struct msm_dsi_host *msm_host)
1096 data0 = dsi_read(msm_host, REG_DSI_CTRL);
1098 data1 &= ~DSI_CTRL_ENABLE;
1099 dsi_write(msm_host, REG_DSI_CTRL, data1);
1101 * dsi controller need to be disabled before
1106 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
1107 wmb(); /* make sure clocks enabled */
1109 /* dsi controller can only be reset while clocks are running */
1110 dsi_write(msm_host, REG_DSI_RESET, 1);
1111 wmb(); /* make sure reset happen */
1112 dsi_write(msm_host, REG_DSI_RESET, 0);
1113 wmb(); /* controller out of reset */
1114 dsi_write(msm_host, REG_DSI_CTRL, data0);
1115 wmb(); /* make sure dsi controller enabled again */
1118 static void dsi_err_worker(struct work_struct *work)
1120 struct msm_dsi_host *msm_host =
1121 container_of(work, struct msm_dsi_host, err_work);
1122 u32 status = msm_host->err_work_state;
1124 pr_err_ratelimited("%s: status=%x\n", __func__, status);
1125 if (status & DSI_ERR_STATE_MDP_FIFO_UNDERFLOW)
1126 dsi_sw_reset_restore(msm_host);
1128 /* It is safe to clear here because error irq is disabled. */
1129 msm_host->err_work_state = 0;
1131 /* enable dsi error interrupt */
1132 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1);
1135 static void dsi_ack_err_status(struct msm_dsi_host *msm_host)
1139 status = dsi_read(msm_host, REG_DSI_ACK_ERR_STATUS);
1142 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, status);
1143 /* Writing of an extra 0 needed to clear error bits */
1144 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, 0);
1145 msm_host->err_work_state |= DSI_ERR_STATE_ACK;
1149 static void dsi_timeout_status(struct msm_dsi_host *msm_host)
1153 status = dsi_read(msm_host, REG_DSI_TIMEOUT_STATUS);
1156 dsi_write(msm_host, REG_DSI_TIMEOUT_STATUS, status);
1157 msm_host->err_work_state |= DSI_ERR_STATE_TIMEOUT;
1161 static void dsi_dln0_phy_err(struct msm_dsi_host *msm_host)
1165 status = dsi_read(msm_host, REG_DSI_DLN0_PHY_ERR);
1167 if (status & (DSI_DLN0_PHY_ERR_DLN0_ERR_ESC |
1168 DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC |
1169 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL |
1170 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 |
1171 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1)) {
1172 dsi_write(msm_host, REG_DSI_DLN0_PHY_ERR, status);
1173 msm_host->err_work_state |= DSI_ERR_STATE_DLN0_PHY;
1177 static void dsi_fifo_status(struct msm_dsi_host *msm_host)
1181 status = dsi_read(msm_host, REG_DSI_FIFO_STATUS);
1183 /* fifo underflow, overflow */
1185 dsi_write(msm_host, REG_DSI_FIFO_STATUS, status);
1186 msm_host->err_work_state |= DSI_ERR_STATE_FIFO;
1187 if (status & DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW)
1188 msm_host->err_work_state |=
1189 DSI_ERR_STATE_MDP_FIFO_UNDERFLOW;
1193 static void dsi_status(struct msm_dsi_host *msm_host)
1197 status = dsi_read(msm_host, REG_DSI_STATUS0);
1199 if (status & DSI_STATUS0_INTERLEAVE_OP_CONTENTION) {
1200 dsi_write(msm_host, REG_DSI_STATUS0, status);
1201 msm_host->err_work_state |=
1202 DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION;
1206 static void dsi_clk_status(struct msm_dsi_host *msm_host)
1210 status = dsi_read(msm_host, REG_DSI_CLK_STATUS);
1212 if (status & DSI_CLK_STATUS_PLL_UNLOCKED) {
1213 dsi_write(msm_host, REG_DSI_CLK_STATUS, status);
1214 msm_host->err_work_state |= DSI_ERR_STATE_PLL_UNLOCKED;
1218 static void dsi_error(struct msm_dsi_host *msm_host)
1220 /* disable dsi error interrupt */
1221 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 0);
1223 dsi_clk_status(msm_host);
1224 dsi_fifo_status(msm_host);
1225 dsi_ack_err_status(msm_host);
1226 dsi_timeout_status(msm_host);
1227 dsi_status(msm_host);
1228 dsi_dln0_phy_err(msm_host);
1230 queue_work(msm_host->workqueue, &msm_host->err_work);
1233 static irqreturn_t dsi_host_irq(int irq, void *ptr)
1235 struct msm_dsi_host *msm_host = ptr;
1237 unsigned long flags;
1239 if (!msm_host->ctrl_base)
1242 spin_lock_irqsave(&msm_host->intr_lock, flags);
1243 isr = dsi_read(msm_host, REG_DSI_INTR_CTRL);
1244 dsi_write(msm_host, REG_DSI_INTR_CTRL, isr);
1245 spin_unlock_irqrestore(&msm_host->intr_lock, flags);
1247 DBG("isr=0x%x, id=%d", isr, msm_host->id);
1249 if (isr & DSI_IRQ_ERROR)
1250 dsi_error(msm_host);
1252 if (isr & DSI_IRQ_VIDEO_DONE)
1253 complete(&msm_host->video_comp);
1255 if (isr & DSI_IRQ_CMD_DMA_DONE)
1256 complete(&msm_host->dma_comp);
1261 static int dsi_host_init_panel_gpios(struct msm_dsi_host *msm_host,
1262 struct device *panel_device)
1264 msm_host->disp_en_gpio = devm_gpiod_get_optional(panel_device,
1267 if (IS_ERR(msm_host->disp_en_gpio)) {
1268 DBG("cannot get disp-enable-gpios %ld",
1269 PTR_ERR(msm_host->disp_en_gpio));
1270 return PTR_ERR(msm_host->disp_en_gpio);
1273 msm_host->te_gpio = devm_gpiod_get_optional(panel_device, "disp-te",
1275 if (IS_ERR(msm_host->te_gpio)) {
1276 DBG("cannot get disp-te-gpios %ld", PTR_ERR(msm_host->te_gpio));
1277 return PTR_ERR(msm_host->te_gpio);
1283 static int dsi_host_attach(struct mipi_dsi_host *host,
1284 struct mipi_dsi_device *dsi)
1286 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1289 msm_host->channel = dsi->channel;
1290 msm_host->lanes = dsi->lanes;
1291 msm_host->format = dsi->format;
1292 msm_host->mode_flags = dsi->mode_flags;
1294 WARN_ON(dsi->dev.of_node != msm_host->device_node);
1296 /* Some gpios defined in panel DT need to be controlled by host */
1297 ret = dsi_host_init_panel_gpios(msm_host, &dsi->dev);
1301 DBG("id=%d", msm_host->id);
1303 drm_helper_hpd_irq_event(msm_host->dev);
1308 static int dsi_host_detach(struct mipi_dsi_host *host,
1309 struct mipi_dsi_device *dsi)
1311 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1313 msm_host->device_node = NULL;
1315 DBG("id=%d", msm_host->id);
1317 drm_helper_hpd_irq_event(msm_host->dev);
1322 static ssize_t dsi_host_transfer(struct mipi_dsi_host *host,
1323 const struct mipi_dsi_msg *msg)
1325 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1328 if (!msg || !msm_host->power_on)
1331 mutex_lock(&msm_host->cmd_mutex);
1332 ret = msm_dsi_manager_cmd_xfer(msm_host->id, msg);
1333 mutex_unlock(&msm_host->cmd_mutex);
1338 static struct mipi_dsi_host_ops dsi_host_ops = {
1339 .attach = dsi_host_attach,
1340 .detach = dsi_host_detach,
1341 .transfer = dsi_host_transfer,
1344 static int dsi_host_parse_dt(struct msm_dsi_host *msm_host)
1346 struct device *dev = &msm_host->pdev->dev;
1347 struct device_node *np = dev->of_node;
1348 struct device_node *endpoint, *device_node;
1351 ret = of_property_read_u32(np, "qcom,dsi-host-index", &msm_host->id);
1353 dev_err(dev, "%s: host index not specified, ret=%d\n",
1359 * Get the first endpoint node. In our case, dsi has one output port
1360 * to which the panel is connected. Don't return an error if a port
1361 * isn't defined. It's possible that there is nothing connected to
1364 endpoint = of_graph_get_next_endpoint(np, NULL);
1366 dev_dbg(dev, "%s: no endpoint\n", __func__);
1370 /* Get panel node from the output port's endpoint data */
1371 device_node = of_graph_get_remote_port_parent(endpoint);
1373 dev_err(dev, "%s: no valid device\n", __func__);
1374 of_node_put(endpoint);
1378 of_node_put(endpoint);
1379 of_node_put(device_node);
1381 msm_host->device_node = device_node;
1386 int msm_dsi_host_init(struct msm_dsi *msm_dsi)
1388 struct msm_dsi_host *msm_host = NULL;
1389 struct platform_device *pdev = msm_dsi->pdev;
1392 msm_host = devm_kzalloc(&pdev->dev, sizeof(*msm_host), GFP_KERNEL);
1394 pr_err("%s: FAILED: cannot alloc dsi host\n",
1400 msm_host->pdev = pdev;
1402 ret = dsi_host_parse_dt(msm_host);
1404 pr_err("%s: failed to parse dt\n", __func__);
1408 ret = dsi_clk_init(msm_host);
1410 pr_err("%s: unable to initialize dsi clks\n", __func__);
1414 msm_host->ctrl_base = msm_ioremap(pdev, "dsi_ctrl", "DSI CTRL");
1415 if (IS_ERR(msm_host->ctrl_base)) {
1416 pr_err("%s: unable to map Dsi ctrl base\n", __func__);
1417 ret = PTR_ERR(msm_host->ctrl_base);
1421 msm_host->cfg_hnd = dsi_get_config(msm_host);
1422 if (!msm_host->cfg_hnd) {
1424 pr_err("%s: get config failed\n", __func__);
1428 /* fixup base address by io offset */
1429 msm_host->ctrl_base += msm_host->cfg_hnd->cfg->io_offset;
1431 ret = dsi_regulator_init(msm_host);
1433 pr_err("%s: regulator init failed\n", __func__);
1437 msm_host->rx_buf = devm_kzalloc(&pdev->dev, SZ_4K, GFP_KERNEL);
1438 if (!msm_host->rx_buf) {
1439 pr_err("%s: alloc rx temp buf failed\n", __func__);
1443 init_completion(&msm_host->dma_comp);
1444 init_completion(&msm_host->video_comp);
1445 mutex_init(&msm_host->dev_mutex);
1446 mutex_init(&msm_host->cmd_mutex);
1447 mutex_init(&msm_host->clk_mutex);
1448 spin_lock_init(&msm_host->intr_lock);
1450 /* setup workqueue */
1451 msm_host->workqueue = alloc_ordered_workqueue("dsi_drm_work", 0);
1452 INIT_WORK(&msm_host->err_work, dsi_err_worker);
1454 msm_dsi->host = &msm_host->base;
1455 msm_dsi->id = msm_host->id;
1457 DBG("Dsi Host %d initialized", msm_host->id);
1464 void msm_dsi_host_destroy(struct mipi_dsi_host *host)
1466 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1469 dsi_tx_buf_free(msm_host);
1470 if (msm_host->workqueue) {
1471 flush_workqueue(msm_host->workqueue);
1472 destroy_workqueue(msm_host->workqueue);
1473 msm_host->workqueue = NULL;
1476 mutex_destroy(&msm_host->clk_mutex);
1477 mutex_destroy(&msm_host->cmd_mutex);
1478 mutex_destroy(&msm_host->dev_mutex);
1481 int msm_dsi_host_modeset_init(struct mipi_dsi_host *host,
1482 struct drm_device *dev)
1484 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1485 struct platform_device *pdev = msm_host->pdev;
1488 msm_host->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
1489 if (msm_host->irq < 0) {
1490 ret = msm_host->irq;
1491 dev_err(dev->dev, "failed to get irq: %d\n", ret);
1495 ret = devm_request_irq(&pdev->dev, msm_host->irq,
1496 dsi_host_irq, IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
1497 "dsi_isr", msm_host);
1499 dev_err(&pdev->dev, "failed to request IRQ%u: %d\n",
1500 msm_host->irq, ret);
1504 msm_host->dev = dev;
1505 ret = dsi_tx_buf_alloc(msm_host, SZ_4K);
1507 pr_err("%s: alloc tx gem obj failed, %d\n", __func__, ret);
1514 int msm_dsi_host_register(struct mipi_dsi_host *host, bool check_defer)
1516 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1519 /* Register mipi dsi host */
1520 if (!msm_host->registered) {
1521 host->dev = &msm_host->pdev->dev;
1522 host->ops = &dsi_host_ops;
1523 ret = mipi_dsi_host_register(host);
1527 msm_host->registered = true;
1529 /* If the panel driver has not been probed after host register,
1530 * we should defer the host's probe.
1531 * It makes sure panel is connected when fbcon detects
1532 * connector status and gets the proper display mode to
1533 * create framebuffer.
1534 * Don't try to defer if there is nothing connected to the dsi
1537 if (check_defer && msm_host->device_node) {
1538 if (!of_drm_find_panel(msm_host->device_node))
1539 if (!of_drm_find_bridge(msm_host->device_node))
1540 return -EPROBE_DEFER;
1547 void msm_dsi_host_unregister(struct mipi_dsi_host *host)
1549 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1551 if (msm_host->registered) {
1552 mipi_dsi_host_unregister(host);
1555 msm_host->registered = false;
1559 int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host,
1560 const struct mipi_dsi_msg *msg)
1562 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1564 /* TODO: make sure dsi_cmd_mdp is idle.
1565 * Since DSI6G v1.2.0, we can set DSI_TRIG_CTRL.BLOCK_DMA_WITHIN_FRAME
1566 * to ask H/W to wait until cmd mdp is idle. S/W wait is not needed.
1567 * How to handle the old versions? Wait for mdp cmd done?
1571 * mdss interrupt is generated in mdp core clock domain
1572 * mdp clock need to be enabled to receive dsi interrupt
1574 dsi_clk_ctrl(msm_host, 1);
1576 /* TODO: vote for bus bandwidth */
1578 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM))
1579 dsi_set_tx_power_mode(0, msm_host);
1581 msm_host->dma_cmd_ctrl_restore = dsi_read(msm_host, REG_DSI_CTRL);
1582 dsi_write(msm_host, REG_DSI_CTRL,
1583 msm_host->dma_cmd_ctrl_restore |
1584 DSI_CTRL_CMD_MODE_EN |
1586 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 1);
1591 void msm_dsi_host_xfer_restore(struct mipi_dsi_host *host,
1592 const struct mipi_dsi_msg *msg)
1594 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1596 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 0);
1597 dsi_write(msm_host, REG_DSI_CTRL, msm_host->dma_cmd_ctrl_restore);
1599 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM))
1600 dsi_set_tx_power_mode(1, msm_host);
1602 /* TODO: unvote for bus bandwidth */
1604 dsi_clk_ctrl(msm_host, 0);
1607 int msm_dsi_host_cmd_tx(struct mipi_dsi_host *host,
1608 const struct mipi_dsi_msg *msg)
1610 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1612 return dsi_cmds2buf_tx(msm_host, msg);
1615 int msm_dsi_host_cmd_rx(struct mipi_dsi_host *host,
1616 const struct mipi_dsi_msg *msg)
1618 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1619 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
1620 int data_byte, rx_byte, dlen, end;
1621 int short_response, diff, pkt_size, ret = 0;
1623 int rlen = msg->rx_len;
1632 data_byte = 10; /* first read */
1633 if (rlen < data_byte)
1636 pkt_size = data_byte;
1637 rx_byte = data_byte + 6; /* 4 header + 2 crc */
1640 buf = msm_host->rx_buf;
1643 u8 tx[2] = {pkt_size & 0xff, pkt_size >> 8};
1644 struct mipi_dsi_msg max_pkt_size_msg = {
1645 .channel = msg->channel,
1646 .type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE,
1651 DBG("rlen=%d pkt_size=%d rx_byte=%d",
1652 rlen, pkt_size, rx_byte);
1654 ret = dsi_cmds2buf_tx(msm_host, &max_pkt_size_msg);
1656 pr_err("%s: Set max pkt size failed, %d\n",
1661 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) &&
1662 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_1)) {
1663 /* Clear the RDBK_DATA registers */
1664 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL,
1665 DSI_RDBK_DATA_CTRL_CLR);
1666 wmb(); /* make sure the RDBK registers are cleared */
1667 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 0);
1668 wmb(); /* release cleared status before transfer */
1671 ret = dsi_cmds2buf_tx(msm_host, msg);
1672 if (ret < msg->tx_len) {
1673 pr_err("%s: Read cmd Tx failed, %d\n", __func__, ret);
1678 * once cmd_dma_done interrupt received,
1679 * return data from client is ready and stored
1680 * at RDBK_DATA register already
1681 * since rx fifo is 16 bytes, dcs header is kept at first loop,
1682 * after that dcs header lost during shift into registers
1684 dlen = dsi_cmd_dma_rx(msm_host, buf, rx_byte, pkt_size);
1692 if (rlen <= data_byte) {
1693 diff = data_byte - rlen;
1701 dlen -= 2; /* 2 crc */
1703 buf += dlen; /* next start position */
1704 data_byte = 14; /* NOT first read */
1705 if (rlen < data_byte)
1708 pkt_size += data_byte;
1709 DBG("buf=%p dlen=%d diff=%d", buf, dlen, diff);
1714 * For single Long read, if the requested rlen < 10,
1715 * we need to shift the start position of rx
1716 * data buffer to skip the bytes which are not
1719 if (pkt_size < 10 && !short_response)
1720 buf = msm_host->rx_buf + (10 - rlen);
1722 buf = msm_host->rx_buf;
1726 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
1727 pr_err("%s: rx ACK_ERR_PACLAGE\n", __func__);
1730 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
1731 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
1732 ret = dsi_short_read1_resp(buf, msg);
1734 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
1735 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
1736 ret = dsi_short_read2_resp(buf, msg);
1738 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
1739 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
1740 ret = dsi_long_read_resp(buf, msg);
1743 pr_warn("%s:Invalid response cmd\n", __func__);
1750 void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 iova, u32 len)
1752 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1754 dsi_write(msm_host, REG_DSI_DMA_BASE, iova);
1755 dsi_write(msm_host, REG_DSI_DMA_LEN, len);
1756 dsi_write(msm_host, REG_DSI_TRIG_DMA, 1);
1758 /* Make sure trigger happens */
1762 int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host,
1763 struct msm_dsi_pll *src_pll)
1765 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1766 struct clk *byte_clk_provider, *pixel_clk_provider;
1769 ret = msm_dsi_pll_get_clk_provider(src_pll,
1770 &byte_clk_provider, &pixel_clk_provider);
1772 pr_info("%s: can't get provider from pll, don't set parent\n",
1777 ret = clk_set_parent(msm_host->byte_clk_src, byte_clk_provider);
1779 pr_err("%s: can't set parent to byte_clk_src. ret=%d\n",
1784 ret = clk_set_parent(msm_host->pixel_clk_src, pixel_clk_provider);
1786 pr_err("%s: can't set parent to pixel_clk_src. ret=%d\n",
1795 int msm_dsi_host_enable(struct mipi_dsi_host *host)
1797 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1799 dsi_op_mode_config(msm_host,
1800 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), true);
1802 /* TODO: clock should be turned off for command mode,
1803 * and only turned on before MDP START.
1804 * This part of code should be enabled once mdp driver support it.
1806 /* if (msm_panel->mode == MSM_DSI_CMD_MODE)
1807 dsi_clk_ctrl(msm_host, 0); */
1812 int msm_dsi_host_disable(struct mipi_dsi_host *host)
1814 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1816 dsi_op_mode_config(msm_host,
1817 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), false);
1819 /* Since we have disabled INTF, the video engine won't stop so that
1820 * the cmd engine will be blocked.
1821 * Reset to disable video engine so that we can send off cmd.
1823 dsi_sw_reset(msm_host);
1828 int msm_dsi_host_power_on(struct mipi_dsi_host *host)
1830 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1831 u32 clk_pre = 0, clk_post = 0;
1834 mutex_lock(&msm_host->dev_mutex);
1835 if (msm_host->power_on) {
1836 DBG("dsi host already on");
1840 ret = dsi_calc_clk_rate(msm_host);
1842 pr_err("%s: unable to calc clk rate, %d\n", __func__, ret);
1846 ret = dsi_host_regulator_enable(msm_host);
1848 pr_err("%s:Failed to enable vregs.ret=%d\n",
1853 ret = dsi_bus_clk_enable(msm_host);
1855 pr_err("%s: failed to enable bus clocks, %d\n", __func__, ret);
1856 goto fail_disable_reg;
1859 dsi_phy_sw_reset(msm_host);
1860 ret = msm_dsi_manager_phy_enable(msm_host->id,
1861 msm_host->byte_clk_rate * 8,
1862 clk_get_rate(msm_host->esc_clk),
1863 &clk_pre, &clk_post);
1864 dsi_bus_clk_disable(msm_host);
1866 pr_err("%s: failed to enable phy, %d\n", __func__, ret);
1867 goto fail_disable_reg;
1870 ret = dsi_clk_ctrl(msm_host, 1);
1872 pr_err("%s: failed to enable clocks. ret=%d\n", __func__, ret);
1873 goto fail_disable_reg;
1876 ret = pinctrl_pm_select_default_state(&msm_host->pdev->dev);
1878 pr_err("%s: failed to set pinctrl default state, %d\n",
1880 goto fail_disable_clk;
1883 dsi_timing_setup(msm_host);
1884 dsi_sw_reset(msm_host);
1885 dsi_ctrl_config(msm_host, true, clk_pre, clk_post);
1887 if (msm_host->disp_en_gpio)
1888 gpiod_set_value(msm_host->disp_en_gpio, 1);
1890 msm_host->power_on = true;
1891 mutex_unlock(&msm_host->dev_mutex);
1896 dsi_clk_ctrl(msm_host, 0);
1898 dsi_host_regulator_disable(msm_host);
1900 mutex_unlock(&msm_host->dev_mutex);
1904 int msm_dsi_host_power_off(struct mipi_dsi_host *host)
1906 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1908 mutex_lock(&msm_host->dev_mutex);
1909 if (!msm_host->power_on) {
1910 DBG("dsi host already off");
1914 dsi_ctrl_config(msm_host, false, 0, 0);
1916 if (msm_host->disp_en_gpio)
1917 gpiod_set_value(msm_host->disp_en_gpio, 0);
1919 pinctrl_pm_select_sleep_state(&msm_host->pdev->dev);
1921 msm_dsi_manager_phy_disable(msm_host->id);
1923 dsi_clk_ctrl(msm_host, 0);
1925 dsi_host_regulator_disable(msm_host);
1929 msm_host->power_on = false;
1932 mutex_unlock(&msm_host->dev_mutex);
1936 int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host,
1937 struct drm_display_mode *mode)
1939 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1941 if (msm_host->mode) {
1942 drm_mode_destroy(msm_host->dev, msm_host->mode);
1943 msm_host->mode = NULL;
1946 msm_host->mode = drm_mode_duplicate(msm_host->dev, mode);
1947 if (IS_ERR(msm_host->mode)) {
1948 pr_err("%s: cannot duplicate mode\n", __func__);
1949 return PTR_ERR(msm_host->mode);
1955 struct drm_panel *msm_dsi_host_get_panel(struct mipi_dsi_host *host,
1956 unsigned long *panel_flags)
1958 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1959 struct drm_panel *panel;
1961 panel = of_drm_find_panel(msm_host->device_node);
1963 *panel_flags = msm_host->mode_flags;
1968 struct drm_bridge *msm_dsi_host_get_bridge(struct mipi_dsi_host *host)
1970 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1972 return of_drm_find_bridge(msm_host->device_node);