4 /* Autogenerated file, DO NOT EDIT manually!
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
10 The rules-ng-ng source files this header was generated from are:
11 - /local/mnt/workspace/source_trees/envytools/rnndb/../rnndb/hdmi/hdmi.xml ( 41472 bytes, from 2016-01-08 08:20:42)
12 - /local/mnt/workspace/source_trees/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-02-09 03:18:10)
14 Copyright (C) 2013-2016 by the following authors:
15 - Rob Clark <robdclark@gmail.com> (robclark)
17 Permission is hereby granted, free of charge, to any person obtaining
18 a copy of this software and associated documentation files (the
19 "Software"), to deal in the Software without restriction, including
20 without limitation the rights to use, copy, modify, merge, publish,
21 distribute, sublicense, and/or sell copies of the Software, and to
22 permit persons to whom the Software is furnished to do so, subject to
23 the following conditions:
25 The above copyright notice and this permission notice (including the
26 next paragraph) shall be included in all copies or substantial
27 portions of the Software.
29 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
30 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
31 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
32 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
33 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
34 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
35 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
39 enum hdmi_hdcp_key_state {
40 HDCP_KEYS_STATE_NO_KEYS = 0,
41 HDCP_KEYS_STATE_NOT_CHECKED = 1,
42 HDCP_KEYS_STATE_CHECKING = 2,
43 HDCP_KEYS_STATE_VALID = 3,
44 HDCP_KEYS_STATE_AKSV_NOT_VALID = 4,
45 HDCP_KEYS_STATE_CHKSUM_MISMATCH = 5,
46 HDCP_KEYS_STATE_PROD_AKSV = 6,
47 HDCP_KEYS_STATE_RESERVED = 7,
50 enum hdmi_ddc_read_write {
62 #define REG_HDMI_CTRL 0x00000000
63 #define HDMI_CTRL_ENABLE 0x00000001
64 #define HDMI_CTRL_HDMI 0x00000002
65 #define HDMI_CTRL_ENCRYPTED 0x00000004
67 #define REG_HDMI_AUDIO_PKT_CTRL1 0x00000020
68 #define HDMI_AUDIO_PKT_CTRL1_AUDIO_SAMPLE_SEND 0x00000001
70 #define REG_HDMI_ACR_PKT_CTRL 0x00000024
71 #define HDMI_ACR_PKT_CTRL_CONT 0x00000001
72 #define HDMI_ACR_PKT_CTRL_SEND 0x00000002
73 #define HDMI_ACR_PKT_CTRL_SELECT__MASK 0x00000030
74 #define HDMI_ACR_PKT_CTRL_SELECT__SHIFT 4
75 static inline uint32_t HDMI_ACR_PKT_CTRL_SELECT(enum hdmi_acr_cts val)
77 return ((val) << HDMI_ACR_PKT_CTRL_SELECT__SHIFT) & HDMI_ACR_PKT_CTRL_SELECT__MASK;
79 #define HDMI_ACR_PKT_CTRL_SOURCE 0x00000100
80 #define HDMI_ACR_PKT_CTRL_N_MULTIPLIER__MASK 0x00070000
81 #define HDMI_ACR_PKT_CTRL_N_MULTIPLIER__SHIFT 16
82 static inline uint32_t HDMI_ACR_PKT_CTRL_N_MULTIPLIER(uint32_t val)
84 return ((val) << HDMI_ACR_PKT_CTRL_N_MULTIPLIER__SHIFT) & HDMI_ACR_PKT_CTRL_N_MULTIPLIER__MASK;
86 #define HDMI_ACR_PKT_CTRL_AUDIO_PRIORITY 0x80000000
88 #define REG_HDMI_VBI_PKT_CTRL 0x00000028
89 #define HDMI_VBI_PKT_CTRL_GC_ENABLE 0x00000010
90 #define HDMI_VBI_PKT_CTRL_GC_EVERY_FRAME 0x00000020
91 #define HDMI_VBI_PKT_CTRL_ISRC_SEND 0x00000100
92 #define HDMI_VBI_PKT_CTRL_ISRC_CONTINUOUS 0x00000200
93 #define HDMI_VBI_PKT_CTRL_ACP_SEND 0x00001000
94 #define HDMI_VBI_PKT_CTRL_ACP_SRC_SW 0x00002000
96 #define REG_HDMI_INFOFRAME_CTRL0 0x0000002c
97 #define HDMI_INFOFRAME_CTRL0_AVI_SEND 0x00000001
98 #define HDMI_INFOFRAME_CTRL0_AVI_CONT 0x00000002
99 #define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SEND 0x00000010
100 #define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_CONT 0x00000020
101 #define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SOURCE 0x00000040
102 #define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_UPDATE 0x00000080
104 #define REG_HDMI_GEN_PKT_CTRL 0x00000034
105 #define HDMI_GEN_PKT_CTRL_GENERIC0_SEND 0x00000001
106 #define HDMI_GEN_PKT_CTRL_GENERIC0_CONT 0x00000002
107 #define HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__MASK 0x0000000c
108 #define HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__SHIFT 2
109 static inline uint32_t HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE(uint32_t val)
111 return ((val) << HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__SHIFT) & HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__MASK;
113 #define HDMI_GEN_PKT_CTRL_GENERIC1_SEND 0x00000010
114 #define HDMI_GEN_PKT_CTRL_GENERIC1_CONT 0x00000020
115 #define HDMI_GEN_PKT_CTRL_GENERIC0_LINE__MASK 0x003f0000
116 #define HDMI_GEN_PKT_CTRL_GENERIC0_LINE__SHIFT 16
117 static inline uint32_t HDMI_GEN_PKT_CTRL_GENERIC0_LINE(uint32_t val)
119 return ((val) << HDMI_GEN_PKT_CTRL_GENERIC0_LINE__SHIFT) & HDMI_GEN_PKT_CTRL_GENERIC0_LINE__MASK;
121 #define HDMI_GEN_PKT_CTRL_GENERIC1_LINE__MASK 0x3f000000
122 #define HDMI_GEN_PKT_CTRL_GENERIC1_LINE__SHIFT 24
123 static inline uint32_t HDMI_GEN_PKT_CTRL_GENERIC1_LINE(uint32_t val)
125 return ((val) << HDMI_GEN_PKT_CTRL_GENERIC1_LINE__SHIFT) & HDMI_GEN_PKT_CTRL_GENERIC1_LINE__MASK;
128 #define REG_HDMI_GC 0x00000040
129 #define HDMI_GC_MUTE 0x00000001
131 #define REG_HDMI_AUDIO_PKT_CTRL2 0x00000044
132 #define HDMI_AUDIO_PKT_CTRL2_OVERRIDE 0x00000001
133 #define HDMI_AUDIO_PKT_CTRL2_LAYOUT 0x00000002
135 static inline uint32_t REG_HDMI_AVI_INFO(uint32_t i0) { return 0x0000006c + 0x4*i0; }
137 #define REG_HDMI_GENERIC0_HDR 0x00000084
139 static inline uint32_t REG_HDMI_GENERIC0(uint32_t i0) { return 0x00000088 + 0x4*i0; }
141 #define REG_HDMI_GENERIC1_HDR 0x000000a4
143 static inline uint32_t REG_HDMI_GENERIC1(uint32_t i0) { return 0x000000a8 + 0x4*i0; }
145 static inline uint32_t REG_HDMI_ACR(enum hdmi_acr_cts i0) { return 0x000000c4 + 0x8*i0; }
147 static inline uint32_t REG_HDMI_ACR_0(enum hdmi_acr_cts i0) { return 0x000000c4 + 0x8*i0; }
148 #define HDMI_ACR_0_CTS__MASK 0xfffff000
149 #define HDMI_ACR_0_CTS__SHIFT 12
150 static inline uint32_t HDMI_ACR_0_CTS(uint32_t val)
152 return ((val) << HDMI_ACR_0_CTS__SHIFT) & HDMI_ACR_0_CTS__MASK;
155 static inline uint32_t REG_HDMI_ACR_1(enum hdmi_acr_cts i0) { return 0x000000c8 + 0x8*i0; }
156 #define HDMI_ACR_1_N__MASK 0xffffffff
157 #define HDMI_ACR_1_N__SHIFT 0
158 static inline uint32_t HDMI_ACR_1_N(uint32_t val)
160 return ((val) << HDMI_ACR_1_N__SHIFT) & HDMI_ACR_1_N__MASK;
163 #define REG_HDMI_AUDIO_INFO0 0x000000e4
164 #define HDMI_AUDIO_INFO0_CHECKSUM__MASK 0x000000ff
165 #define HDMI_AUDIO_INFO0_CHECKSUM__SHIFT 0
166 static inline uint32_t HDMI_AUDIO_INFO0_CHECKSUM(uint32_t val)
168 return ((val) << HDMI_AUDIO_INFO0_CHECKSUM__SHIFT) & HDMI_AUDIO_INFO0_CHECKSUM__MASK;
170 #define HDMI_AUDIO_INFO0_CC__MASK 0x00000700
171 #define HDMI_AUDIO_INFO0_CC__SHIFT 8
172 static inline uint32_t HDMI_AUDIO_INFO0_CC(uint32_t val)
174 return ((val) << HDMI_AUDIO_INFO0_CC__SHIFT) & HDMI_AUDIO_INFO0_CC__MASK;
177 #define REG_HDMI_AUDIO_INFO1 0x000000e8
178 #define HDMI_AUDIO_INFO1_CA__MASK 0x000000ff
179 #define HDMI_AUDIO_INFO1_CA__SHIFT 0
180 static inline uint32_t HDMI_AUDIO_INFO1_CA(uint32_t val)
182 return ((val) << HDMI_AUDIO_INFO1_CA__SHIFT) & HDMI_AUDIO_INFO1_CA__MASK;
184 #define HDMI_AUDIO_INFO1_LSV__MASK 0x00007800
185 #define HDMI_AUDIO_INFO1_LSV__SHIFT 11
186 static inline uint32_t HDMI_AUDIO_INFO1_LSV(uint32_t val)
188 return ((val) << HDMI_AUDIO_INFO1_LSV__SHIFT) & HDMI_AUDIO_INFO1_LSV__MASK;
190 #define HDMI_AUDIO_INFO1_DM_INH 0x00008000
192 #define REG_HDMI_HDCP_CTRL 0x00000110
193 #define HDMI_HDCP_CTRL_ENABLE 0x00000001
194 #define HDMI_HDCP_CTRL_ENCRYPTION_ENABLE 0x00000100
196 #define REG_HDMI_HDCP_DEBUG_CTRL 0x00000114
197 #define HDMI_HDCP_DEBUG_CTRL_RNG_CIPHER 0x00000004
199 #define REG_HDMI_HDCP_INT_CTRL 0x00000118
200 #define HDMI_HDCP_INT_CTRL_AUTH_SUCCESS_INT 0x00000001
201 #define HDMI_HDCP_INT_CTRL_AUTH_SUCCESS_ACK 0x00000002
202 #define HDMI_HDCP_INT_CTRL_AUTH_SUCCESS_MASK 0x00000004
203 #define HDMI_HDCP_INT_CTRL_AUTH_FAIL_INT 0x00000010
204 #define HDMI_HDCP_INT_CTRL_AUTH_FAIL_ACK 0x00000020
205 #define HDMI_HDCP_INT_CTRL_AUTH_FAIL_MASK 0x00000040
206 #define HDMI_HDCP_INT_CTRL_AUTH_FAIL_INFO_ACK 0x00000080
207 #define HDMI_HDCP_INT_CTRL_AUTH_XFER_REQ_INT 0x00000100
208 #define HDMI_HDCP_INT_CTRL_AUTH_XFER_REQ_ACK 0x00000200
209 #define HDMI_HDCP_INT_CTRL_AUTH_XFER_REQ_MASK 0x00000400
210 #define HDMI_HDCP_INT_CTRL_AUTH_XFER_DONE_INT 0x00001000
211 #define HDMI_HDCP_INT_CTRL_AUTH_XFER_DONE_ACK 0x00002000
212 #define HDMI_HDCP_INT_CTRL_AUTH_XFER_DONE_MASK 0x00004000
214 #define REG_HDMI_HDCP_LINK0_STATUS 0x0000011c
215 #define HDMI_HDCP_LINK0_STATUS_AN_0_READY 0x00000100
216 #define HDMI_HDCP_LINK0_STATUS_AN_1_READY 0x00000200
217 #define HDMI_HDCP_LINK0_STATUS_RI_MATCHES 0x00001000
218 #define HDMI_HDCP_LINK0_STATUS_V_MATCHES 0x00100000
219 #define HDMI_HDCP_LINK0_STATUS_KEY_STATE__MASK 0x70000000
220 #define HDMI_HDCP_LINK0_STATUS_KEY_STATE__SHIFT 28
221 static inline uint32_t HDMI_HDCP_LINK0_STATUS_KEY_STATE(enum hdmi_hdcp_key_state val)
223 return ((val) << HDMI_HDCP_LINK0_STATUS_KEY_STATE__SHIFT) & HDMI_HDCP_LINK0_STATUS_KEY_STATE__MASK;
226 #define REG_HDMI_HDCP_DDC_CTRL_0 0x00000120
227 #define HDMI_HDCP_DDC_CTRL_0_DISABLE 0x00000001
229 #define REG_HDMI_HDCP_DDC_CTRL_1 0x00000124
230 #define HDMI_HDCP_DDC_CTRL_1_FAILED_ACK 0x00000001
232 #define REG_HDMI_HDCP_DDC_STATUS 0x00000128
233 #define HDMI_HDCP_DDC_STATUS_XFER_REQ 0x00000010
234 #define HDMI_HDCP_DDC_STATUS_XFER_DONE 0x00000400
235 #define HDMI_HDCP_DDC_STATUS_ABORTED 0x00001000
236 #define HDMI_HDCP_DDC_STATUS_TIMEOUT 0x00002000
237 #define HDMI_HDCP_DDC_STATUS_NACK0 0x00004000
238 #define HDMI_HDCP_DDC_STATUS_NACK1 0x00008000
239 #define HDMI_HDCP_DDC_STATUS_FAILED 0x00010000
241 #define REG_HDMI_HDCP_ENTROPY_CTRL0 0x0000012c
243 #define REG_HDMI_HDCP_ENTROPY_CTRL1 0x0000025c
245 #define REG_HDMI_HDCP_RESET 0x00000130
246 #define HDMI_HDCP_RESET_LINK0_DEAUTHENTICATE 0x00000001
248 #define REG_HDMI_HDCP_RCVPORT_DATA0 0x00000134
250 #define REG_HDMI_HDCP_RCVPORT_DATA1 0x00000138
252 #define REG_HDMI_HDCP_RCVPORT_DATA2_0 0x0000013c
254 #define REG_HDMI_HDCP_RCVPORT_DATA2_1 0x00000140
256 #define REG_HDMI_HDCP_RCVPORT_DATA3 0x00000144
258 #define REG_HDMI_HDCP_RCVPORT_DATA4 0x00000148
260 #define REG_HDMI_HDCP_RCVPORT_DATA5 0x0000014c
262 #define REG_HDMI_HDCP_RCVPORT_DATA6 0x00000150
264 #define REG_HDMI_HDCP_RCVPORT_DATA7 0x00000154
266 #define REG_HDMI_HDCP_RCVPORT_DATA8 0x00000158
268 #define REG_HDMI_HDCP_RCVPORT_DATA9 0x0000015c
270 #define REG_HDMI_HDCP_RCVPORT_DATA10 0x00000160
272 #define REG_HDMI_HDCP_RCVPORT_DATA11 0x00000164
274 #define REG_HDMI_HDCP_RCVPORT_DATA12 0x00000168
276 #define REG_HDMI_VENSPEC_INFO0 0x0000016c
278 #define REG_HDMI_VENSPEC_INFO1 0x00000170
280 #define REG_HDMI_VENSPEC_INFO2 0x00000174
282 #define REG_HDMI_VENSPEC_INFO3 0x00000178
284 #define REG_HDMI_VENSPEC_INFO4 0x0000017c
286 #define REG_HDMI_VENSPEC_INFO5 0x00000180
288 #define REG_HDMI_VENSPEC_INFO6 0x00000184
290 #define REG_HDMI_AUDIO_CFG 0x000001d0
291 #define HDMI_AUDIO_CFG_ENGINE_ENABLE 0x00000001
292 #define HDMI_AUDIO_CFG_FIFO_WATERMARK__MASK 0x000000f0
293 #define HDMI_AUDIO_CFG_FIFO_WATERMARK__SHIFT 4
294 static inline uint32_t HDMI_AUDIO_CFG_FIFO_WATERMARK(uint32_t val)
296 return ((val) << HDMI_AUDIO_CFG_FIFO_WATERMARK__SHIFT) & HDMI_AUDIO_CFG_FIFO_WATERMARK__MASK;
299 #define REG_HDMI_USEC_REFTIMER 0x00000208
301 #define REG_HDMI_DDC_CTRL 0x0000020c
302 #define HDMI_DDC_CTRL_GO 0x00000001
303 #define HDMI_DDC_CTRL_SOFT_RESET 0x00000002
304 #define HDMI_DDC_CTRL_SEND_RESET 0x00000004
305 #define HDMI_DDC_CTRL_SW_STATUS_RESET 0x00000008
306 #define HDMI_DDC_CTRL_TRANSACTION_CNT__MASK 0x00300000
307 #define HDMI_DDC_CTRL_TRANSACTION_CNT__SHIFT 20
308 static inline uint32_t HDMI_DDC_CTRL_TRANSACTION_CNT(uint32_t val)
310 return ((val) << HDMI_DDC_CTRL_TRANSACTION_CNT__SHIFT) & HDMI_DDC_CTRL_TRANSACTION_CNT__MASK;
313 #define REG_HDMI_DDC_ARBITRATION 0x00000210
314 #define HDMI_DDC_ARBITRATION_HW_ARBITRATION 0x00000010
316 #define REG_HDMI_DDC_INT_CTRL 0x00000214
317 #define HDMI_DDC_INT_CTRL_SW_DONE_INT 0x00000001
318 #define HDMI_DDC_INT_CTRL_SW_DONE_ACK 0x00000002
319 #define HDMI_DDC_INT_CTRL_SW_DONE_MASK 0x00000004
321 #define REG_HDMI_DDC_SW_STATUS 0x00000218
322 #define HDMI_DDC_SW_STATUS_NACK0 0x00001000
323 #define HDMI_DDC_SW_STATUS_NACK1 0x00002000
324 #define HDMI_DDC_SW_STATUS_NACK2 0x00004000
325 #define HDMI_DDC_SW_STATUS_NACK3 0x00008000
327 #define REG_HDMI_DDC_HW_STATUS 0x0000021c
328 #define HDMI_DDC_HW_STATUS_DONE 0x00000008
330 #define REG_HDMI_DDC_SPEED 0x00000220
331 #define HDMI_DDC_SPEED_THRESHOLD__MASK 0x00000003
332 #define HDMI_DDC_SPEED_THRESHOLD__SHIFT 0
333 static inline uint32_t HDMI_DDC_SPEED_THRESHOLD(uint32_t val)
335 return ((val) << HDMI_DDC_SPEED_THRESHOLD__SHIFT) & HDMI_DDC_SPEED_THRESHOLD__MASK;
337 #define HDMI_DDC_SPEED_PRESCALE__MASK 0xffff0000
338 #define HDMI_DDC_SPEED_PRESCALE__SHIFT 16
339 static inline uint32_t HDMI_DDC_SPEED_PRESCALE(uint32_t val)
341 return ((val) << HDMI_DDC_SPEED_PRESCALE__SHIFT) & HDMI_DDC_SPEED_PRESCALE__MASK;
344 #define REG_HDMI_DDC_SETUP 0x00000224
345 #define HDMI_DDC_SETUP_TIMEOUT__MASK 0xff000000
346 #define HDMI_DDC_SETUP_TIMEOUT__SHIFT 24
347 static inline uint32_t HDMI_DDC_SETUP_TIMEOUT(uint32_t val)
349 return ((val) << HDMI_DDC_SETUP_TIMEOUT__SHIFT) & HDMI_DDC_SETUP_TIMEOUT__MASK;
352 static inline uint32_t REG_HDMI_I2C_TRANSACTION(uint32_t i0) { return 0x00000228 + 0x4*i0; }
354 static inline uint32_t REG_HDMI_I2C_TRANSACTION_REG(uint32_t i0) { return 0x00000228 + 0x4*i0; }
355 #define HDMI_I2C_TRANSACTION_REG_RW__MASK 0x00000001
356 #define HDMI_I2C_TRANSACTION_REG_RW__SHIFT 0
357 static inline uint32_t HDMI_I2C_TRANSACTION_REG_RW(enum hdmi_ddc_read_write val)
359 return ((val) << HDMI_I2C_TRANSACTION_REG_RW__SHIFT) & HDMI_I2C_TRANSACTION_REG_RW__MASK;
361 #define HDMI_I2C_TRANSACTION_REG_STOP_ON_NACK 0x00000100
362 #define HDMI_I2C_TRANSACTION_REG_START 0x00001000
363 #define HDMI_I2C_TRANSACTION_REG_STOP 0x00002000
364 #define HDMI_I2C_TRANSACTION_REG_CNT__MASK 0x00ff0000
365 #define HDMI_I2C_TRANSACTION_REG_CNT__SHIFT 16
366 static inline uint32_t HDMI_I2C_TRANSACTION_REG_CNT(uint32_t val)
368 return ((val) << HDMI_I2C_TRANSACTION_REG_CNT__SHIFT) & HDMI_I2C_TRANSACTION_REG_CNT__MASK;
371 #define REG_HDMI_DDC_DATA 0x00000238
372 #define HDMI_DDC_DATA_DATA_RW__MASK 0x00000001
373 #define HDMI_DDC_DATA_DATA_RW__SHIFT 0
374 static inline uint32_t HDMI_DDC_DATA_DATA_RW(enum hdmi_ddc_read_write val)
376 return ((val) << HDMI_DDC_DATA_DATA_RW__SHIFT) & HDMI_DDC_DATA_DATA_RW__MASK;
378 #define HDMI_DDC_DATA_DATA__MASK 0x0000ff00
379 #define HDMI_DDC_DATA_DATA__SHIFT 8
380 static inline uint32_t HDMI_DDC_DATA_DATA(uint32_t val)
382 return ((val) << HDMI_DDC_DATA_DATA__SHIFT) & HDMI_DDC_DATA_DATA__MASK;
384 #define HDMI_DDC_DATA_INDEX__MASK 0x00ff0000
385 #define HDMI_DDC_DATA_INDEX__SHIFT 16
386 static inline uint32_t HDMI_DDC_DATA_INDEX(uint32_t val)
388 return ((val) << HDMI_DDC_DATA_INDEX__SHIFT) & HDMI_DDC_DATA_INDEX__MASK;
390 #define HDMI_DDC_DATA_INDEX_WRITE 0x80000000
392 #define REG_HDMI_HDCP_SHA_CTRL 0x0000023c
394 #define REG_HDMI_HDCP_SHA_STATUS 0x00000240
395 #define HDMI_HDCP_SHA_STATUS_BLOCK_DONE 0x00000001
396 #define HDMI_HDCP_SHA_STATUS_COMP_DONE 0x00000010
398 #define REG_HDMI_HDCP_SHA_DATA 0x00000244
399 #define HDMI_HDCP_SHA_DATA_DONE 0x00000001
401 #define REG_HDMI_HPD_INT_STATUS 0x00000250
402 #define HDMI_HPD_INT_STATUS_INT 0x00000001
403 #define HDMI_HPD_INT_STATUS_CABLE_DETECTED 0x00000002
405 #define REG_HDMI_HPD_INT_CTRL 0x00000254
406 #define HDMI_HPD_INT_CTRL_INT_ACK 0x00000001
407 #define HDMI_HPD_INT_CTRL_INT_CONNECT 0x00000002
408 #define HDMI_HPD_INT_CTRL_INT_EN 0x00000004
409 #define HDMI_HPD_INT_CTRL_RX_INT_ACK 0x00000010
410 #define HDMI_HPD_INT_CTRL_RX_INT_EN 0x00000020
411 #define HDMI_HPD_INT_CTRL_RCV_PLUGIN_DET_MASK 0x00000200
413 #define REG_HDMI_HPD_CTRL 0x00000258
414 #define HDMI_HPD_CTRL_TIMEOUT__MASK 0x00001fff
415 #define HDMI_HPD_CTRL_TIMEOUT__SHIFT 0
416 static inline uint32_t HDMI_HPD_CTRL_TIMEOUT(uint32_t val)
418 return ((val) << HDMI_HPD_CTRL_TIMEOUT__SHIFT) & HDMI_HPD_CTRL_TIMEOUT__MASK;
420 #define HDMI_HPD_CTRL_ENABLE 0x10000000
422 #define REG_HDMI_DDC_REF 0x0000027c
423 #define HDMI_DDC_REF_REFTIMER_ENABLE 0x00010000
424 #define HDMI_DDC_REF_REFTIMER__MASK 0x0000ffff
425 #define HDMI_DDC_REF_REFTIMER__SHIFT 0
426 static inline uint32_t HDMI_DDC_REF_REFTIMER(uint32_t val)
428 return ((val) << HDMI_DDC_REF_REFTIMER__SHIFT) & HDMI_DDC_REF_REFTIMER__MASK;
431 #define REG_HDMI_HDCP_SW_UPPER_AKSV 0x00000284
433 #define REG_HDMI_HDCP_SW_LOWER_AKSV 0x00000288
435 #define REG_HDMI_CEC_CTRL 0x0000028c
437 #define REG_HDMI_CEC_WR_DATA 0x00000290
439 #define REG_HDMI_CEC_CEC_RETRANSMIT 0x00000294
441 #define REG_HDMI_CEC_STATUS 0x00000298
443 #define REG_HDMI_CEC_INT 0x0000029c
445 #define REG_HDMI_CEC_ADDR 0x000002a0
447 #define REG_HDMI_CEC_TIME 0x000002a4
449 #define REG_HDMI_CEC_REFTIMER 0x000002a8
451 #define REG_HDMI_CEC_RD_DATA 0x000002ac
453 #define REG_HDMI_CEC_RD_FILTER 0x000002b0
455 #define REG_HDMI_ACTIVE_HSYNC 0x000002b4
456 #define HDMI_ACTIVE_HSYNC_START__MASK 0x00000fff
457 #define HDMI_ACTIVE_HSYNC_START__SHIFT 0
458 static inline uint32_t HDMI_ACTIVE_HSYNC_START(uint32_t val)
460 return ((val) << HDMI_ACTIVE_HSYNC_START__SHIFT) & HDMI_ACTIVE_HSYNC_START__MASK;
462 #define HDMI_ACTIVE_HSYNC_END__MASK 0x0fff0000
463 #define HDMI_ACTIVE_HSYNC_END__SHIFT 16
464 static inline uint32_t HDMI_ACTIVE_HSYNC_END(uint32_t val)
466 return ((val) << HDMI_ACTIVE_HSYNC_END__SHIFT) & HDMI_ACTIVE_HSYNC_END__MASK;
469 #define REG_HDMI_ACTIVE_VSYNC 0x000002b8
470 #define HDMI_ACTIVE_VSYNC_START__MASK 0x00000fff
471 #define HDMI_ACTIVE_VSYNC_START__SHIFT 0
472 static inline uint32_t HDMI_ACTIVE_VSYNC_START(uint32_t val)
474 return ((val) << HDMI_ACTIVE_VSYNC_START__SHIFT) & HDMI_ACTIVE_VSYNC_START__MASK;
476 #define HDMI_ACTIVE_VSYNC_END__MASK 0x0fff0000
477 #define HDMI_ACTIVE_VSYNC_END__SHIFT 16
478 static inline uint32_t HDMI_ACTIVE_VSYNC_END(uint32_t val)
480 return ((val) << HDMI_ACTIVE_VSYNC_END__SHIFT) & HDMI_ACTIVE_VSYNC_END__MASK;
483 #define REG_HDMI_VSYNC_ACTIVE_F2 0x000002bc
484 #define HDMI_VSYNC_ACTIVE_F2_START__MASK 0x00000fff
485 #define HDMI_VSYNC_ACTIVE_F2_START__SHIFT 0
486 static inline uint32_t HDMI_VSYNC_ACTIVE_F2_START(uint32_t val)
488 return ((val) << HDMI_VSYNC_ACTIVE_F2_START__SHIFT) & HDMI_VSYNC_ACTIVE_F2_START__MASK;
490 #define HDMI_VSYNC_ACTIVE_F2_END__MASK 0x0fff0000
491 #define HDMI_VSYNC_ACTIVE_F2_END__SHIFT 16
492 static inline uint32_t HDMI_VSYNC_ACTIVE_F2_END(uint32_t val)
494 return ((val) << HDMI_VSYNC_ACTIVE_F2_END__SHIFT) & HDMI_VSYNC_ACTIVE_F2_END__MASK;
497 #define REG_HDMI_TOTAL 0x000002c0
498 #define HDMI_TOTAL_H_TOTAL__MASK 0x00000fff
499 #define HDMI_TOTAL_H_TOTAL__SHIFT 0
500 static inline uint32_t HDMI_TOTAL_H_TOTAL(uint32_t val)
502 return ((val) << HDMI_TOTAL_H_TOTAL__SHIFT) & HDMI_TOTAL_H_TOTAL__MASK;
504 #define HDMI_TOTAL_V_TOTAL__MASK 0x0fff0000
505 #define HDMI_TOTAL_V_TOTAL__SHIFT 16
506 static inline uint32_t HDMI_TOTAL_V_TOTAL(uint32_t val)
508 return ((val) << HDMI_TOTAL_V_TOTAL__SHIFT) & HDMI_TOTAL_V_TOTAL__MASK;
511 #define REG_HDMI_VSYNC_TOTAL_F2 0x000002c4
512 #define HDMI_VSYNC_TOTAL_F2_V_TOTAL__MASK 0x00000fff
513 #define HDMI_VSYNC_TOTAL_F2_V_TOTAL__SHIFT 0
514 static inline uint32_t HDMI_VSYNC_TOTAL_F2_V_TOTAL(uint32_t val)
516 return ((val) << HDMI_VSYNC_TOTAL_F2_V_TOTAL__SHIFT) & HDMI_VSYNC_TOTAL_F2_V_TOTAL__MASK;
519 #define REG_HDMI_FRAME_CTRL 0x000002c8
520 #define HDMI_FRAME_CTRL_RGB_MUX_SEL_BGR 0x00001000
521 #define HDMI_FRAME_CTRL_VSYNC_LOW 0x10000000
522 #define HDMI_FRAME_CTRL_HSYNC_LOW 0x20000000
523 #define HDMI_FRAME_CTRL_INTERLACED_EN 0x80000000
525 #define REG_HDMI_AUD_INT 0x000002cc
526 #define HDMI_AUD_INT_AUD_FIFO_URUN_INT 0x00000001
527 #define HDMI_AUD_INT_AUD_FIFO_URAN_MASK 0x00000002
528 #define HDMI_AUD_INT_AUD_SAM_DROP_INT 0x00000004
529 #define HDMI_AUD_INT_AUD_SAM_DROP_MASK 0x00000008
531 #define REG_HDMI_PHY_CTRL 0x000002d4
532 #define HDMI_PHY_CTRL_SW_RESET_PLL 0x00000001
533 #define HDMI_PHY_CTRL_SW_RESET_PLL_LOW 0x00000002
534 #define HDMI_PHY_CTRL_SW_RESET 0x00000004
535 #define HDMI_PHY_CTRL_SW_RESET_LOW 0x00000008
537 #define REG_HDMI_CEC_WR_RANGE 0x000002dc
539 #define REG_HDMI_CEC_RD_RANGE 0x000002e0
541 #define REG_HDMI_VERSION 0x000002e4
543 #define REG_HDMI_CEC_COMPL_CTL 0x00000360
545 #define REG_HDMI_CEC_RD_START_RANGE 0x00000364
547 #define REG_HDMI_CEC_RD_TOTAL_RANGE 0x00000368
549 #define REG_HDMI_CEC_RD_ERR_RESP_LO 0x0000036c
551 #define REG_HDMI_CEC_WR_CHECK_CONFIG 0x00000370
553 #define REG_HDMI_8x60_PHY_REG0 0x00000000
554 #define HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__MASK 0x0000001c
555 #define HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__SHIFT 2
556 static inline uint32_t HDMI_8x60_PHY_REG0_DESER_DEL_CTRL(uint32_t val)
558 return ((val) << HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__SHIFT) & HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__MASK;
561 #define REG_HDMI_8x60_PHY_REG1 0x00000004
562 #define HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__MASK 0x000000f0
563 #define HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__SHIFT 4
564 static inline uint32_t HDMI_8x60_PHY_REG1_DTEST_MUX_SEL(uint32_t val)
566 return ((val) << HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__SHIFT) & HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__MASK;
568 #define HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__MASK 0x0000000f
569 #define HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__SHIFT 0
570 static inline uint32_t HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(uint32_t val)
572 return ((val) << HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__SHIFT) & HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__MASK;
575 #define REG_HDMI_8x60_PHY_REG2 0x00000008
576 #define HDMI_8x60_PHY_REG2_PD_DESER 0x00000001
577 #define HDMI_8x60_PHY_REG2_PD_DRIVE_1 0x00000002
578 #define HDMI_8x60_PHY_REG2_PD_DRIVE_2 0x00000004
579 #define HDMI_8x60_PHY_REG2_PD_DRIVE_3 0x00000008
580 #define HDMI_8x60_PHY_REG2_PD_DRIVE_4 0x00000010
581 #define HDMI_8x60_PHY_REG2_PD_PLL 0x00000020
582 #define HDMI_8x60_PHY_REG2_PD_PWRGEN 0x00000040
583 #define HDMI_8x60_PHY_REG2_RCV_SENSE_EN 0x00000080
585 #define REG_HDMI_8x60_PHY_REG3 0x0000000c
586 #define HDMI_8x60_PHY_REG3_PLL_ENABLE 0x00000001
588 #define REG_HDMI_8x60_PHY_REG4 0x00000010
590 #define REG_HDMI_8x60_PHY_REG5 0x00000014
592 #define REG_HDMI_8x60_PHY_REG6 0x00000018
594 #define REG_HDMI_8x60_PHY_REG7 0x0000001c
596 #define REG_HDMI_8x60_PHY_REG8 0x00000020
598 #define REG_HDMI_8x60_PHY_REG9 0x00000024
600 #define REG_HDMI_8x60_PHY_REG10 0x00000028
602 #define REG_HDMI_8x60_PHY_REG11 0x0000002c
604 #define REG_HDMI_8x60_PHY_REG12 0x00000030
605 #define HDMI_8x60_PHY_REG12_RETIMING_EN 0x00000001
606 #define HDMI_8x60_PHY_REG12_PLL_LOCK_DETECT_EN 0x00000002
607 #define HDMI_8x60_PHY_REG12_FORCE_LOCK 0x00000010
609 #define REG_HDMI_8960_PHY_REG0 0x00000000
611 #define REG_HDMI_8960_PHY_REG1 0x00000004
613 #define REG_HDMI_8960_PHY_REG2 0x00000008
615 #define REG_HDMI_8960_PHY_REG3 0x0000000c
617 #define REG_HDMI_8960_PHY_REG4 0x00000010
619 #define REG_HDMI_8960_PHY_REG5 0x00000014
621 #define REG_HDMI_8960_PHY_REG6 0x00000018
623 #define REG_HDMI_8960_PHY_REG7 0x0000001c
625 #define REG_HDMI_8960_PHY_REG8 0x00000020
627 #define REG_HDMI_8960_PHY_REG9 0x00000024
629 #define REG_HDMI_8960_PHY_REG10 0x00000028
631 #define REG_HDMI_8960_PHY_REG11 0x0000002c
633 #define REG_HDMI_8960_PHY_REG12 0x00000030
634 #define HDMI_8960_PHY_REG12_SW_RESET 0x00000020
635 #define HDMI_8960_PHY_REG12_PWRDN_B 0x00000080
637 #define REG_HDMI_8960_PHY_REG_BIST_CFG 0x00000034
639 #define REG_HDMI_8960_PHY_DEBUG_BUS_SEL 0x00000038
641 #define REG_HDMI_8960_PHY_REG_MISC0 0x0000003c
643 #define REG_HDMI_8960_PHY_REG13 0x00000040
645 #define REG_HDMI_8960_PHY_REG14 0x00000044
647 #define REG_HDMI_8960_PHY_REG15 0x00000048
649 #define REG_HDMI_8960_PHY_PLL_REFCLK_CFG 0x00000000
651 #define REG_HDMI_8960_PHY_PLL_CHRG_PUMP_CFG 0x00000004
653 #define REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 0x00000008
655 #define REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 0x0000000c
657 #define REG_HDMI_8960_PHY_PLL_IDAC_ADJ_CFG 0x00000010
659 #define REG_HDMI_8960_PHY_PLL_I_VI_KVCO_CFG 0x00000014
661 #define REG_HDMI_8960_PHY_PLL_PWRDN_B 0x00000018
662 #define HDMI_8960_PHY_PLL_PWRDN_B_PD_PLL 0x00000002
663 #define HDMI_8960_PHY_PLL_PWRDN_B_PLL_PWRDN_B 0x00000008
665 #define REG_HDMI_8960_PHY_PLL_SDM_CFG0 0x0000001c
667 #define REG_HDMI_8960_PHY_PLL_SDM_CFG1 0x00000020
669 #define REG_HDMI_8960_PHY_PLL_SDM_CFG2 0x00000024
671 #define REG_HDMI_8960_PHY_PLL_SDM_CFG3 0x00000028
673 #define REG_HDMI_8960_PHY_PLL_SDM_CFG4 0x0000002c
675 #define REG_HDMI_8960_PHY_PLL_SSC_CFG0 0x00000030
677 #define REG_HDMI_8960_PHY_PLL_SSC_CFG1 0x00000034
679 #define REG_HDMI_8960_PHY_PLL_SSC_CFG2 0x00000038
681 #define REG_HDMI_8960_PHY_PLL_SSC_CFG3 0x0000003c
683 #define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG0 0x00000040
685 #define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG1 0x00000044
687 #define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2 0x00000048
689 #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 0x0000004c
691 #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 0x00000050
693 #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 0x00000054
695 #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3 0x00000058
697 #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4 0x0000005c
699 #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5 0x00000060
701 #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG6 0x00000064
703 #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG7 0x00000068
705 #define REG_HDMI_8960_PHY_PLL_DEBUG_SEL 0x0000006c
707 #define REG_HDMI_8960_PHY_PLL_MISC0 0x00000070
709 #define REG_HDMI_8960_PHY_PLL_MISC1 0x00000074
711 #define REG_HDMI_8960_PHY_PLL_MISC2 0x00000078
713 #define REG_HDMI_8960_PHY_PLL_MISC3 0x0000007c
715 #define REG_HDMI_8960_PHY_PLL_MISC4 0x00000080
717 #define REG_HDMI_8960_PHY_PLL_MISC5 0x00000084
719 #define REG_HDMI_8960_PHY_PLL_MISC6 0x00000088
721 #define REG_HDMI_8960_PHY_PLL_DEBUG_BUS0 0x0000008c
723 #define REG_HDMI_8960_PHY_PLL_DEBUG_BUS1 0x00000090
725 #define REG_HDMI_8960_PHY_PLL_DEBUG_BUS2 0x00000094
727 #define REG_HDMI_8960_PHY_PLL_STATUS0 0x00000098
728 #define HDMI_8960_PHY_PLL_STATUS0_PLL_LOCK 0x00000001
730 #define REG_HDMI_8960_PHY_PLL_STATUS1 0x0000009c
732 #define REG_HDMI_8x74_ANA_CFG0 0x00000000
734 #define REG_HDMI_8x74_ANA_CFG1 0x00000004
736 #define REG_HDMI_8x74_PD_CTRL0 0x00000010
738 #define REG_HDMI_8x74_PD_CTRL1 0x00000014
740 #define REG_HDMI_8x74_BIST_CFG0 0x00000034
742 #define REG_HDMI_8x74_BIST_PATN0 0x0000003c
744 #define REG_HDMI_8x74_BIST_PATN1 0x00000040
746 #define REG_HDMI_8x74_BIST_PATN2 0x00000044
748 #define REG_HDMI_8x74_BIST_PATN3 0x00000048
750 #define REG_HDMI_28nm_PHY_PLL_REFCLK_CFG 0x00000000
752 #define REG_HDMI_28nm_PHY_PLL_POSTDIV1_CFG 0x00000004
754 #define REG_HDMI_28nm_PHY_PLL_CHGPUMP_CFG 0x00000008
756 #define REG_HDMI_28nm_PHY_PLL_VCOLPF_CFG 0x0000000c
758 #define REG_HDMI_28nm_PHY_PLL_VREG_CFG 0x00000010
760 #define REG_HDMI_28nm_PHY_PLL_PWRGEN_CFG 0x00000014
762 #define REG_HDMI_28nm_PHY_PLL_DMUX_CFG 0x00000018
764 #define REG_HDMI_28nm_PHY_PLL_AMUX_CFG 0x0000001c
766 #define REG_HDMI_28nm_PHY_PLL_GLB_CFG 0x00000020
767 #define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B 0x00000001
768 #define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B 0x00000002
769 #define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B 0x00000004
770 #define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE 0x00000008
772 #define REG_HDMI_28nm_PHY_PLL_POSTDIV2_CFG 0x00000024
774 #define REG_HDMI_28nm_PHY_PLL_POSTDIV3_CFG 0x00000028
776 #define REG_HDMI_28nm_PHY_PLL_LPFR_CFG 0x0000002c
778 #define REG_HDMI_28nm_PHY_PLL_LPFC1_CFG 0x00000030
780 #define REG_HDMI_28nm_PHY_PLL_LPFC2_CFG 0x00000034
782 #define REG_HDMI_28nm_PHY_PLL_SDM_CFG0 0x00000038
784 #define REG_HDMI_28nm_PHY_PLL_SDM_CFG1 0x0000003c
786 #define REG_HDMI_28nm_PHY_PLL_SDM_CFG2 0x00000040
788 #define REG_HDMI_28nm_PHY_PLL_SDM_CFG3 0x00000044
790 #define REG_HDMI_28nm_PHY_PLL_SDM_CFG4 0x00000048
792 #define REG_HDMI_28nm_PHY_PLL_SSC_CFG0 0x0000004c
794 #define REG_HDMI_28nm_PHY_PLL_SSC_CFG1 0x00000050
796 #define REG_HDMI_28nm_PHY_PLL_SSC_CFG2 0x00000054
798 #define REG_HDMI_28nm_PHY_PLL_SSC_CFG3 0x00000058
800 #define REG_HDMI_28nm_PHY_PLL_LKDET_CFG0 0x0000005c
802 #define REG_HDMI_28nm_PHY_PLL_LKDET_CFG1 0x00000060
804 #define REG_HDMI_28nm_PHY_PLL_LKDET_CFG2 0x00000064
806 #define REG_HDMI_28nm_PHY_PLL_TEST_CFG 0x00000068
807 #define HDMI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET 0x00000001
809 #define REG_HDMI_28nm_PHY_PLL_CAL_CFG0 0x0000006c
811 #define REG_HDMI_28nm_PHY_PLL_CAL_CFG1 0x00000070
813 #define REG_HDMI_28nm_PHY_PLL_CAL_CFG2 0x00000074
815 #define REG_HDMI_28nm_PHY_PLL_CAL_CFG3 0x00000078
817 #define REG_HDMI_28nm_PHY_PLL_CAL_CFG4 0x0000007c
819 #define REG_HDMI_28nm_PHY_PLL_CAL_CFG5 0x00000080
821 #define REG_HDMI_28nm_PHY_PLL_CAL_CFG6 0x00000084
823 #define REG_HDMI_28nm_PHY_PLL_CAL_CFG7 0x00000088
825 #define REG_HDMI_28nm_PHY_PLL_CAL_CFG8 0x0000008c
827 #define REG_HDMI_28nm_PHY_PLL_CAL_CFG9 0x00000090
829 #define REG_HDMI_28nm_PHY_PLL_CAL_CFG10 0x00000094
831 #define REG_HDMI_28nm_PHY_PLL_CAL_CFG11 0x00000098
833 #define REG_HDMI_28nm_PHY_PLL_EFUSE_CFG 0x0000009c
835 #define REG_HDMI_28nm_PHY_PLL_DEBUG_BUS_SEL 0x000000a0
837 #define REG_HDMI_8996_PHY_CFG 0x00000000
839 #define REG_HDMI_8996_PHY_PD_CTL 0x00000004
841 #define REG_HDMI_8996_PHY_MODE 0x00000008
843 #define REG_HDMI_8996_PHY_MISR_CLEAR 0x0000000c
845 #define REG_HDMI_8996_PHY_TX0_TX1_BIST_CFG0 0x00000010
847 #define REG_HDMI_8996_PHY_TX0_TX1_BIST_CFG1 0x00000014
849 #define REG_HDMI_8996_PHY_TX0_TX1_PRBS_SEED_BYTE0 0x00000018
851 #define REG_HDMI_8996_PHY_TX0_TX1_PRBS_SEED_BYTE1 0x0000001c
853 #define REG_HDMI_8996_PHY_TX0_TX1_BIST_PATTERN0 0x00000020
855 #define REG_HDMI_8996_PHY_TX0_TX1_BIST_PATTERN1 0x00000024
857 #define REG_HDMI_8996_PHY_TX2_TX3_BIST_CFG0 0x00000028
859 #define REG_HDMI_8996_PHY_TX2_TX3_BIST_CFG1 0x0000002c
861 #define REG_HDMI_8996_PHY_TX2_TX3_PRBS_SEED_BYTE0 0x00000030
863 #define REG_HDMI_8996_PHY_TX2_TX3_PRBS_SEED_BYTE1 0x00000034
865 #define REG_HDMI_8996_PHY_TX2_TX3_BIST_PATTERN0 0x00000038
867 #define REG_HDMI_8996_PHY_TX2_TX3_BIST_PATTERN1 0x0000003c
869 #define REG_HDMI_8996_PHY_DEBUG_BUS_SEL 0x00000040
871 #define REG_HDMI_8996_PHY_TXCAL_CFG0 0x00000044
873 #define REG_HDMI_8996_PHY_TXCAL_CFG1 0x00000048
875 #define REG_HDMI_8996_PHY_TX0_TX1_LANE_CTL 0x0000004c
877 #define REG_HDMI_8996_PHY_TX2_TX3_LANE_CTL 0x00000050
879 #define REG_HDMI_8996_PHY_LANE_BIST_CONFIG 0x00000054
881 #define REG_HDMI_8996_PHY_CLOCK 0x00000058
883 #define REG_HDMI_8996_PHY_MISC1 0x0000005c
885 #define REG_HDMI_8996_PHY_MISC2 0x00000060
887 #define REG_HDMI_8996_PHY_TX0_TX1_BIST_STATUS0 0x00000064
889 #define REG_HDMI_8996_PHY_TX0_TX1_BIST_STATUS1 0x00000068
891 #define REG_HDMI_8996_PHY_TX0_TX1_BIST_STATUS2 0x0000006c
893 #define REG_HDMI_8996_PHY_TX2_TX3_BIST_STATUS0 0x00000070
895 #define REG_HDMI_8996_PHY_TX2_TX3_BIST_STATUS1 0x00000074
897 #define REG_HDMI_8996_PHY_TX2_TX3_BIST_STATUS2 0x00000078
899 #define REG_HDMI_8996_PHY_PRE_MISR_STATUS0 0x0000007c
901 #define REG_HDMI_8996_PHY_PRE_MISR_STATUS1 0x00000080
903 #define REG_HDMI_8996_PHY_PRE_MISR_STATUS2 0x00000084
905 #define REG_HDMI_8996_PHY_PRE_MISR_STATUS3 0x00000088
907 #define REG_HDMI_8996_PHY_POST_MISR_STATUS0 0x0000008c
909 #define REG_HDMI_8996_PHY_POST_MISR_STATUS1 0x00000090
911 #define REG_HDMI_8996_PHY_POST_MISR_STATUS2 0x00000094
913 #define REG_HDMI_8996_PHY_POST_MISR_STATUS3 0x00000098
915 #define REG_HDMI_8996_PHY_STATUS 0x0000009c
917 #define REG_HDMI_8996_PHY_MISC3_STATUS 0x000000a0
919 #define REG_HDMI_8996_PHY_MISC4_STATUS 0x000000a4
921 #define REG_HDMI_8996_PHY_DEBUG_BUS0 0x000000a8
923 #define REG_HDMI_8996_PHY_DEBUG_BUS1 0x000000ac
925 #define REG_HDMI_8996_PHY_DEBUG_BUS2 0x000000b0
927 #define REG_HDMI_8996_PHY_DEBUG_BUS3 0x000000b4
929 #define REG_HDMI_8996_PHY_PHY_REVISION_ID0 0x000000b8
931 #define REG_HDMI_8996_PHY_PHY_REVISION_ID1 0x000000bc
933 #define REG_HDMI_8996_PHY_PHY_REVISION_ID2 0x000000c0
935 #define REG_HDMI_8996_PHY_PHY_REVISION_ID3 0x000000c4
937 #define REG_HDMI_PHY_QSERDES_COM_ATB_SEL1 0x00000000
939 #define REG_HDMI_PHY_QSERDES_COM_ATB_SEL2 0x00000004
941 #define REG_HDMI_PHY_QSERDES_COM_FREQ_UPDATE 0x00000008
943 #define REG_HDMI_PHY_QSERDES_COM_BG_TIMER 0x0000000c
945 #define REG_HDMI_PHY_QSERDES_COM_SSC_EN_CENTER 0x00000010
947 #define REG_HDMI_PHY_QSERDES_COM_SSC_ADJ_PER1 0x00000014
949 #define REG_HDMI_PHY_QSERDES_COM_SSC_ADJ_PER2 0x00000018
951 #define REG_HDMI_PHY_QSERDES_COM_SSC_PER1 0x0000001c
953 #define REG_HDMI_PHY_QSERDES_COM_SSC_PER2 0x00000020
955 #define REG_HDMI_PHY_QSERDES_COM_SSC_STEP_SIZE1 0x00000024
957 #define REG_HDMI_PHY_QSERDES_COM_SSC_STEP_SIZE2 0x00000028
959 #define REG_HDMI_PHY_QSERDES_COM_POST_DIV 0x0000002c
961 #define REG_HDMI_PHY_QSERDES_COM_POST_DIV_MUX 0x00000030
963 #define REG_HDMI_PHY_QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x00000034
965 #define REG_HDMI_PHY_QSERDES_COM_CLK_ENABLE1 0x00000038
967 #define REG_HDMI_PHY_QSERDES_COM_SYS_CLK_CTRL 0x0000003c
969 #define REG_HDMI_PHY_QSERDES_COM_SYSCLK_BUF_ENABLE 0x00000040
971 #define REG_HDMI_PHY_QSERDES_COM_PLL_EN 0x00000044
973 #define REG_HDMI_PHY_QSERDES_COM_PLL_IVCO 0x00000048
975 #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE0 0x0000004c
977 #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE0 0x00000050
979 #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE0 0x00000054
981 #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE1 0x00000058
983 #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE1 0x0000005c
985 #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE1 0x00000060
987 #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE2 0x00000064
989 #define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD0 0x00000064
991 #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE2 0x00000068
993 #define REG_HDMI_PHY_QSERDES_COM_EP_CLOCK_DETECT_CTRL 0x00000068
995 #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE2 0x0000006c
997 #define REG_HDMI_PHY_QSERDES_COM_SYSCLK_DET_COMP_STATUS 0x0000006c
999 #define REG_HDMI_PHY_QSERDES_COM_BG_TRIM 0x00000070
1001 #define REG_HDMI_PHY_QSERDES_COM_CLK_EP_DIV 0x00000074
1003 #define REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE0 0x00000078
1005 #define REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE1 0x0000007c
1007 #define REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE2 0x00000080
1009 #define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD1 0x00000080
1011 #define REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE0 0x00000084
1013 #define REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE1 0x00000088
1015 #define REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE2 0x0000008c
1017 #define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD2 0x0000008c
1019 #define REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE0 0x00000090
1021 #define REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE1 0x00000094
1023 #define REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE2 0x00000098
1025 #define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD3 0x00000098
1027 #define REG_HDMI_PHY_QSERDES_COM_PLL_CNTRL 0x0000009c
1029 #define REG_HDMI_PHY_QSERDES_COM_PHASE_SEL_CTRL 0x000000a0
1031 #define REG_HDMI_PHY_QSERDES_COM_PHASE_SEL_DC 0x000000a4
1033 #define REG_HDMI_PHY_QSERDES_COM_CORE_CLK_IN_SYNC_SEL 0x000000a8
1035 #define REG_HDMI_PHY_QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x000000a8
1037 #define REG_HDMI_PHY_QSERDES_COM_SYSCLK_EN_SEL 0x000000ac
1039 #define REG_HDMI_PHY_QSERDES_COM_CML_SYSCLK_SEL 0x000000b0
1041 #define REG_HDMI_PHY_QSERDES_COM_RESETSM_CNTRL 0x000000b4
1043 #define REG_HDMI_PHY_QSERDES_COM_RESETSM_CNTRL2 0x000000b8
1045 #define REG_HDMI_PHY_QSERDES_COM_RESTRIM_CTRL 0x000000bc
1047 #define REG_HDMI_PHY_QSERDES_COM_RESTRIM_CTRL2 0x000000c0
1049 #define REG_HDMI_PHY_QSERDES_COM_RESCODE_DIV_NUM 0x000000c4
1051 #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP_EN 0x000000c8
1053 #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP_CFG 0x000000cc
1055 #define REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE0 0x000000d0
1057 #define REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE1 0x000000d4
1059 #define REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE2 0x000000d8
1061 #define REG_HDMI_PHY_QSERDES_COM_VCOCAL_DEADMAN_CTRL 0x000000d8
1063 #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE0 0x000000dc
1065 #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE0 0x000000e0
1067 #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE0 0x000000e4
1069 #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE1 0x000000e8
1071 #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE1 0x000000ec
1073 #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE1 0x000000f0
1075 #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE2 0x000000f4
1077 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MINVAL1 0x000000f4
1079 #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE2 0x000000f8
1081 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MINVAL2 0x000000f8
1083 #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE2 0x000000fc
1085 #define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD4 0x000000fc
1087 #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_INITVAL 0x00000100
1089 #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_EN 0x00000104
1091 #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x00000108
1093 #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x0000010c
1095 #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0x00000110
1097 #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE1 0x00000114
1099 #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE2 0x00000118
1101 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAXVAL1 0x00000118
1103 #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE2 0x0000011c
1105 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAXVAL2 0x0000011c
1107 #define REG_HDMI_PHY_QSERDES_COM_RES_TRIM_CONTROL2 0x00000120
1109 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_CTRL 0x00000124
1111 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAP 0x00000128
1113 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE1_MODE0 0x0000012c
1115 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE2_MODE0 0x00000130
1117 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE1_MODE1 0x00000134
1119 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE2_MODE1 0x00000138
1121 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE1_MODE2 0x0000013c
1123 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_INITVAL1 0x0000013c
1125 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE2_MODE2 0x00000140
1127 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_INITVAL2 0x00000140
1129 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_TIMER1 0x00000144
1131 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_TIMER2 0x00000148
1133 #define REG_HDMI_PHY_QSERDES_COM_SAR 0x0000014c
1135 #define REG_HDMI_PHY_QSERDES_COM_SAR_CLK 0x00000150
1137 #define REG_HDMI_PHY_QSERDES_COM_SAR_CODE_OUT_STATUS 0x00000154
1139 #define REG_HDMI_PHY_QSERDES_COM_SAR_CODE_READY_STATUS 0x00000158
1141 #define REG_HDMI_PHY_QSERDES_COM_CMN_STATUS 0x0000015c
1143 #define REG_HDMI_PHY_QSERDES_COM_RESET_SM_STATUS 0x00000160
1145 #define REG_HDMI_PHY_QSERDES_COM_RESTRIM_CODE_STATUS 0x00000164
1147 #define REG_HDMI_PHY_QSERDES_COM_PLLCAL_CODE1_STATUS 0x00000168
1149 #define REG_HDMI_PHY_QSERDES_COM_PLLCAL_CODE2_STATUS 0x0000016c
1151 #define REG_HDMI_PHY_QSERDES_COM_BG_CTRL 0x00000170
1153 #define REG_HDMI_PHY_QSERDES_COM_CLK_SELECT 0x00000174
1155 #define REG_HDMI_PHY_QSERDES_COM_HSCLK_SEL 0x00000178
1157 #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_BINCODE_STATUS 0x0000017c
1159 #define REG_HDMI_PHY_QSERDES_COM_PLL_ANALOG 0x00000180
1161 #define REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV 0x00000184
1163 #define REG_HDMI_PHY_QSERDES_COM_SW_RESET 0x00000188
1165 #define REG_HDMI_PHY_QSERDES_COM_CORE_CLK_EN 0x0000018c
1167 #define REG_HDMI_PHY_QSERDES_COM_C_READY_STATUS 0x00000190
1169 #define REG_HDMI_PHY_QSERDES_COM_CMN_CONFIG 0x00000194
1171 #define REG_HDMI_PHY_QSERDES_COM_CMN_RATE_OVERRIDE 0x00000198
1173 #define REG_HDMI_PHY_QSERDES_COM_SVS_MODE_CLK_SEL 0x0000019c
1175 #define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS0 0x000001a0
1177 #define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS1 0x000001a4
1179 #define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS2 0x000001a8
1181 #define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS3 0x000001ac
1183 #define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS_SEL 0x000001b0
1185 #define REG_HDMI_PHY_QSERDES_COM_CMN_MISC1 0x000001b4
1187 #define REG_HDMI_PHY_QSERDES_COM_CMN_MISC2 0x000001b8
1189 #define REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV_MODE1 0x000001bc
1191 #define REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV_MODE2 0x000001c0
1193 #define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD5 0x000001c4
1195 #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_MODE_LANENO 0x00000000
1197 #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_INVERT 0x00000004
1199 #define REG_HDMI_PHY_QSERDES_TX_LX_CLKBUF_ENABLE 0x00000008
1201 #define REG_HDMI_PHY_QSERDES_TX_LX_CMN_CONTROL_ONE 0x0000000c
1203 #define REG_HDMI_PHY_QSERDES_TX_LX_CMN_CONTROL_TWO 0x00000010
1205 #define REG_HDMI_PHY_QSERDES_TX_LX_CMN_CONTROL_THREE 0x00000014
1207 #define REG_HDMI_PHY_QSERDES_TX_LX_TX_EMP_POST1_LVL 0x00000018
1209 #define REG_HDMI_PHY_QSERDES_TX_LX_TX_POST2_EMPH 0x0000001c
1211 #define REG_HDMI_PHY_QSERDES_TX_LX_TX_BOOST_LVL_UP_DN 0x00000020
1213 #define REG_HDMI_PHY_QSERDES_TX_LX_HP_PD_ENABLES 0x00000024
1215 #define REG_HDMI_PHY_QSERDES_TX_LX_TX_IDLE_LVL_LARGE_AMP 0x00000028
1217 #define REG_HDMI_PHY_QSERDES_TX_LX_TX_DRV_LVL 0x0000002c
1219 #define REG_HDMI_PHY_QSERDES_TX_LX_TX_DRV_LVL_OFFSET 0x00000030
1221 #define REG_HDMI_PHY_QSERDES_TX_LX_RESET_TSYNC_EN 0x00000034
1223 #define REG_HDMI_PHY_QSERDES_TX_LX_PRE_STALL_LDO_BOOST_EN 0x00000038
1225 #define REG_HDMI_PHY_QSERDES_TX_LX_TX_BAND 0x0000003c
1227 #define REG_HDMI_PHY_QSERDES_TX_LX_SLEW_CNTL 0x00000040
1229 #define REG_HDMI_PHY_QSERDES_TX_LX_INTERFACE_SELECT 0x00000044
1231 #define REG_HDMI_PHY_QSERDES_TX_LX_LPB_EN 0x00000048
1233 #define REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_TX 0x0000004c
1235 #define REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_RX 0x00000050
1237 #define REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_OFFSET 0x00000054
1239 #define REG_HDMI_PHY_QSERDES_TX_LX_PERL_LENGTH1 0x00000058
1241 #define REG_HDMI_PHY_QSERDES_TX_LX_PERL_LENGTH2 0x0000005c
1243 #define REG_HDMI_PHY_QSERDES_TX_LX_SERDES_BYP_EN_OUT 0x00000060
1245 #define REG_HDMI_PHY_QSERDES_TX_LX_DEBUG_BUS_SEL 0x00000064
1247 #define REG_HDMI_PHY_QSERDES_TX_LX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN 0x00000068
1249 #define REG_HDMI_PHY_QSERDES_TX_LX_TX_POL_INV 0x0000006c
1251 #define REG_HDMI_PHY_QSERDES_TX_LX_PARRATE_REC_DETECT_IDLE_EN 0x00000070
1253 #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN1 0x00000074
1255 #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN2 0x00000078
1257 #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN3 0x0000007c
1259 #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN4 0x00000080
1261 #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN5 0x00000084
1263 #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN6 0x00000088
1265 #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN7 0x0000008c
1267 #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN8 0x00000090
1269 #define REG_HDMI_PHY_QSERDES_TX_LX_LANE_MODE 0x00000094
1271 #define REG_HDMI_PHY_QSERDES_TX_LX_IDAC_CAL_LANE_MODE 0x00000098
1273 #define REG_HDMI_PHY_QSERDES_TX_LX_IDAC_CAL_LANE_MODE_CONFIGURATION 0x0000009c
1275 #define REG_HDMI_PHY_QSERDES_TX_LX_ATB_SEL1 0x000000a0
1277 #define REG_HDMI_PHY_QSERDES_TX_LX_ATB_SEL2 0x000000a4
1279 #define REG_HDMI_PHY_QSERDES_TX_LX_RCV_DETECT_LVL 0x000000a8
1281 #define REG_HDMI_PHY_QSERDES_TX_LX_RCV_DETECT_LVL_2 0x000000ac
1283 #define REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED1 0x000000b0
1285 #define REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED2 0x000000b4
1287 #define REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED3 0x000000b8
1289 #define REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED4 0x000000bc
1291 #define REG_HDMI_PHY_QSERDES_TX_LX_RESET_GEN 0x000000c0
1293 #define REG_HDMI_PHY_QSERDES_TX_LX_RESET_GEN_MUXES 0x000000c4
1295 #define REG_HDMI_PHY_QSERDES_TX_LX_TRAN_DRVR_EMP_EN 0x000000c8
1297 #define REG_HDMI_PHY_QSERDES_TX_LX_TX_INTERFACE_MODE 0x000000cc
1299 #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_CTRL 0x000000d0
1301 #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_ENCODED_OR_DATA 0x000000d4
1303 #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_1_DIVIDER_BAND2 0x000000d8
1305 #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_2_DIVIDER_BAND2 0x000000dc
1307 #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_3_DIVIDER_BAND2 0x000000e0
1309 #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_4_DIVIDER_BAND2 0x000000e4
1311 #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_1_DIVIDER_BAND0_1 0x000000e8
1313 #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_2_DIVIDER_BAND0_1 0x000000ec
1315 #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_3_DIVIDER_BAND0_1 0x000000f0
1317 #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_4_DIVIDER_BAND0_1 0x000000f4
1319 #define REG_HDMI_PHY_QSERDES_TX_LX_VMODE_CTRL1 0x000000f8
1321 #define REG_HDMI_PHY_QSERDES_TX_LX_VMODE_CTRL2 0x000000fc
1323 #define REG_HDMI_PHY_QSERDES_TX_LX_TX_ALOG_INTF_OBSV_CNTL 0x00000100
1325 #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_STATUS 0x00000104
1327 #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_ERROR_COUNT1 0x00000108
1329 #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_ERROR_COUNT2 0x0000010c
1331 #define REG_HDMI_PHY_QSERDES_TX_LX_TX_ALOG_INTF_OBSV 0x00000110
1334 #endif /* HDMI_XML */