drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c

   1 /*
   2  * Copyright (c) 2014-2015 The Linux Foundation. All rights reserved.
   3  * Copyright (C) 2013 Red Hat
   4  * Author: Rob Clark <robdclark@gmail.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published by
   8  * the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include "mdp5_kms.h"
  20
  21 #include <linux/sort.h>
  22 #include <drm/drm_mode.h>
  23 #include "drm_crtc.h"
  24 #include "drm_crtc_helper.h"
  25 #include "drm_flip_work.h"
  26
  27 #define CURSOR_WIDTH    64
  28 #define CURSOR_HEIGHT   64
  29
  30 #define SSPP_MAX        (SSPP_RGB3 + 1) /* TODO: Add SSPP_MAX in mdp5.xml.h */
  31
  32 struct mdp5_crtc {
  33         struct drm_crtc base;
  34         char name[8];
  35         int id;
  36         bool enabled;
  37
  38         /* layer mixer used for this CRTC (+ its lock): */
  39 #define GET_LM_ID(crtc_id)      ((crtc_id == 3) ? 5 : crtc_id)
  40         int lm;
  41         spinlock_t lm_lock;     /* protect REG_MDP5_LM_* registers */
  42
  43         /* CTL used for this CRTC: */
  44         struct mdp5_ctl *ctl;
  45
  46         /* if there is a pending flip, these will be non-null: */
  47         struct drm_pending_vblank_event *event;
  48
  49         /* Bits have been flushed at the last commit,
  50          * used to decide if a vsync has happened since last commit.
  51          */
  52         u32 flushed_mask;
  53
  54 #define PENDING_CURSOR 0x1
  55 #define PENDING_FLIP   0x2
  56         atomic_t pending;
  57
  58         /* for unref'ing cursor bo's after scanout completes: */
  59         struct drm_flip_work unref_cursor_work;
  60
  61         struct mdp_irq vblank;
  62         struct mdp_irq err;
  63         struct mdp_irq pp_done;
  64
  65         struct completion pp_completion;
  66
  67         bool cmd_mode;
  68
  69         struct {
  70                 /* protect REG_MDP5_LM_CURSOR* registers and cursor scanout_bo*/
  71                 spinlock_t lock;
  72
  73                 /* current cursor being scanned out: */
  74                 struct drm_gem_object *scanout_bo;
  75                 uint32_t width, height;
  76                 uint32_t x, y;
  77         } cursor;
  78 };
  79 #define to_mdp5_crtc(x) container_of(x, struct mdp5_crtc, base)
  80
  81 static struct mdp5_kms *get_kms(struct drm_crtc *crtc)
  82 {
  83         struct msm_drm_private *priv = crtc->dev->dev_private;
  84         return to_mdp5_kms(to_mdp_kms(priv->kms));
  85 }
  86
  87 static void request_pending(struct drm_crtc *crtc, uint32_t pending)
  88 {
  89         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
  90
  91         atomic_or(pending, &mdp5_crtc->pending);
  92         mdp_irq_register(&get_kms(crtc)->base, &mdp5_crtc->vblank);
  93 }
  94
  95 static void request_pp_done_pending(struct drm_crtc *crtc)
  96 {
  97         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
  98         reinit_completion(&mdp5_crtc->pp_completion);
  99 }
 100
 101 static u32 crtc_flush(struct drm_crtc *crtc, u32 flush_mask)
 102 {
 103         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 104
 105         DBG("%s: flush=%08x", mdp5_crtc->name, flush_mask);
 106         return mdp5_ctl_commit(mdp5_crtc->ctl, flush_mask);
 107 }
 108
 109 /*
 110  * flush updates, to make sure hw is updated to new scanout fb,
 111  * so that we can safely queue unref to current fb (ie. next
 112  * vblank we know hw is done w/ previous scanout_fb).
 113  */
 114 static u32 crtc_flush_all(struct drm_crtc *crtc)
 115 {
 116         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 117         struct drm_plane *plane;
 118         uint32_t flush_mask = 0;
 119
 120         /* this should not happen: */
 121         if (WARN_ON(!mdp5_crtc->ctl))
 122                 return 0;
 123
 124         drm_atomic_crtc_for_each_plane(plane, crtc) {
 125                 flush_mask |= mdp5_plane_get_flush(plane);
 126         }
 127
 128         flush_mask |= mdp_ctl_flush_mask_lm(mdp5_crtc->lm);
 129
 130         return crtc_flush(crtc, flush_mask);
 131 }
 132
 133 /* if file!=NULL, this is preclose potential cancel-flip path */
 134 static void complete_flip(struct drm_crtc *crtc, struct drm_file *file)
 135 {
 136         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 137         struct drm_device *dev = crtc->dev;
 138         struct drm_pending_vblank_event *event;
 139         struct drm_plane *plane;
 140         unsigned long flags;
 141
 142         spin_lock_irqsave(&dev->event_lock, flags);
 143         event = mdp5_crtc->event;
 144         if (event) {
 145                 /* if regular vblank case (!file) or if cancel-flip from
 146                  * preclose on file that requested flip, then send the
 147                  * event:
 148                  */
 149                 if (!file || (event->base.file_priv == file)) {
 150                         mdp5_crtc->event = NULL;
 151                         DBG("%s: send event: %p", mdp5_crtc->name, event);
 152                         drm_send_vblank_event(dev, mdp5_crtc->id, event);
 153                 }
 154         }
 155         spin_unlock_irqrestore(&dev->event_lock, flags);
 156
 157         drm_atomic_crtc_for_each_plane(plane, crtc) {
 158                 mdp5_plane_complete_flip(plane);
 159         }
 160
 161         if (mdp5_crtc->ctl && !crtc->state->enable) {
 162                 /* set STAGE_UNUSED for all layers */
 163                 mdp5_ctl_blend(mdp5_crtc->ctl, NULL, 0, 0);
 164                 mdp5_crtc->ctl = NULL;
 165         }
 166 }
 167
 168 static void unref_cursor_worker(struct drm_flip_work *work, void *val)
 169 {
 170         struct mdp5_crtc *mdp5_crtc =
 171                 container_of(work, struct mdp5_crtc, unref_cursor_work);
 172         struct mdp5_kms *mdp5_kms = get_kms(&mdp5_crtc->base);
 173
 174         msm_gem_put_iova(val, mdp5_kms->id);
 175         drm_gem_object_unreference_unlocked(val);
 176 }
 177
 178 static void mdp5_crtc_destroy(struct drm_crtc *crtc)
 179 {
 180         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 181
 182         drm_crtc_cleanup(crtc);
 183         drm_flip_work_cleanup(&mdp5_crtc->unref_cursor_work);
 184
 185         kfree(mdp5_crtc);
 186 }
 187
 188 static bool mdp5_crtc_mode_fixup(struct drm_crtc *crtc,
 189                 const struct drm_display_mode *mode,
 190                 struct drm_display_mode *adjusted_mode)
 191 {
 192         return true;
 193 }
 194
 195 /*
 196  * blend_setup() - blend all the planes of a CRTC
 197  *
 198  * If no base layer is available, border will be enabled as the base layer.
 199  * Otherwise all layers will be blended based on their stage calculated
 200  * in mdp5_crtc_atomic_check.
 201  */
 202 static void blend_setup(struct drm_crtc *crtc)
 203 {
 204         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 205         struct mdp5_kms *mdp5_kms = get_kms(crtc);
 206         struct drm_plane *plane;
 207         const struct mdp5_cfg_hw *hw_cfg;
 208         struct mdp5_plane_state *pstate, *pstates[STAGE_MAX + 1] = {NULL};
 209         const struct mdp_format *format;
 210         uint32_t lm = mdp5_crtc->lm;
 211         uint32_t blend_op, fg_alpha, bg_alpha, ctl_blend_flags = 0;
 212         unsigned long flags;
 213         uint8_t stage[STAGE_MAX + 1];
 214         int i, plane_cnt = 0;
 215 #define blender(stage)  ((stage) - STAGE0)
 216
 217         hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
 218
 219         spin_lock_irqsave(&mdp5_crtc->lm_lock, flags);
 220
 221         /* ctl could be released already when we are shutting down: */
 222         if (!mdp5_crtc->ctl)
 223                 goto out;
 224
 225         /* Collect all plane information */
 226         drm_atomic_crtc_for_each_plane(plane, crtc) {
 227                 pstate = to_mdp5_plane_state(plane->state);
 228                 pstates[pstate->stage] = pstate;
 229                 stage[pstate->stage] = mdp5_plane_pipe(plane);
 230                 plane_cnt++;
 231         }
 232
 233         /*
 234         * If there is no base layer, enable border color.
 235         * Although it's not possbile in current blend logic,
 236         * put it here as a reminder.
 237         */
 238         if (!pstates[STAGE_BASE] && plane_cnt) {
 239                 ctl_blend_flags |= MDP5_CTL_BLEND_OP_FLAG_BORDER_OUT;
 240                 DBG("Border Color is enabled");
 241         }
 242
 243         /* The reset for blending */
 244         for (i = STAGE0; i <= STAGE_MAX; i++) {
 245                 if (!pstates[i])
 246                         continue;
 247
 248                 format = to_mdp_format(
 249                         msm_framebuffer_format(pstates[i]->base.fb));
 250                 plane = pstates[i]->base.plane;
 251                 blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_CONST) |
 252                         MDP5_LM_BLEND_OP_MODE_BG_ALPHA(BG_CONST);
 253                 fg_alpha = pstates[i]->alpha;
 254                 bg_alpha = 0xFF - pstates[i]->alpha;
 255                 DBG("Stage %d fg_alpha %x bg_alpha %x", i, fg_alpha, bg_alpha);
 256
 257                 if (format->alpha_enable && pstates[i]->premultiplied) {
 258                         blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_CONST) |
 259                                 MDP5_LM_BLEND_OP_MODE_BG_ALPHA(FG_PIXEL);
 260                         if (fg_alpha != 0xff) {
 261                                 bg_alpha = fg_alpha;
 262                                 blend_op |=
 263                                         MDP5_LM_BLEND_OP_MODE_BG_MOD_ALPHA |
 264                                         MDP5_LM_BLEND_OP_MODE_BG_INV_MOD_ALPHA;
 265                         } else {
 266                                 blend_op |= MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA;
 267                         }
 268                 } else if (format->alpha_enable) {
 269                         blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_PIXEL) |
 270                                 MDP5_LM_BLEND_OP_MODE_BG_ALPHA(FG_PIXEL);
 271                         if (fg_alpha != 0xff) {
 272                                 bg_alpha = fg_alpha;
 273                                 blend_op |=
 274                                        MDP5_LM_BLEND_OP_MODE_FG_MOD_ALPHA |
 275                                        MDP5_LM_BLEND_OP_MODE_FG_INV_MOD_ALPHA |
 276                                        MDP5_LM_BLEND_OP_MODE_BG_MOD_ALPHA |
 277                                        MDP5_LM_BLEND_OP_MODE_BG_INV_MOD_ALPHA;
 278                         } else {
 279                                 blend_op |= MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA;
 280                         }
 281                 }
 282
 283                 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_OP_MODE(lm,
 284                                 blender(i)), blend_op);
 285                 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_FG_ALPHA(lm,
 286                                 blender(i)), fg_alpha);
 287                 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_BG_ALPHA(lm,
 288                                 blender(i)), bg_alpha);
 289         }
 290
 291         mdp5_ctl_blend(mdp5_crtc->ctl, stage, plane_cnt, ctl_blend_flags);
 292
 293 out:
 294         spin_unlock_irqrestore(&mdp5_crtc->lm_lock, flags);
 295 }
 296
 297 static void mdp5_crtc_mode_set_nofb(struct drm_crtc *crtc)
 298 {
 299         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 300         struct mdp5_kms *mdp5_kms = get_kms(crtc);
 301         unsigned long flags;
 302         struct drm_display_mode *mode;
 303
 304         if (WARN_ON(!crtc->state))
 305                 return;
 306
 307         mode = &crtc->state->adjusted_mode;
 308
 309         DBG("%s: set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x",
 310                         mdp5_crtc->name, mode->base.id, mode->name,
 311                         mode->vrefresh, mode->clock,
 312                         mode->hdisplay, mode->hsync_start,
 313                         mode->hsync_end, mode->htotal,
 314                         mode->vdisplay, mode->vsync_start,
 315                         mode->vsync_end, mode->vtotal,
 316                         mode->type, mode->flags);
 317
 318         spin_lock_irqsave(&mdp5_crtc->lm_lock, flags);
 319         mdp5_write(mdp5_kms, REG_MDP5_LM_OUT_SIZE(mdp5_crtc->lm),
 320                         MDP5_LM_OUT_SIZE_WIDTH(mode->hdisplay) |
 321                         MDP5_LM_OUT_SIZE_HEIGHT(mode->vdisplay));
 322         spin_unlock_irqrestore(&mdp5_crtc->lm_lock, flags);
 323 }
 324
 325 static void mdp5_crtc_disable(struct drm_crtc *crtc)
 326 {
 327         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 328         struct mdp5_kms *mdp5_kms = get_kms(crtc);
 329
 330         DBG("%s", mdp5_crtc->name);
 331
 332         if (WARN_ON(!mdp5_crtc->enabled))
 333                 return;
 334
 335         if (mdp5_crtc->cmd_mode)
 336                 mdp_irq_unregister(&mdp5_kms->base, &mdp5_crtc->pp_done);
 337
 338         mdp_irq_unregister(&mdp5_kms->base, &mdp5_crtc->err);
 339         mdp5_disable(mdp5_kms);
 340
 341         mdp5_crtc->enabled = false;
 342 }
 343
 344 static void mdp5_crtc_enable(struct drm_crtc *crtc)
 345 {
 346         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 347         struct mdp5_kms *mdp5_kms = get_kms(crtc);
 348
 349         DBG("%s", mdp5_crtc->name);
 350
 351         if (WARN_ON(mdp5_crtc->enabled))
 352                 return;
 353
 354         mdp5_enable(mdp5_kms);
 355         mdp_irq_register(&mdp5_kms->base, &mdp5_crtc->err);
 356
 357         if (mdp5_crtc->cmd_mode)
 358                 mdp_irq_register(&mdp5_kms->base, &mdp5_crtc->pp_done);
 359
 360         mdp5_crtc->enabled = true;
 361 }
 362
 363 struct plane_state {
 364         struct drm_plane *plane;
 365         struct mdp5_plane_state *state;
 366 };
 367
 368 static int pstate_cmp(const void *a, const void *b)
 369 {
 370         struct plane_state *pa = (struct plane_state *)a;
 371         struct plane_state *pb = (struct plane_state *)b;
 372         return pa->state->zpos - pb->state->zpos;
 373 }
 374
 375 static int mdp5_crtc_atomic_check(struct drm_crtc *crtc,
 376                 struct drm_crtc_state *state)
 377 {
 378         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 379         struct mdp5_kms *mdp5_kms = get_kms(crtc);
 380         struct drm_plane *plane;
 381         struct drm_device *dev = crtc->dev;
 382         struct plane_state pstates[STAGE_MAX + 1];
 383         const struct mdp5_cfg_hw *hw_cfg;
 384         int cnt = 0, i;
 385
 386         DBG("%s: check", mdp5_crtc->name);
 387
 388         /* verify that there are not too many planes attached to crtc
 389          * and that we don't have conflicting mixer stages:
 390          */
 391         hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
 392         drm_atomic_crtc_state_for_each_plane(plane, state) {
 393                 struct drm_plane_state *pstate;
 394                 if (cnt >= (hw_cfg->lm.nb_stages)) {
 395                         dev_err(dev->dev, "too many planes!\n");
 396                         return -EINVAL;
 397                 }
 398
 399                 pstate = state->state->plane_states[drm_plane_index(plane)];
 400
 401                 /* plane might not have changed, in which case take
 402                  * current state:
 403                  */
 404                 if (!pstate)
 405                         pstate = plane->state;
 406                 pstates[cnt].plane = plane;
 407                 pstates[cnt].state = to_mdp5_plane_state(pstate);
 408
 409                 cnt++;
 410         }
 411
 412         /* assign a stage based on sorted zpos property */
 413         sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL);
 414
 415         for (i = 0; i < cnt; i++) {
 416                 pstates[i].state->stage = STAGE_BASE + i;
 417                 DBG("%s: assign pipe %s on stage=%d", mdp5_crtc->name,
 418                                 pipe2name(mdp5_plane_pipe(pstates[i].plane)),
 419                                 pstates[i].state->stage);
 420         }
 421
 422         return 0;
 423 }
 424
 425 static void mdp5_crtc_atomic_begin(struct drm_crtc *crtc,
 426                                    struct drm_crtc_state *old_crtc_state)
 427 {
 428         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 429         DBG("%s: begin", mdp5_crtc->name);
 430 }
 431
 432 static void mdp5_crtc_atomic_flush(struct drm_crtc *crtc,
 433                                    struct drm_crtc_state *old_crtc_state)
 434 {
 435         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 436         struct drm_device *dev = crtc->dev;
 437         unsigned long flags;
 438
 439         DBG("%s: event: %p", mdp5_crtc->name, crtc->state->event);
 440
 441         WARN_ON(mdp5_crtc->event);
 442
 443         spin_lock_irqsave(&dev->event_lock, flags);
 444         mdp5_crtc->event = crtc->state->event;
 445         spin_unlock_irqrestore(&dev->event_lock, flags);
 446
 447         /*
 448          * If no CTL has been allocated in mdp5_crtc_atomic_check(),
 449          * it means we are trying to flush a CRTC whose state is disabled:
 450          * nothing else needs to be done.
 451          */
 452         if (unlikely(!mdp5_crtc->ctl))
 453                 return;
 454
 455         blend_setup(crtc);
 456
 457         /* PP_DONE irq is only used by command mode for now.
 458          * It is better to request pending before FLUSH and START trigger
 459          * to make sure no pp_done irq missed.
 460          * This is safe because no pp_done will happen before SW trigger
 461          * in command mode.
 462          */
 463         if (mdp5_crtc->cmd_mode)
 464                 request_pp_done_pending(crtc);
 465
 466         mdp5_crtc->flushed_mask = crtc_flush_all(crtc);
 467
 468         request_pending(crtc, PENDING_FLIP);
 469 }
 470
 471 static int mdp5_crtc_set_property(struct drm_crtc *crtc,
 472                 struct drm_property *property, uint64_t val)
 473 {
 474         // XXX
 475         return -EINVAL;
 476 }
 477
 478 static void get_roi(struct drm_crtc *crtc, uint32_t *roi_w, uint32_t *roi_h)
 479 {
 480         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 481         uint32_t xres = crtc->mode.hdisplay;
 482         uint32_t yres = crtc->mode.vdisplay;
 483
 484         /*
 485          * Cursor Region Of Interest (ROI) is a plane read from cursor
 486          * buffer to render. The ROI region is determined by the visibility of
 487          * the cursor point. In the default Cursor image the cursor point will
 488          * be at the top left of the cursor image, unless it is specified
 489          * otherwise using hotspot feature.
 490          *
 491          * If the cursor point reaches the right (xres - x < cursor.width) or
 492          * bottom (yres - y < cursor.height) boundary of the screen, then ROI
 493          * width and ROI height need to be evaluated to crop the cursor image
 494          * accordingly.
 495          * (xres-x) will be new cursor width when x > (xres - cursor.width)
 496          * (yres-y) will be new cursor height when y > (yres - cursor.height)
 497          */
 498         *roi_w = min(mdp5_crtc->cursor.width, xres -
 499                         mdp5_crtc->cursor.x);
 500         *roi_h = min(mdp5_crtc->cursor.height, yres -
 501                         mdp5_crtc->cursor.y);
 502 }
 503
 504 static int mdp5_crtc_cursor_set(struct drm_crtc *crtc,
 505                 struct drm_file *file, uint32_t handle,
 506                 uint32_t width, uint32_t height)
 507 {
 508         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 509         struct drm_device *dev = crtc->dev;
 510         struct mdp5_kms *mdp5_kms = get_kms(crtc);
 511         struct drm_gem_object *cursor_bo, *old_bo = NULL;
 512         uint32_t blendcfg, cursor_addr, stride;
 513         int ret, bpp, lm;
 514         unsigned int depth;
 515         enum mdp5_cursor_alpha cur_alpha = CURSOR_ALPHA_PER_PIXEL;
 516         uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0);
 517         uint32_t roi_w, roi_h;
 518         bool cursor_enable = true;
 519         unsigned long flags;
 520
 521         if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) {
 522                 dev_err(dev->dev, "bad cursor size: %dx%d\n", width, height);
 523                 return -EINVAL;
 524         }
 525
 526         if (NULL == mdp5_crtc->ctl)
 527                 return -EINVAL;
 528
 529         if (!handle) {
 530                 DBG("Cursor off");
 531                 cursor_enable = false;
 532                 goto set_cursor;
 533         }
 534
 535         cursor_bo = drm_gem_object_lookup(dev, file, handle);
 536         if (!cursor_bo)
 537                 return -ENOENT;
 538
 539         ret = msm_gem_get_iova(cursor_bo, mdp5_kms->id, &cursor_addr);
 540         if (ret)
 541                 return -EINVAL;
 542
 543         lm = mdp5_crtc->lm;
 544         drm_fb_get_bpp_depth(DRM_FORMAT_ARGB8888, &depth, &bpp);
 545         stride = width * (bpp >> 3);
 546
 547         spin_lock_irqsave(&mdp5_crtc->cursor.lock, flags);
 548         old_bo = mdp5_crtc->cursor.scanout_bo;
 549
 550         mdp5_crtc->cursor.scanout_bo = cursor_bo;
 551         mdp5_crtc->cursor.width = width;
 552         mdp5_crtc->cursor.height = height;
 553
 554         get_roi(crtc, &roi_w, &roi_h);
 555
 556         mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_STRIDE(lm), stride);
 557         mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_FORMAT(lm),
 558                         MDP5_LM_CURSOR_FORMAT_FORMAT(CURSOR_FMT_ARGB8888));
 559         mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_IMG_SIZE(lm),
 560                         MDP5_LM_CURSOR_IMG_SIZE_SRC_H(height) |
 561                         MDP5_LM_CURSOR_IMG_SIZE_SRC_W(width));
 562         mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_SIZE(lm),
 563                         MDP5_LM_CURSOR_SIZE_ROI_H(roi_h) |
 564                         MDP5_LM_CURSOR_SIZE_ROI_W(roi_w));
 565         mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_BASE_ADDR(lm), cursor_addr);
 566
 567         blendcfg = MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_EN;
 568         blendcfg |= MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL(cur_alpha);
 569         mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_BLEND_CONFIG(lm), blendcfg);
 570
 571         spin_unlock_irqrestore(&mdp5_crtc->cursor.lock, flags);
 572
 573 set_cursor:
 574         ret = mdp5_ctl_set_cursor(mdp5_crtc->ctl, 0, cursor_enable);
 575         if (ret) {
 576                 dev_err(dev->dev, "failed to %sable cursor: %d\n",
 577                                 cursor_enable ? "en" : "dis", ret);
 578                 goto end;
 579         }
 580
 581         crtc_flush(crtc, flush_mask);
 582
 583 end:
 584         if (old_bo) {
 585                 drm_flip_work_queue(&mdp5_crtc->unref_cursor_work, old_bo);
 586                 /* enable vblank to complete cursor work: */
 587                 request_pending(crtc, PENDING_CURSOR);
 588         }
 589         return ret;
 590 }
 591
 592 static int mdp5_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
 593 {
 594         struct mdp5_kms *mdp5_kms = get_kms(crtc);
 595         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 596         uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0);
 597         uint32_t roi_w;
 598         uint32_t roi_h;
 599         unsigned long flags;
 600
 601         /* In case the CRTC is disabled, just drop the cursor update */
 602         if (unlikely(!crtc->state->enable))
 603                 return 0;
 604
 605         mdp5_crtc->cursor.x = x = max(x, 0);
 606         mdp5_crtc->cursor.y = y = max(y, 0);
 607
 608         get_roi(crtc, &roi_w, &roi_h);
 609
 610         spin_lock_irqsave(&mdp5_crtc->cursor.lock, flags);
 611         mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_SIZE(mdp5_crtc->lm),
 612                         MDP5_LM_CURSOR_SIZE_ROI_H(roi_h) |
 613                         MDP5_LM_CURSOR_SIZE_ROI_W(roi_w));
 614         mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_START_XY(mdp5_crtc->lm),
 615                         MDP5_LM_CURSOR_START_XY_Y_START(y) |
 616                         MDP5_LM_CURSOR_START_XY_X_START(x));
 617         spin_unlock_irqrestore(&mdp5_crtc->cursor.lock, flags);
 618
 619         crtc_flush(crtc, flush_mask);
 620
 621         return 0;
 622 }
 623
 624 static const struct drm_crtc_funcs mdp5_crtc_funcs = {
 625         .set_config = drm_atomic_helper_set_config,
 626         .destroy = mdp5_crtc_destroy,
 627         .page_flip = drm_atomic_helper_page_flip,
 628         .set_property = mdp5_crtc_set_property,
 629         .reset = drm_atomic_helper_crtc_reset,
 630         .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
 631         .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
 632         .cursor_set = mdp5_crtc_cursor_set,
 633         .cursor_move = mdp5_crtc_cursor_move,
 634 };
 635
 636 static const struct drm_crtc_helper_funcs mdp5_crtc_helper_funcs = {
 637         .mode_fixup = mdp5_crtc_mode_fixup,
 638         .mode_set_nofb = mdp5_crtc_mode_set_nofb,
 639         .disable = mdp5_crtc_disable,
 640         .enable = mdp5_crtc_enable,
 641         .atomic_check = mdp5_crtc_atomic_check,
 642         .atomic_begin = mdp5_crtc_atomic_begin,
 643         .atomic_flush = mdp5_crtc_atomic_flush,
 644 };
 645
 646 static void mdp5_crtc_vblank_irq(struct mdp_irq *irq, uint32_t irqstatus)
 647 {
 648         struct mdp5_crtc *mdp5_crtc = container_of(irq, struct mdp5_crtc, vblank);
 649         struct drm_crtc *crtc = &mdp5_crtc->base;
 650         struct msm_drm_private *priv = crtc->dev->dev_private;
 651         unsigned pending;
 652
 653         mdp_irq_unregister(&get_kms(crtc)->base, &mdp5_crtc->vblank);
 654
 655         pending = atomic_xchg(&mdp5_crtc->pending, 0);
 656
 657         if (pending & PENDING_FLIP) {
 658                 complete_flip(crtc, NULL);
 659         }
 660
 661         if (pending & PENDING_CURSOR)
 662                 drm_flip_work_commit(&mdp5_crtc->unref_cursor_work, priv->wq);
 663 }
 664
 665 static void mdp5_crtc_err_irq(struct mdp_irq *irq, uint32_t irqstatus)
 666 {
 667         struct mdp5_crtc *mdp5_crtc = container_of(irq, struct mdp5_crtc, err);
 668
 669         DBG("%s: error: %08x", mdp5_crtc->name, irqstatus);
 670 }
 671
 672 static void mdp5_crtc_pp_done_irq(struct mdp_irq *irq, uint32_t irqstatus)
 673 {
 674         struct mdp5_crtc *mdp5_crtc = container_of(irq, struct mdp5_crtc,
 675                                                                 pp_done);
 676
 677         complete(&mdp5_crtc->pp_completion);
 678 }
 679
 680 static void mdp5_crtc_wait_for_pp_done(struct drm_crtc *crtc)
 681 {
 682         struct drm_device *dev = crtc->dev;
 683         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 684         int ret;
 685
 686         ret = wait_for_completion_timeout(&mdp5_crtc->pp_completion,
 687                                                 msecs_to_jiffies(50));
 688         if (ret == 0)
 689                 dev_warn(dev->dev, "pp done time out, lm=%d\n", mdp5_crtc->lm);
 690 }
 691
 692 static void mdp5_crtc_wait_for_flush_done(struct drm_crtc *crtc)
 693 {
 694         struct drm_device *dev = crtc->dev;
 695         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 696         int ret;
 697
 698         /* Should not call this function if crtc is disabled. */
 699         if (!mdp5_crtc->ctl)
 700                 return;
 701
 702         ret = drm_crtc_vblank_get(crtc);
 703         if (ret)
 704                 return;
 705
 706         ret = wait_event_timeout(dev->vblank[drm_crtc_index(crtc)].queue,
 707                 ((mdp5_ctl_get_commit_status(mdp5_crtc->ctl) &
 708                 mdp5_crtc->flushed_mask) == 0),
 709                 msecs_to_jiffies(50));
 710         if (ret <= 0)
 711                 dev_warn(dev->dev, "vblank time out, crtc=%d\n", mdp5_crtc->id);
 712
 713         mdp5_crtc->flushed_mask = 0;
 714
 715         drm_crtc_vblank_put(crtc);
 716 }
 717
 718 uint32_t mdp5_crtc_vblank(struct drm_crtc *crtc)
 719 {
 720         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 721         return mdp5_crtc->vblank.irqmask;
 722 }
 723
 724 void mdp5_crtc_cancel_pending_flip(struct drm_crtc *crtc, struct drm_file *file)
 725 {
 726         DBG("cancel: %p", file);
 727         complete_flip(crtc, file);
 728 }
 729
 730 void mdp5_crtc_set_pipeline(struct drm_crtc *crtc,
 731                 struct mdp5_interface *intf, struct mdp5_ctl *ctl)
 732 {
 733         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 734         struct mdp5_kms *mdp5_kms = get_kms(crtc);
 735         int lm = mdp5_crtc_get_lm(crtc);
 736
 737         /* now that we know what irq's we want: */
 738         mdp5_crtc->err.irqmask = intf2err(intf->num);
 739         mdp5_crtc->vblank.irqmask = intf2vblank(lm, intf);
 740
 741         if ((intf->type == INTF_DSI) &&
 742                 (intf->mode == MDP5_INTF_DSI_MODE_COMMAND)) {
 743                 mdp5_crtc->pp_done.irqmask = lm2ppdone(lm);
 744                 mdp5_crtc->pp_done.irq = mdp5_crtc_pp_done_irq;
 745                 mdp5_crtc->cmd_mode = true;
 746         } else {
 747                 mdp5_crtc->pp_done.irqmask = 0;
 748                 mdp5_crtc->pp_done.irq = NULL;
 749                 mdp5_crtc->cmd_mode = false;
 750         }
 751
 752         mdp_irq_update(&mdp5_kms->base);
 753
 754         mdp5_crtc->ctl = ctl;
 755         mdp5_ctl_set_pipeline(ctl, intf, lm);
 756 }
 757
 758 int mdp5_crtc_get_lm(struct drm_crtc *crtc)
 759 {
 760         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 761         return WARN_ON(!crtc) ? -EINVAL : mdp5_crtc->lm;
 762 }
 763
 764 void mdp5_crtc_wait_for_commit_done(struct drm_crtc *crtc)
 765 {
 766         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 767
 768         if (mdp5_crtc->cmd_mode)
 769                 mdp5_crtc_wait_for_pp_done(crtc);
 770         else
 771                 mdp5_crtc_wait_for_flush_done(crtc);
 772 }
 773
 774 /* initialize crtc */
 775 struct drm_crtc *mdp5_crtc_init(struct drm_device *dev,
 776                 struct drm_plane *plane, int id)
 777 {
 778         struct drm_crtc *crtc = NULL;
 779         struct mdp5_crtc *mdp5_crtc;
 780
 781         mdp5_crtc = kzalloc(sizeof(*mdp5_crtc), GFP_KERNEL);
 782         if (!mdp5_crtc)
 783                 return ERR_PTR(-ENOMEM);
 784
 785         crtc = &mdp5_crtc->base;
 786
 787         mdp5_crtc->id = id;
 788         mdp5_crtc->lm = GET_LM_ID(id);
 789
 790         spin_lock_init(&mdp5_crtc->lm_lock);
 791         spin_lock_init(&mdp5_crtc->cursor.lock);
 792         init_completion(&mdp5_crtc->pp_completion);
 793
 794         mdp5_crtc->vblank.irq = mdp5_crtc_vblank_irq;
 795         mdp5_crtc->err.irq = mdp5_crtc_err_irq;
 796
 797         snprintf(mdp5_crtc->name, sizeof(mdp5_crtc->name), "%s:%d",
 798                         pipe2name(mdp5_plane_pipe(plane)), id);
 799
 800         drm_crtc_init_with_planes(dev, crtc, plane, NULL, &mdp5_crtc_funcs,
 801                                   NULL);
 802
 803         drm_flip_work_init(&mdp5_crtc->unref_cursor_work,
 804                         "unref cursor", unref_cursor_worker);
 805
 806         drm_crtc_helper_add(crtc, &mdp5_crtc_helper_funcs);
 807         plane->crtc = crtc;
 808
 809         return crtc;
 810 }