2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published by
8 * the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
24 static const char *iommu_ports[] = {
28 static int mdp5_hw_init(struct msm_kms *kms)
30 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
31 struct drm_device *dev = mdp5_kms->dev;
34 pm_runtime_get_sync(dev->dev);
36 /* Magic unknown register writes:
38 * W VBIF:0x004 00000001 (mdss_mdp.c:839)
39 * W MDP5:0x2e0 0xe9 (mdss_mdp.c:839)
40 * W MDP5:0x2e4 0x55 (mdss_mdp.c:839)
41 * W MDP5:0x3ac 0xc0000ccc (mdss_mdp.c:839)
42 * W MDP5:0x3b4 0xc0000ccc (mdss_mdp.c:839)
43 * W MDP5:0x3bc 0xcccccc (mdss_mdp.c:839)
44 * W MDP5:0x4a8 0xcccc0c0 (mdss_mdp.c:839)
45 * W MDP5:0x4b0 0xccccc0c0 (mdss_mdp.c:839)
46 * W MDP5:0x4b8 0xccccc000 (mdss_mdp.c:839)
48 * Downstream fbdev driver gets these register offsets/values
49 * from DT.. not really sure what these registers are or if
50 * different values for different boards/SoC's, etc. I guess
51 * they are the golden registers.
53 * Not setting these does not seem to cause any problem. But
54 * we may be getting lucky with the bootloader initializing
55 * them for us. OTOH, if we can always count on the bootloader
56 * setting the golden registers, then perhaps we don't need to
60 spin_lock_irqsave(&mdp5_kms->resource_lock, flags);
61 mdp5_write(mdp5_kms, REG_MDP5_DISP_INTF_SEL, 0);
62 spin_unlock_irqrestore(&mdp5_kms->resource_lock, flags);
64 mdp5_ctlm_hw_reset(mdp5_kms->ctl_priv);
66 pm_runtime_put_sync(dev->dev);
71 static long mdp5_round_pixclk(struct msm_kms *kms, unsigned long rate,
72 struct drm_encoder *encoder)
77 static void mdp5_preclose(struct msm_kms *kms, struct drm_file *file)
79 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
80 struct msm_drm_private *priv = mdp5_kms->dev->dev_private;
83 for (i = 0; i < priv->num_crtcs; i++)
84 mdp5_crtc_cancel_pending_flip(priv->crtcs[i], file);
87 static void mdp5_destroy(struct msm_kms *kms)
89 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
90 struct msm_mmu *mmu = mdp5_kms->mmu;
91 void *smp = mdp5_kms->smp_priv;
92 void *cfg = mdp5_kms->cfg_priv;
93 void *ctl = mdp5_kms->ctl_priv;
95 mdp5_irq_domain_fini(mdp5_kms);
98 mmu->funcs->detach(mmu, iommu_ports, ARRAY_SIZE(iommu_ports));
99 mmu->funcs->destroy(mmu);
102 mdp5_ctlm_destroy(ctl);
104 mdp5_smp_destroy(smp);
106 mdp5_cfg_destroy(cfg);
111 static const struct mdp_kms_funcs kms_funcs = {
113 .hw_init = mdp5_hw_init,
114 .irq_preinstall = mdp5_irq_preinstall,
115 .irq_postinstall = mdp5_irq_postinstall,
116 .irq_uninstall = mdp5_irq_uninstall,
118 .enable_vblank = mdp5_enable_vblank,
119 .disable_vblank = mdp5_disable_vblank,
120 .get_format = mdp_get_format,
121 .round_pixclk = mdp5_round_pixclk,
122 .preclose = mdp5_preclose,
123 .destroy = mdp5_destroy,
125 .set_irqmask = mdp5_set_irqmask,
128 int mdp5_disable(struct mdp5_kms *mdp5_kms)
132 clk_disable_unprepare(mdp5_kms->ahb_clk);
133 clk_disable_unprepare(mdp5_kms->axi_clk);
134 clk_disable_unprepare(mdp5_kms->core_clk);
135 clk_disable_unprepare(mdp5_kms->lut_clk);
140 int mdp5_enable(struct mdp5_kms *mdp5_kms)
144 clk_prepare_enable(mdp5_kms->ahb_clk);
145 clk_prepare_enable(mdp5_kms->axi_clk);
146 clk_prepare_enable(mdp5_kms->core_clk);
147 clk_prepare_enable(mdp5_kms->lut_clk);
152 static int modeset_init(struct mdp5_kms *mdp5_kms)
154 static const enum mdp5_pipe crtcs[] = {
155 SSPP_RGB0, SSPP_RGB1, SSPP_RGB2, SSPP_RGB3,
157 static const enum mdp5_pipe pub_planes[] = {
158 SSPP_VIG0, SSPP_VIG1, SSPP_VIG2, SSPP_VIG3,
160 struct drm_device *dev = mdp5_kms->dev;
161 struct msm_drm_private *priv = dev->dev_private;
162 struct drm_encoder *encoder;
163 const struct mdp5_cfg_hw *hw_cfg;
166 hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg_priv);
168 /* register our interrupt-controller for hdmi/eDP/dsi/etc
169 * to use for irqs routed through mdp:
171 ret = mdp5_irq_domain_init(mdp5_kms);
175 /* construct CRTCs and their private planes: */
176 for (i = 0; i < hw_cfg->pipe_rgb.count; i++) {
177 struct drm_plane *plane;
178 struct drm_crtc *crtc;
180 plane = mdp5_plane_init(dev, crtcs[i], true,
181 hw_cfg->pipe_rgb.base[i]);
183 ret = PTR_ERR(plane);
184 dev_err(dev->dev, "failed to construct plane for %s (%d)\n",
185 pipe2name(crtcs[i]), ret);
189 crtc = mdp5_crtc_init(dev, plane, i);
192 dev_err(dev->dev, "failed to construct crtc for %s (%d)\n",
193 pipe2name(crtcs[i]), ret);
196 priv->crtcs[priv->num_crtcs++] = crtc;
199 /* Construct public planes: */
200 for (i = 0; i < hw_cfg->pipe_vig.count; i++) {
201 struct drm_plane *plane;
203 plane = mdp5_plane_init(dev, pub_planes[i], false,
204 hw_cfg->pipe_vig.base[i]);
206 ret = PTR_ERR(plane);
207 dev_err(dev->dev, "failed to construct %s plane: %d\n",
208 pipe2name(pub_planes[i]), ret);
213 /* Construct encoder for HDMI: */
214 encoder = mdp5_encoder_init(dev, 3, INTF_HDMI);
215 if (IS_ERR(encoder)) {
216 dev_err(dev->dev, "failed to construct encoder\n");
217 ret = PTR_ERR(encoder);
221 /* NOTE: the vsync and error irq's are actually associated with
222 * the INTF/encoder.. the easiest way to deal with this (ie. what
223 * we do now) is assume a fixed relationship between crtc's and
224 * encoders. I'm not sure if there is ever a need to more freely
225 * assign crtcs to encoders, but if there is then we need to take
226 * care of error and vblank irq's that the crtc has registered,
227 * and also update user-requested vblank_mask.
229 encoder->possible_crtcs = BIT(0);
230 mdp5_crtc_set_intf(priv->crtcs[0], 3, INTF_HDMI);
232 priv->encoders[priv->num_encoders++] = encoder;
234 /* Construct bridge/connector for HDMI: */
236 ret = hdmi_modeset_init(priv->hdmi, dev, encoder);
238 dev_err(dev->dev, "failed to initialize HDMI: %d\n", ret);
249 static void read_hw_revision(struct mdp5_kms *mdp5_kms,
250 uint32_t *major, uint32_t *minor)
254 mdp5_enable(mdp5_kms);
255 version = mdp5_read(mdp5_kms, REG_MDP5_MDP_VERSION);
256 mdp5_disable(mdp5_kms);
258 *major = FIELD(version, MDP5_MDP_VERSION_MAJOR);
259 *minor = FIELD(version, MDP5_MDP_VERSION_MINOR);
261 DBG("MDP5 version v%d.%d", *major, *minor);
264 static int get_clk(struct platform_device *pdev, struct clk **clkp,
267 struct device *dev = &pdev->dev;
268 struct clk *clk = devm_clk_get(dev, name);
270 dev_err(dev, "failed to get %s (%ld)\n", name, PTR_ERR(clk));
277 struct msm_kms *mdp5_kms_init(struct drm_device *dev)
279 struct platform_device *pdev = dev->platformdev;
280 struct mdp5_cfg *config;
281 struct mdp5_kms *mdp5_kms;
282 struct msm_kms *kms = NULL;
284 uint32_t major, minor;
288 mdp5_kms = kzalloc(sizeof(*mdp5_kms), GFP_KERNEL);
290 dev_err(dev->dev, "failed to allocate kms\n");
295 spin_lock_init(&mdp5_kms->resource_lock);
297 mdp_kms_init(&mdp5_kms->base, &kms_funcs);
299 kms = &mdp5_kms->base.base;
303 mdp5_kms->mmio = msm_ioremap(pdev, "mdp_phys", "MDP5");
304 if (IS_ERR(mdp5_kms->mmio)) {
305 ret = PTR_ERR(mdp5_kms->mmio);
309 mdp5_kms->vbif = msm_ioremap(pdev, "vbif_phys", "VBIF");
310 if (IS_ERR(mdp5_kms->vbif)) {
311 ret = PTR_ERR(mdp5_kms->vbif);
315 mdp5_kms->vdd = devm_regulator_get(&pdev->dev, "vdd");
316 if (IS_ERR(mdp5_kms->vdd)) {
317 ret = PTR_ERR(mdp5_kms->vdd);
321 ret = regulator_enable(mdp5_kms->vdd);
323 dev_err(dev->dev, "failed to enable regulator vdd: %d\n", ret);
327 ret = get_clk(pdev, &mdp5_kms->axi_clk, "bus_clk");
330 ret = get_clk(pdev, &mdp5_kms->ahb_clk, "iface_clk");
333 ret = get_clk(pdev, &mdp5_kms->src_clk, "core_clk_src");
336 ret = get_clk(pdev, &mdp5_kms->core_clk, "core_clk");
339 ret = get_clk(pdev, &mdp5_kms->lut_clk, "lut_clk");
342 ret = get_clk(pdev, &mdp5_kms->vsync_clk, "vsync_clk");
346 /* we need to set a default rate before enabling. Set a safe
347 * rate first, then figure out hw revision, and then set a
350 clk_set_rate(mdp5_kms->src_clk, 200000000);
352 read_hw_revision(mdp5_kms, &major, &minor);
353 priv = mdp5_cfg_init(mdp5_kms, major, minor);
358 mdp5_kms->cfg_priv = priv;
359 config = mdp5_cfg_get_config(mdp5_kms->cfg_priv);
361 /* TODO: compute core clock rate at runtime */
362 clk_set_rate(mdp5_kms->src_clk, config->hw->max_clk);
364 priv = mdp5_smp_init(mdp5_kms->dev, &config->hw->smp);
369 mdp5_kms->smp_priv = priv;
371 priv = mdp5_ctlm_init(dev, mdp5_kms->mmio, config->hw);
376 mdp5_kms->ctl_priv = priv;
378 /* make sure things are off before attaching iommu (bootloader could
379 * have left things on, in which case we'll start getting faults if
382 mdp5_enable(mdp5_kms);
383 for (i = 0; i < config->hw->intf.count; i++)
384 mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(i), 0);
385 mdp5_disable(mdp5_kms);
388 if (config->platform.iommu) {
389 mmu = msm_iommu_new(&pdev->dev, config->platform.iommu);
392 dev_err(dev->dev, "failed to init iommu: %d\n", ret);
396 ret = mmu->funcs->attach(mmu, iommu_ports,
397 ARRAY_SIZE(iommu_ports));
399 dev_err(dev->dev, "failed to attach iommu: %d\n", ret);
400 mmu->funcs->destroy(mmu);
404 dev_info(dev->dev, "no iommu, fallback to phys "
405 "contig buffers for scanout\n");
410 mdp5_kms->id = msm_register_mmu(dev, mmu);
411 if (mdp5_kms->id < 0) {
413 dev_err(dev->dev, "failed to register mdp5 iommu: %d\n", ret);
417 ret = modeset_init(mdp5_kms);
419 dev_err(dev->dev, "modeset_init failed: %d\n", ret);