2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published by
8 * the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
24 static const char *iommu_ports[] = {
28 static int mdp5_hw_init(struct msm_kms *kms)
30 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
31 struct drm_device *dev = mdp5_kms->dev;
34 pm_runtime_get_sync(dev->dev);
36 /* Magic unknown register writes:
38 * W VBIF:0x004 00000001 (mdss_mdp.c:839)
39 * W MDP5:0x2e0 0xe9 (mdss_mdp.c:839)
40 * W MDP5:0x2e4 0x55 (mdss_mdp.c:839)
41 * W MDP5:0x3ac 0xc0000ccc (mdss_mdp.c:839)
42 * W MDP5:0x3b4 0xc0000ccc (mdss_mdp.c:839)
43 * W MDP5:0x3bc 0xcccccc (mdss_mdp.c:839)
44 * W MDP5:0x4a8 0xcccc0c0 (mdss_mdp.c:839)
45 * W MDP5:0x4b0 0xccccc0c0 (mdss_mdp.c:839)
46 * W MDP5:0x4b8 0xccccc000 (mdss_mdp.c:839)
48 * Downstream fbdev driver gets these register offsets/values
49 * from DT.. not really sure what these registers are or if
50 * different values for different boards/SoC's, etc. I guess
51 * they are the golden registers.
53 * Not setting these does not seem to cause any problem. But
54 * we may be getting lucky with the bootloader initializing
55 * them for us. OTOH, if we can always count on the bootloader
56 * setting the golden registers, then perhaps we don't need to
60 spin_lock_irqsave(&mdp5_kms->resource_lock, flags);
61 mdp5_write(mdp5_kms, REG_MDP5_MDP_DISP_INTF_SEL(0), 0);
62 spin_unlock_irqrestore(&mdp5_kms->resource_lock, flags);
64 mdp5_ctlm_hw_reset(mdp5_kms->ctlm);
66 pm_runtime_put_sync(dev->dev);
71 static void mdp5_prepare_commit(struct msm_kms *kms, struct drm_atomic_state *state)
73 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
74 mdp5_enable(mdp5_kms);
77 static void mdp5_complete_commit(struct msm_kms *kms, struct drm_atomic_state *state)
80 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
81 int nplanes = mdp5_kms->dev->mode_config.num_total_plane;
83 for (i = 0; i < nplanes; i++) {
84 struct drm_plane *plane = state->planes[i];
85 struct drm_plane_state *plane_state = state->plane_states[i];
90 mdp5_plane_complete_commit(plane, plane_state);
93 mdp5_disable(mdp5_kms);
96 static void mdp5_wait_for_crtc_commit_done(struct msm_kms *kms,
97 struct drm_crtc *crtc)
99 mdp5_crtc_wait_for_commit_done(crtc);
102 static long mdp5_round_pixclk(struct msm_kms *kms, unsigned long rate,
103 struct drm_encoder *encoder)
108 static int mdp5_set_split_display(struct msm_kms *kms,
109 struct drm_encoder *encoder,
110 struct drm_encoder *slave_encoder,
114 return mdp5_cmd_encoder_set_split_display(encoder,
117 return mdp5_encoder_set_split_display(encoder, slave_encoder);
120 static void mdp5_destroy(struct msm_kms *kms)
122 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
123 struct msm_mmu *mmu = mdp5_kms->mmu;
125 mdp5_irq_domain_fini(mdp5_kms);
128 mmu->funcs->detach(mmu, iommu_ports, ARRAY_SIZE(iommu_ports));
129 mmu->funcs->destroy(mmu);
133 mdp5_ctlm_destroy(mdp5_kms->ctlm);
135 mdp5_smp_destroy(mdp5_kms->smp);
137 mdp5_cfg_destroy(mdp5_kms->cfg);
142 static const struct mdp_kms_funcs kms_funcs = {
144 .hw_init = mdp5_hw_init,
145 .irq_preinstall = mdp5_irq_preinstall,
146 .irq_postinstall = mdp5_irq_postinstall,
147 .irq_uninstall = mdp5_irq_uninstall,
149 .enable_vblank = mdp5_enable_vblank,
150 .disable_vblank = mdp5_disable_vblank,
151 .prepare_commit = mdp5_prepare_commit,
152 .complete_commit = mdp5_complete_commit,
153 .wait_for_crtc_commit_done = mdp5_wait_for_crtc_commit_done,
154 .get_format = mdp_get_format,
155 .round_pixclk = mdp5_round_pixclk,
156 .set_split_display = mdp5_set_split_display,
157 .destroy = mdp5_destroy,
159 .set_irqmask = mdp5_set_irqmask,
162 int mdp5_disable(struct mdp5_kms *mdp5_kms)
166 clk_disable_unprepare(mdp5_kms->ahb_clk);
167 clk_disable_unprepare(mdp5_kms->axi_clk);
168 clk_disable_unprepare(mdp5_kms->core_clk);
169 if (mdp5_kms->lut_clk)
170 clk_disable_unprepare(mdp5_kms->lut_clk);
175 int mdp5_enable(struct mdp5_kms *mdp5_kms)
179 clk_prepare_enable(mdp5_kms->ahb_clk);
180 clk_prepare_enable(mdp5_kms->axi_clk);
181 clk_prepare_enable(mdp5_kms->core_clk);
182 if (mdp5_kms->lut_clk)
183 clk_prepare_enable(mdp5_kms->lut_clk);
188 static struct drm_encoder *construct_encoder(struct mdp5_kms *mdp5_kms,
189 enum mdp5_intf_type intf_type, int intf_num,
190 enum mdp5_intf_mode intf_mode, struct mdp5_ctl *ctl)
192 struct drm_device *dev = mdp5_kms->dev;
193 struct msm_drm_private *priv = dev->dev_private;
194 struct drm_encoder *encoder;
195 struct mdp5_interface intf = {
201 if ((intf_type == INTF_DSI) &&
202 (intf_mode == MDP5_INTF_DSI_MODE_COMMAND))
203 encoder = mdp5_cmd_encoder_init(dev, &intf, ctl);
205 encoder = mdp5_encoder_init(dev, &intf, ctl);
207 if (IS_ERR(encoder)) {
208 dev_err(dev->dev, "failed to construct encoder\n");
212 encoder->possible_crtcs = (1 << priv->num_crtcs) - 1;
213 priv->encoders[priv->num_encoders++] = encoder;
218 static int get_dsi_id_from_intf(const struct mdp5_cfg_hw *hw_cfg, int intf_num)
220 const enum mdp5_intf_type *intfs = hw_cfg->intf.connect;
221 const int intf_cnt = ARRAY_SIZE(hw_cfg->intf.connect);
224 for (i = 0; i < intf_cnt; i++) {
225 if (intfs[i] == INTF_DSI) {
236 static int modeset_init_intf(struct mdp5_kms *mdp5_kms, int intf_num)
238 struct drm_device *dev = mdp5_kms->dev;
239 struct msm_drm_private *priv = dev->dev_private;
240 const struct mdp5_cfg_hw *hw_cfg =
241 mdp5_cfg_get_hw_config(mdp5_kms->cfg);
242 enum mdp5_intf_type intf_type = hw_cfg->intf.connect[intf_num];
243 struct mdp5_ctl_manager *ctlm = mdp5_kms->ctlm;
244 struct mdp5_ctl *ctl;
245 struct drm_encoder *encoder;
255 ctl = mdp5_ctlm_request(ctlm, intf_num);
261 encoder = construct_encoder(mdp5_kms, INTF_eDP, intf_num,
262 MDP5_INTF_MODE_NONE, ctl);
263 if (IS_ERR(encoder)) {
264 ret = PTR_ERR(encoder);
268 ret = msm_edp_modeset_init(priv->edp, dev, encoder);
274 ctl = mdp5_ctlm_request(ctlm, intf_num);
280 encoder = construct_encoder(mdp5_kms, INTF_HDMI, intf_num,
281 MDP5_INTF_MODE_NONE, ctl);
282 if (IS_ERR(encoder)) {
283 ret = PTR_ERR(encoder);
287 ret = hdmi_modeset_init(priv->hdmi, dev, encoder);
291 int dsi_id = get_dsi_id_from_intf(hw_cfg, intf_num);
292 struct drm_encoder *dsi_encs[MSM_DSI_ENCODER_NUM];
293 enum mdp5_intf_mode mode;
296 if ((dsi_id >= ARRAY_SIZE(priv->dsi)) || (dsi_id < 0)) {
297 dev_err(dev->dev, "failed to find dsi from intf %d\n",
303 if (!priv->dsi[dsi_id])
306 ctl = mdp5_ctlm_request(ctlm, intf_num);
312 for (i = 0; i < MSM_DSI_ENCODER_NUM; i++) {
313 mode = (i == MSM_DSI_CMD_ENCODER_ID) ?
314 MDP5_INTF_DSI_MODE_COMMAND :
315 MDP5_INTF_DSI_MODE_VIDEO;
316 dsi_encs[i] = construct_encoder(mdp5_kms, INTF_DSI,
317 intf_num, mode, ctl);
318 if (IS_ERR(dsi_encs[i])) {
319 ret = PTR_ERR(dsi_encs[i]);
324 ret = msm_dsi_modeset_init(priv->dsi[dsi_id], dev, dsi_encs);
328 dev_err(dev->dev, "unknown intf: %d\n", intf_type);
336 static int modeset_init(struct mdp5_kms *mdp5_kms)
338 static const enum mdp5_pipe crtcs[] = {
339 SSPP_RGB0, SSPP_RGB1, SSPP_RGB2, SSPP_RGB3,
341 static const enum mdp5_pipe vig_planes[] = {
342 SSPP_VIG0, SSPP_VIG1, SSPP_VIG2, SSPP_VIG3,
344 static const enum mdp5_pipe dma_planes[] = {
345 SSPP_DMA0, SSPP_DMA1,
347 struct drm_device *dev = mdp5_kms->dev;
348 struct msm_drm_private *priv = dev->dev_private;
349 const struct mdp5_cfg_hw *hw_cfg;
352 hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
354 /* register our interrupt-controller for hdmi/eDP/dsi/etc
355 * to use for irqs routed through mdp:
357 ret = mdp5_irq_domain_init(mdp5_kms);
361 /* construct CRTCs and their private planes: */
362 for (i = 0; i < hw_cfg->pipe_rgb.count; i++) {
363 struct drm_plane *plane;
364 struct drm_crtc *crtc;
366 plane = mdp5_plane_init(dev, crtcs[i], true,
367 hw_cfg->pipe_rgb.base[i], hw_cfg->pipe_rgb.caps);
369 ret = PTR_ERR(plane);
370 dev_err(dev->dev, "failed to construct plane for %s (%d)\n",
371 pipe2name(crtcs[i]), ret);
375 crtc = mdp5_crtc_init(dev, plane, i);
378 dev_err(dev->dev, "failed to construct crtc for %s (%d)\n",
379 pipe2name(crtcs[i]), ret);
382 priv->crtcs[priv->num_crtcs++] = crtc;
385 /* Construct video planes: */
386 for (i = 0; i < hw_cfg->pipe_vig.count; i++) {
387 struct drm_plane *plane;
389 plane = mdp5_plane_init(dev, vig_planes[i], false,
390 hw_cfg->pipe_vig.base[i], hw_cfg->pipe_vig.caps);
392 ret = PTR_ERR(plane);
393 dev_err(dev->dev, "failed to construct %s plane: %d\n",
394 pipe2name(vig_planes[i]), ret);
400 for (i = 0; i < hw_cfg->pipe_dma.count; i++) {
401 struct drm_plane *plane;
403 plane = mdp5_plane_init(dev, dma_planes[i], false,
404 hw_cfg->pipe_dma.base[i], hw_cfg->pipe_dma.caps);
406 ret = PTR_ERR(plane);
407 dev_err(dev->dev, "failed to construct %s plane: %d\n",
408 pipe2name(dma_planes[i]), ret);
413 /* Construct encoders and modeset initialize connector devices
414 * for each external display interface.
416 for (i = 0; i < ARRAY_SIZE(hw_cfg->intf.connect); i++) {
417 ret = modeset_init_intf(mdp5_kms, i);
428 static void read_hw_revision(struct mdp5_kms *mdp5_kms,
429 uint32_t *major, uint32_t *minor)
433 mdp5_enable(mdp5_kms);
434 version = mdp5_read(mdp5_kms, REG_MDSS_HW_VERSION);
435 mdp5_disable(mdp5_kms);
437 *major = FIELD(version, MDSS_HW_VERSION_MAJOR);
438 *minor = FIELD(version, MDSS_HW_VERSION_MINOR);
440 DBG("MDP5 version v%d.%d", *major, *minor);
443 static int get_clk(struct platform_device *pdev, struct clk **clkp,
444 const char *name, bool mandatory)
446 struct device *dev = &pdev->dev;
447 struct clk *clk = devm_clk_get(dev, name);
448 if (IS_ERR(clk) && mandatory) {
449 dev_err(dev, "failed to get %s (%ld)\n", name, PTR_ERR(clk));
453 DBG("skipping %s", name);
460 static struct drm_encoder *get_encoder_from_crtc(struct drm_crtc *crtc)
462 struct drm_device *dev = crtc->dev;
463 struct drm_encoder *encoder;
465 drm_for_each_encoder(encoder, dev)
466 if (encoder->crtc == crtc)
472 static int mdp5_get_scanoutpos(struct drm_device *dev, unsigned int pipe,
473 unsigned int flags, int *vpos, int *hpos,
474 ktime_t *stime, ktime_t *etime,
475 const struct drm_display_mode *mode)
477 struct msm_drm_private *priv = dev->dev_private;
478 struct drm_crtc *crtc;
479 struct drm_encoder *encoder;
480 int line, vsw, vbp, vactive_start, vactive_end, vfp_end;
483 crtc = priv->crtcs[pipe];
485 DRM_ERROR("Invalid crtc %d\n", pipe);
489 encoder = get_encoder_from_crtc(crtc);
491 DRM_ERROR("no encoder found for crtc %d\n", pipe);
495 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
497 vsw = mode->crtc_vsync_end - mode->crtc_vsync_start;
498 vbp = mode->crtc_vtotal - mode->crtc_vsync_end;
501 * the line counter is 1 at the start of the VSYNC pulse and VTOTAL at
502 * the end of VFP. Translate the porch values relative to the line
506 vactive_start = vsw + vbp + 1;
508 vactive_end = vactive_start + mode->crtc_vdisplay;
510 /* last scan line before VSYNC */
511 vfp_end = mode->crtc_vtotal;
514 *stime = ktime_get();
516 line = mdp5_encoder_get_linecount(encoder);
518 if (line < vactive_start) {
519 line -= vactive_start;
520 ret |= DRM_SCANOUTPOS_IN_VBLANK;
521 } else if (line > vactive_end) {
522 line = line - vfp_end - vactive_start;
523 ret |= DRM_SCANOUTPOS_IN_VBLANK;
525 line -= vactive_start;
532 *etime = ktime_get();
537 static int mdp5_get_vblank_timestamp(struct drm_device *dev, unsigned int pipe,
539 struct timeval *vblank_time,
542 struct msm_drm_private *priv = dev->dev_private;
543 struct drm_crtc *crtc;
545 if (pipe < 0 || pipe >= priv->num_crtcs) {
546 DRM_ERROR("Invalid crtc %d\n", pipe);
550 crtc = priv->crtcs[pipe];
552 DRM_ERROR("Invalid crtc %d\n", pipe);
556 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
561 static u32 mdp5_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
563 struct msm_drm_private *priv = dev->dev_private;
564 struct drm_crtc *crtc;
565 struct drm_encoder *encoder;
567 if (pipe < 0 || pipe >= priv->num_crtcs)
570 crtc = priv->crtcs[pipe];
574 encoder = get_encoder_from_crtc(crtc);
578 return mdp5_encoder_get_framecount(encoder);
581 struct msm_kms *mdp5_kms_init(struct drm_device *dev)
583 struct platform_device *pdev = dev->platformdev;
584 struct mdp5_cfg *config;
585 struct mdp5_kms *mdp5_kms;
586 struct msm_kms *kms = NULL;
588 uint32_t major, minor;
591 mdp5_kms = kzalloc(sizeof(*mdp5_kms), GFP_KERNEL);
593 dev_err(dev->dev, "failed to allocate kms\n");
598 spin_lock_init(&mdp5_kms->resource_lock);
600 mdp_kms_init(&mdp5_kms->base, &kms_funcs);
602 kms = &mdp5_kms->base.base;
606 /* mdp5_kms->mmio actually represents the MDSS base address */
607 mdp5_kms->mmio = msm_ioremap(pdev, "mdp_phys", "MDP5");
608 if (IS_ERR(mdp5_kms->mmio)) {
609 ret = PTR_ERR(mdp5_kms->mmio);
613 mdp5_kms->vbif = msm_ioremap(pdev, "vbif_phys", "VBIF");
614 if (IS_ERR(mdp5_kms->vbif)) {
615 ret = PTR_ERR(mdp5_kms->vbif);
619 mdp5_kms->vdd = devm_regulator_get(&pdev->dev, "vdd");
620 if (IS_ERR(mdp5_kms->vdd)) {
621 ret = PTR_ERR(mdp5_kms->vdd);
625 ret = regulator_enable(mdp5_kms->vdd);
627 dev_err(dev->dev, "failed to enable regulator vdd: %d\n", ret);
631 /* mandatory clocks: */
632 ret = get_clk(pdev, &mdp5_kms->axi_clk, "bus_clk", true);
635 ret = get_clk(pdev, &mdp5_kms->ahb_clk, "iface_clk", true);
638 ret = get_clk(pdev, &mdp5_kms->src_clk, "core_clk_src", true);
641 ret = get_clk(pdev, &mdp5_kms->core_clk, "core_clk", true);
644 ret = get_clk(pdev, &mdp5_kms->vsync_clk, "vsync_clk", true);
648 /* optional clocks: */
649 get_clk(pdev, &mdp5_kms->lut_clk, "lut_clk", false);
651 /* we need to set a default rate before enabling. Set a safe
652 * rate first, then figure out hw revision, and then set a
655 clk_set_rate(mdp5_kms->src_clk, 200000000);
657 read_hw_revision(mdp5_kms, &major, &minor);
659 mdp5_kms->cfg = mdp5_cfg_init(mdp5_kms, major, minor);
660 if (IS_ERR(mdp5_kms->cfg)) {
661 ret = PTR_ERR(mdp5_kms->cfg);
662 mdp5_kms->cfg = NULL;
666 config = mdp5_cfg_get_config(mdp5_kms->cfg);
667 mdp5_kms->caps = config->hw->mdp.caps;
669 /* TODO: compute core clock rate at runtime */
670 clk_set_rate(mdp5_kms->src_clk, config->hw->max_clk);
673 * Some chipsets have a Shared Memory Pool (SMP), while others
674 * have dedicated latency buffering per source pipe instead;
675 * this section initializes the SMP:
677 if (mdp5_kms->caps & MDP_CAP_SMP) {
678 mdp5_kms->smp = mdp5_smp_init(mdp5_kms->dev, &config->hw->smp);
679 if (IS_ERR(mdp5_kms->smp)) {
680 ret = PTR_ERR(mdp5_kms->smp);
681 mdp5_kms->smp = NULL;
686 mdp5_kms->ctlm = mdp5_ctlm_init(dev, mdp5_kms->mmio, mdp5_kms->cfg);
687 if (IS_ERR(mdp5_kms->ctlm)) {
688 ret = PTR_ERR(mdp5_kms->ctlm);
689 mdp5_kms->ctlm = NULL;
693 /* make sure things are off before attaching iommu (bootloader could
694 * have left things on, in which case we'll start getting faults if
697 mdp5_enable(mdp5_kms);
698 for (i = 0; i < MDP5_INTF_NUM_MAX; i++) {
699 if (mdp5_cfg_intf_is_virtual(config->hw->intf.connect[i]) ||
700 !config->hw->intf.base[i])
702 mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(i), 0);
704 mdp5_write(mdp5_kms, REG_MDP5_INTF_FRAME_LINE_COUNT_EN(i), 0x3);
706 mdp5_disable(mdp5_kms);
709 if (config->platform.iommu) {
710 mmu = msm_iommu_new(&pdev->dev, config->platform.iommu);
713 dev_err(dev->dev, "failed to init iommu: %d\n", ret);
714 iommu_domain_free(config->platform.iommu);
718 ret = mmu->funcs->attach(mmu, iommu_ports,
719 ARRAY_SIZE(iommu_ports));
721 dev_err(dev->dev, "failed to attach iommu: %d\n", ret);
722 mmu->funcs->destroy(mmu);
726 dev_info(dev->dev, "no iommu, fallback to phys "
727 "contig buffers for scanout\n");
732 mdp5_kms->id = msm_register_mmu(dev, mmu);
733 if (mdp5_kms->id < 0) {
735 dev_err(dev->dev, "failed to register mdp5 iommu: %d\n", ret);
739 ret = modeset_init(mdp5_kms);
741 dev_err(dev->dev, "modeset_init failed: %d\n", ret);
745 dev->mode_config.min_width = 0;
746 dev->mode_config.min_height = 0;
747 dev->mode_config.max_width = config->hw->lm.max_width;
748 dev->mode_config.max_height = config->hw->lm.max_height;
750 dev->driver->get_vblank_timestamp = mdp5_get_vblank_timestamp;
751 dev->driver->get_scanout_position = mdp5_get_scanoutpos;
752 dev->driver->get_vblank_counter = mdp5_get_vblank_counter;
753 dev->max_vblank_count = 0xffffffff;
754 dev->vblank_disable_immediate = true;