2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
18 #ifndef __MDP5_KMS_H__
19 #define __MDP5_KMS_H__
23 #include "mdp/mdp_kms.h"
24 #include "mdp5_cfg.h" /* must be included before mdp5.xml.h */
26 #include "mdp5_pipe.h"
27 #include "mdp5_mixer.h"
36 struct drm_device *dev;
38 struct platform_device *pdev;
41 struct mdp5_hw_pipe *hwpipes[SSPP_MAX];
43 unsigned num_hwmixers;
44 struct mdp5_hw_mixer *hwmixers[8];
47 struct mdp5_interface *intfs[5];
49 struct mdp5_cfg_handler *cfg;
50 uint32_t caps; /* MDP capabilities (MDP_CAP_XXX bits) */
53 * Global atomic state. Do not access directly, use mdp5_get_state()
55 struct mdp5_state *state;
56 struct drm_modeset_lock state_lock;
58 /* mapper-id used to request GEM buffer mapped for scanout: */
60 struct msm_gem_address_space *aspace;
63 struct mdp5_ctl_manager *ctlm;
65 /* io/register spaces: */
72 struct clk *vsync_clk;
75 * lock to protect access to global resources: ie., following register:
76 * - REG_MDP5_DISP_INTF_SEL
78 spinlock_t resource_lock;
82 struct mdp_irq error_handler;
84 #define to_mdp5_kms(x) container_of(x, struct mdp5_kms, base)
86 /* Global atomic state for tracking resources that are shared across
87 * multiple kms objects (planes/crtcs/etc).
89 * For atomic updates which require modifying global state,
92 struct mdp5_hw_pipe_state hwpipe;
93 struct mdp5_hw_mixer_state hwmixer;
94 struct mdp5_smp_state smp;
97 struct mdp5_state *__must_check
98 mdp5_get_state(struct drm_atomic_state *s);
100 /* Atomic plane state. Subclasses the base drm_plane_state in order to
101 * track assigned hwpipe and hw specific state.
103 struct mdp5_plane_state {
104 struct drm_plane_state base;
106 struct mdp5_hw_pipe *hwpipe;
107 struct mdp5_hw_pipe *r_hwpipe; /* right hwpipe */
109 /* aligned with property */
110 uint8_t premultiplied;
114 /* assigned by crtc blender */
115 enum mdp_mixer_stage_id stage;
117 #define to_mdp5_plane_state(x) \
118 container_of(x, struct mdp5_plane_state, base)
120 struct mdp5_pipeline {
121 struct mdp5_interface *intf;
122 struct mdp5_hw_mixer *mixer;
123 struct mdp5_hw_mixer *r_mixer; /* right mixer */
126 struct mdp5_crtc_state {
127 struct drm_crtc_state base;
129 struct mdp5_ctl *ctl;
130 struct mdp5_pipeline pipeline;
132 /* these are derivatives of intf/mixer state in mdp5_pipeline */
139 #define to_mdp5_crtc_state(x) \
140 container_of(x, struct mdp5_crtc_state, base)
142 enum mdp5_intf_mode {
143 MDP5_INTF_MODE_NONE = 0,
145 /* Modes used for DSI interface (INTF_DSI type): */
146 MDP5_INTF_DSI_MODE_VIDEO,
147 MDP5_INTF_DSI_MODE_COMMAND,
149 /* Modes used for WB interface (INTF_WB type): */
150 MDP5_INTF_WB_MODE_BLOCK,
151 MDP5_INTF_WB_MODE_LINE,
154 struct mdp5_interface {
156 int num; /* display interface number */
157 enum mdp5_intf_type type;
158 enum mdp5_intf_mode mode;
161 struct mdp5_encoder {
162 struct drm_encoder base;
163 spinlock_t intf_lock; /* protect REG_MDP5_INTF_* registers */
167 struct mdp5_interface *intf;
168 struct mdp5_ctl *ctl;
170 #define to_mdp5_encoder(x) container_of(x, struct mdp5_encoder, base)
172 static inline void mdp5_write(struct mdp5_kms *mdp5_kms, u32 reg, u32 data)
174 msm_writel(data, mdp5_kms->mmio + reg);
177 static inline u32 mdp5_read(struct mdp5_kms *mdp5_kms, u32 reg)
179 return msm_readl(mdp5_kms->mmio + reg);
182 static inline const char *stage2name(enum mdp_mixer_stage_id stage)
184 static const char *names[] = {
185 #define NAME(n) [n] = #n
186 NAME(STAGE_UNUSED), NAME(STAGE_BASE),
187 NAME(STAGE0), NAME(STAGE1), NAME(STAGE2),
188 NAME(STAGE3), NAME(STAGE4), NAME(STAGE6),
194 static inline const char *pipe2name(enum mdp5_pipe pipe)
196 static const char *names[] = {
197 #define NAME(n) [SSPP_ ## n] = #n
198 NAME(VIG0), NAME(VIG1), NAME(VIG2),
199 NAME(RGB0), NAME(RGB1), NAME(RGB2),
200 NAME(DMA0), NAME(DMA1),
201 NAME(VIG3), NAME(RGB3),
202 NAME(CURSOR0), NAME(CURSOR1),
208 static inline int pipe2nclients(enum mdp5_pipe pipe)
221 static inline uint32_t intf2err(int intf_num)
224 case 0: return MDP5_IRQ_INTF0_UNDER_RUN;
225 case 1: return MDP5_IRQ_INTF1_UNDER_RUN;
226 case 2: return MDP5_IRQ_INTF2_UNDER_RUN;
227 case 3: return MDP5_IRQ_INTF3_UNDER_RUN;
232 static inline uint32_t intf2vblank(struct mdp5_hw_mixer *mixer,
233 struct mdp5_interface *intf)
236 * In case of DSI Command Mode, the Ping Pong's read pointer IRQ
237 * acts as a Vblank signal. The Ping Pong buffer used is bound to
241 if ((intf->type == INTF_DSI) &&
242 (intf->mode == MDP5_INTF_DSI_MODE_COMMAND))
243 return MDP5_IRQ_PING_PONG_0_RD_PTR << mixer->pp;
245 if (intf->type == INTF_WB)
246 return MDP5_IRQ_WB_2_DONE;
249 case 0: return MDP5_IRQ_INTF0_VSYNC;
250 case 1: return MDP5_IRQ_INTF1_VSYNC;
251 case 2: return MDP5_IRQ_INTF2_VSYNC;
252 case 3: return MDP5_IRQ_INTF3_VSYNC;
257 static inline uint32_t lm2ppdone(struct mdp5_hw_mixer *mixer)
259 return MDP5_IRQ_PING_PONG_0_DONE << mixer->pp;
262 int mdp5_disable(struct mdp5_kms *mdp5_kms);
263 int mdp5_enable(struct mdp5_kms *mdp5_kms);
265 void mdp5_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask,
266 uint32_t old_irqmask);
267 void mdp5_irq_preinstall(struct msm_kms *kms);
268 int mdp5_irq_postinstall(struct msm_kms *kms);
269 void mdp5_irq_uninstall(struct msm_kms *kms);
270 irqreturn_t mdp5_irq(struct msm_kms *kms);
271 int mdp5_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);
272 void mdp5_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);
273 int mdp5_irq_domain_init(struct mdp5_kms *mdp5_kms);
274 void mdp5_irq_domain_fini(struct mdp5_kms *mdp5_kms);
276 uint32_t mdp5_plane_get_flush(struct drm_plane *plane);
277 enum mdp5_pipe mdp5_plane_pipe(struct drm_plane *plane);
278 enum mdp5_pipe mdp5_plane_right_pipe(struct drm_plane *plane);
279 struct drm_plane *mdp5_plane_init(struct drm_device *dev,
280 enum drm_plane_type type);
282 struct mdp5_ctl *mdp5_crtc_get_ctl(struct drm_crtc *crtc);
283 uint32_t mdp5_crtc_vblank(struct drm_crtc *crtc);
285 struct mdp5_hw_mixer *mdp5_crtc_get_mixer(struct drm_crtc *crtc);
286 struct mdp5_pipeline *mdp5_crtc_get_pipeline(struct drm_crtc *crtc);
287 void mdp5_crtc_set_pipeline(struct drm_crtc *crtc);
288 void mdp5_crtc_wait_for_commit_done(struct drm_crtc *crtc);
289 struct drm_crtc *mdp5_crtc_init(struct drm_device *dev,
290 struct drm_plane *plane,
291 struct drm_plane *cursor_plane, int id);
293 struct drm_encoder *mdp5_encoder_init(struct drm_device *dev,
294 struct mdp5_interface *intf, struct mdp5_ctl *ctl);
295 int mdp5_vid_encoder_set_split_display(struct drm_encoder *encoder,
296 struct drm_encoder *slave_encoder);
297 void mdp5_encoder_set_intf_mode(struct drm_encoder *encoder, bool cmd_mode);
298 int mdp5_encoder_get_linecount(struct drm_encoder *encoder);
299 u32 mdp5_encoder_get_framecount(struct drm_encoder *encoder);
301 #ifdef CONFIG_DRM_MSM_DSI
302 void mdp5_cmd_encoder_mode_set(struct drm_encoder *encoder,
303 struct drm_display_mode *mode,
304 struct drm_display_mode *adjusted_mode);
305 void mdp5_cmd_encoder_disable(struct drm_encoder *encoder);
306 void mdp5_cmd_encoder_enable(struct drm_encoder *encoder);
307 int mdp5_cmd_encoder_set_split_display(struct drm_encoder *encoder,
308 struct drm_encoder *slave_encoder);
310 static inline void mdp5_cmd_encoder_mode_set(struct drm_encoder *encoder,
311 struct drm_display_mode *mode,
312 struct drm_display_mode *adjusted_mode)
315 static inline void mdp5_cmd_encoder_disable(struct drm_encoder *encoder)
318 static inline void mdp5_cmd_encoder_enable(struct drm_encoder *encoder)
321 static inline int mdp5_cmd_encoder_set_split_display(
322 struct drm_encoder *encoder, struct drm_encoder *slave_encoder)
328 #endif /* __MDP5_KMS_H__ */