drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c

   1 /*
   2  * Copyright (C) 2014-2015 The Linux Foundation. All rights reserved.
   3  * Copyright (C) 2013 Red Hat
   4  * Author: Rob Clark <robdclark@gmail.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published by
   8  * the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include <drm/drm_print.h>
  20 #include "mdp5_kms.h"
  21
  22 struct mdp5_plane {
  23         struct drm_plane base;
  24
  25         uint32_t nformats;
  26         uint32_t formats[32];
  27 };
  28 #define to_mdp5_plane(x) container_of(x, struct mdp5_plane, base)
  29
  30 static int mdp5_plane_mode_set(struct drm_plane *plane,
  31                 struct drm_crtc *crtc, struct drm_framebuffer *fb,
  32                 int crtc_x, int crtc_y,
  33                 unsigned int crtc_w, unsigned int crtc_h,
  34                 uint32_t src_x, uint32_t src_y,
  35                 uint32_t src_w, uint32_t src_h);
  36
  37 static void set_scanout_locked(struct drm_plane *plane,
  38                 struct drm_framebuffer *fb);
  39
  40 static struct mdp5_kms *get_kms(struct drm_plane *plane)
  41 {
  42         struct msm_drm_private *priv = plane->dev->dev_private;
  43         return to_mdp5_kms(to_mdp_kms(priv->kms));
  44 }
  45
  46 static bool plane_enabled(struct drm_plane_state *state)
  47 {
  48         return state->fb && state->crtc;
  49 }
  50
  51 static void mdp5_plane_destroy(struct drm_plane *plane)
  52 {
  53         struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
  54
  55         drm_plane_helper_disable(plane);
  56         drm_plane_cleanup(plane);
  57
  58         kfree(mdp5_plane);
  59 }
  60
  61 static void mdp5_plane_install_rotation_property(struct drm_device *dev,
  62                 struct drm_plane *plane)
  63 {
  64         drm_plane_create_rotation_property(plane,
  65                                            DRM_ROTATE_0,
  66                                            DRM_ROTATE_0 |
  67                                            DRM_ROTATE_180 |
  68                                            DRM_REFLECT_X |
  69                                            DRM_REFLECT_Y);
  70 }
  71
  72 /* helper to install properties which are common to planes and crtcs */
  73 static void mdp5_plane_install_properties(struct drm_plane *plane,
  74                 struct drm_mode_object *obj)
  75 {
  76         struct drm_device *dev = plane->dev;
  77         struct msm_drm_private *dev_priv = dev->dev_private;
  78         struct drm_property *prop;
  79
  80 #define INSTALL_PROPERTY(name, NAME, init_val, fnc, ...) do { \
  81                 prop = dev_priv->plane_property[PLANE_PROP_##NAME]; \
  82                 if (!prop) { \
  83                         prop = drm_property_##fnc(dev, 0, #name, \
  84                                 ##__VA_ARGS__); \
  85                         if (!prop) { \
  86                                 dev_warn(dev->dev, \
  87                                         "Create property %s failed\n", \
  88                                         #name); \
  89                                 return; \
  90                         } \
  91                         dev_priv->plane_property[PLANE_PROP_##NAME] = prop; \
  92                 } \
  93                 drm_object_attach_property(&plane->base, prop, init_val); \
  94         } while (0)
  95
  96 #define INSTALL_RANGE_PROPERTY(name, NAME, min, max, init_val) \
  97                 INSTALL_PROPERTY(name, NAME, init_val, \
  98                                 create_range, min, max)
  99
 100 #define INSTALL_ENUM_PROPERTY(name, NAME, init_val) \
 101                 INSTALL_PROPERTY(name, NAME, init_val, \
 102                                 create_enum, name##_prop_enum_list, \
 103                                 ARRAY_SIZE(name##_prop_enum_list))
 104
 105         INSTALL_RANGE_PROPERTY(zpos, ZPOS, 1, 255, 1);
 106
 107         mdp5_plane_install_rotation_property(dev, plane);
 108
 109 #undef INSTALL_RANGE_PROPERTY
 110 #undef INSTALL_ENUM_PROPERTY
 111 #undef INSTALL_PROPERTY
 112 }
 113
 114 static int mdp5_plane_atomic_set_property(struct drm_plane *plane,
 115                 struct drm_plane_state *state, struct drm_property *property,
 116                 uint64_t val)
 117 {
 118         struct drm_device *dev = plane->dev;
 119         struct mdp5_plane_state *pstate;
 120         struct msm_drm_private *dev_priv = dev->dev_private;
 121         int ret = 0;
 122
 123         pstate = to_mdp5_plane_state(state);
 124
 125 #define SET_PROPERTY(name, NAME, type) do { \
 126                 if (dev_priv->plane_property[PLANE_PROP_##NAME] == property) { \
 127                         pstate->name = (type)val; \
 128                         DBG("Set property %s %d", #name, (type)val); \
 129                         goto done; \
 130                 } \
 131         } while (0)
 132
 133         SET_PROPERTY(zpos, ZPOS, uint8_t);
 134
 135         dev_err(dev->dev, "Invalid property\n");
 136         ret = -EINVAL;
 137 done:
 138         return ret;
 139 #undef SET_PROPERTY
 140 }
 141
 142 static int mdp5_plane_atomic_get_property(struct drm_plane *plane,
 143                 const struct drm_plane_state *state,
 144                 struct drm_property *property, uint64_t *val)
 145 {
 146         struct drm_device *dev = plane->dev;
 147         struct mdp5_plane_state *pstate;
 148         struct msm_drm_private *dev_priv = dev->dev_private;
 149         int ret = 0;
 150
 151         pstate = to_mdp5_plane_state(state);
 152
 153 #define GET_PROPERTY(name, NAME, type) do { \
 154                 if (dev_priv->plane_property[PLANE_PROP_##NAME] == property) { \
 155                         *val = pstate->name; \
 156                         DBG("Get property %s %lld", #name, *val); \
 157                         goto done; \
 158                 } \
 159         } while (0)
 160
 161         GET_PROPERTY(zpos, ZPOS, uint8_t);
 162
 163         dev_err(dev->dev, "Invalid property\n");
 164         ret = -EINVAL;
 165 done:
 166         return ret;
 167 #undef SET_PROPERTY
 168 }
 169
 170 static void
 171 mdp5_plane_atomic_print_state(struct drm_printer *p,
 172                 const struct drm_plane_state *state)
 173 {
 174         struct mdp5_plane_state *pstate = to_mdp5_plane_state(state);
 175
 176         drm_printf(p, "\thwpipe=%s\n", pstate->hwpipe ?
 177                         pstate->hwpipe->name : "(null)");
 178         drm_printf(p, "\tpremultiplied=%u\n", pstate->premultiplied);
 179         drm_printf(p, "\tzpos=%u\n", pstate->zpos);
 180         drm_printf(p, "\talpha=%u\n", pstate->alpha);
 181         drm_printf(p, "\tstage=%s\n", stage2name(pstate->stage));
 182 }
 183
 184 static void mdp5_plane_reset(struct drm_plane *plane)
 185 {
 186         struct mdp5_plane_state *mdp5_state;
 187
 188         if (plane->state && plane->state->fb)
 189                 drm_framebuffer_unreference(plane->state->fb);
 190
 191         kfree(to_mdp5_plane_state(plane->state));
 192         mdp5_state = kzalloc(sizeof(*mdp5_state), GFP_KERNEL);
 193
 194         /* assign default blend parameters */
 195         mdp5_state->alpha = 255;
 196         mdp5_state->premultiplied = 0;
 197
 198         if (plane->type == DRM_PLANE_TYPE_PRIMARY)
 199                 mdp5_state->zpos = STAGE_BASE;
 200         else
 201                 mdp5_state->zpos = STAGE0 + drm_plane_index(plane);
 202
 203         mdp5_state->base.plane = plane;
 204
 205         plane->state = &mdp5_state->base;
 206 }
 207
 208 static struct drm_plane_state *
 209 mdp5_plane_duplicate_state(struct drm_plane *plane)
 210 {
 211         struct mdp5_plane_state *mdp5_state;
 212
 213         if (WARN_ON(!plane->state))
 214                 return NULL;
 215
 216         mdp5_state = kmemdup(to_mdp5_plane_state(plane->state),
 217                         sizeof(*mdp5_state), GFP_KERNEL);
 218
 219         if (mdp5_state && mdp5_state->base.fb)
 220                 drm_framebuffer_reference(mdp5_state->base.fb);
 221
 222         return &mdp5_state->base;
 223 }
 224
 225 static void mdp5_plane_destroy_state(struct drm_plane *plane,
 226                 struct drm_plane_state *state)
 227 {
 228         struct mdp5_plane_state *pstate = to_mdp5_plane_state(state);
 229
 230         if (state->fb)
 231                 drm_framebuffer_unreference(state->fb);
 232
 233         kfree(pstate);
 234 }
 235
 236 static const struct drm_plane_funcs mdp5_plane_funcs = {
 237                 .update_plane = drm_atomic_helper_update_plane,
 238                 .disable_plane = drm_atomic_helper_disable_plane,
 239                 .destroy = mdp5_plane_destroy,
 240                 .set_property = drm_atomic_helper_plane_set_property,
 241                 .atomic_set_property = mdp5_plane_atomic_set_property,
 242                 .atomic_get_property = mdp5_plane_atomic_get_property,
 243                 .reset = mdp5_plane_reset,
 244                 .atomic_duplicate_state = mdp5_plane_duplicate_state,
 245                 .atomic_destroy_state = mdp5_plane_destroy_state,
 246                 .atomic_print_state = mdp5_plane_atomic_print_state,
 247 };
 248
 249 static int mdp5_plane_prepare_fb(struct drm_plane *plane,
 250                                  struct drm_plane_state *new_state)
 251 {
 252         struct mdp5_kms *mdp5_kms = get_kms(plane);
 253         struct drm_framebuffer *fb = new_state->fb;
 254
 255         if (!new_state->fb)
 256                 return 0;
 257
 258         DBG("%s: prepare: FB[%u]", plane->name, fb->base.id);
 259         return msm_framebuffer_prepare(fb, mdp5_kms->id);
 260 }
 261
 262 static void mdp5_plane_cleanup_fb(struct drm_plane *plane,
 263                                   struct drm_plane_state *old_state)
 264 {
 265         struct mdp5_kms *mdp5_kms = get_kms(plane);
 266         struct drm_framebuffer *fb = old_state->fb;
 267
 268         if (!fb)
 269                 return;
 270
 271         DBG("%s: cleanup: FB[%u]", plane->name, fb->base.id);
 272         msm_framebuffer_cleanup(fb, mdp5_kms->id);
 273 }
 274
 275 static int mdp5_plane_atomic_check(struct drm_plane *plane,
 276                 struct drm_plane_state *state)
 277 {
 278         struct mdp5_plane_state *mdp5_state = to_mdp5_plane_state(state);
 279         struct drm_plane_state *old_state = plane->state;
 280         struct mdp5_cfg *config = mdp5_cfg_get_config(get_kms(plane)->cfg);
 281         bool new_hwpipe = false;
 282         uint32_t max_width, max_height;
 283         uint32_t caps = 0;
 284
 285         DBG("%s: check (%d -> %d)", plane->name,
 286                         plane_enabled(old_state), plane_enabled(state));
 287
 288         max_width = config->hw->lm.max_width << 16;
 289         max_height = config->hw->lm.max_height << 16;
 290
 291         /* Make sure source dimensions are within bounds. */
 292         if ((state->src_w > max_width) || (state->src_h > max_height)) {
 293                 struct drm_rect src = drm_plane_state_src(state);
 294                 DBG("Invalid source size "DRM_RECT_FP_FMT,
 295                                 DRM_RECT_FP_ARG(&src));
 296                 return -ERANGE;
 297         }
 298
 299         if (plane_enabled(state)) {
 300                 unsigned int rotation;
 301                 const struct mdp_format *format;
 302                 struct mdp5_kms *mdp5_kms = get_kms(plane);
 303                 uint32_t blkcfg = 0;
 304
 305                 format = to_mdp_format(msm_framebuffer_format(state->fb));
 306                 if (MDP_FORMAT_IS_YUV(format))
 307                         caps |= MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC;
 308
 309                 if (((state->src_w >> 16) != state->crtc_w) ||
 310                                 ((state->src_h >> 16) != state->crtc_h))
 311                         caps |= MDP_PIPE_CAP_SCALE;
 312
 313                 rotation = drm_rotation_simplify(state->rotation,
 314                                                  DRM_ROTATE_0 |
 315                                                  DRM_REFLECT_X |
 316                                                  DRM_REFLECT_Y);
 317
 318                 if (rotation & DRM_REFLECT_X)
 319                         caps |= MDP_PIPE_CAP_HFLIP;
 320
 321                 if (rotation & DRM_REFLECT_Y)
 322                         caps |= MDP_PIPE_CAP_VFLIP;
 323
 324                 /* (re)allocate hw pipe if we don't have one or caps-mismatch: */
 325                 if (!mdp5_state->hwpipe || (caps & ~mdp5_state->hwpipe->caps))
 326                         new_hwpipe = true;
 327
 328                 if (mdp5_kms->smp) {
 329                         const struct mdp_format *format =
 330                                 to_mdp_format(msm_framebuffer_format(state->fb));
 331
 332                         blkcfg = mdp5_smp_calculate(mdp5_kms->smp, format,
 333                                         state->src_w >> 16, false);
 334
 335                         if (mdp5_state->hwpipe && (mdp5_state->hwpipe->blkcfg != blkcfg))
 336                                 new_hwpipe = true;
 337                 }
 338
 339                 /* (re)assign hwpipe if needed, otherwise keep old one: */
 340                 if (new_hwpipe) {
 341                         /* TODO maybe we want to re-assign hwpipe sometimes
 342                          * in cases when we no-longer need some caps to make
 343                          * it available for other planes?
 344                          */
 345                         struct mdp5_hw_pipe *old_hwpipe = mdp5_state->hwpipe;
 346                         mdp5_state->hwpipe = mdp5_pipe_assign(state->state,
 347                                         plane, caps, blkcfg);
 348                         if (IS_ERR(mdp5_state->hwpipe)) {
 349                                 DBG("%s: failed to assign hwpipe!", plane->name);
 350                                 return PTR_ERR(mdp5_state->hwpipe);
 351                         }
 352                         mdp5_pipe_release(state->state, old_hwpipe);
 353                 }
 354         }
 355
 356         return 0;
 357 }
 358
 359 static void mdp5_plane_atomic_update(struct drm_plane *plane,
 360                                      struct drm_plane_state *old_state)
 361 {
 362         struct drm_plane_state *state = plane->state;
 363
 364         DBG("%s: update", plane->name);
 365
 366         if (plane_enabled(state)) {
 367                 int ret;
 368
 369                 ret = mdp5_plane_mode_set(plane,
 370                                 state->crtc, state->fb,
 371                                 state->crtc_x, state->crtc_y,
 372                                 state->crtc_w, state->crtc_h,
 373                                 state->src_x,  state->src_y,
 374                                 state->src_w, state->src_h);
 375                 /* atomic_check should have ensured that this doesn't fail */
 376                 WARN_ON(ret < 0);
 377         }
 378 }
 379
 380 static const struct drm_plane_helper_funcs mdp5_plane_helper_funcs = {
 381                 .prepare_fb = mdp5_plane_prepare_fb,
 382                 .cleanup_fb = mdp5_plane_cleanup_fb,
 383                 .atomic_check = mdp5_plane_atomic_check,
 384                 .atomic_update = mdp5_plane_atomic_update,
 385 };
 386
 387 static void set_scanout_locked(struct drm_plane *plane,
 388                 struct drm_framebuffer *fb)
 389 {
 390         struct mdp5_kms *mdp5_kms = get_kms(plane);
 391         struct mdp5_hw_pipe *hwpipe = to_mdp5_plane_state(plane->state)->hwpipe;
 392         enum mdp5_pipe pipe = hwpipe->pipe;
 393
 394         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_A(pipe),
 395                         MDP5_PIPE_SRC_STRIDE_A_P0(fb->pitches[0]) |
 396                         MDP5_PIPE_SRC_STRIDE_A_P1(fb->pitches[1]));
 397
 398         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_B(pipe),
 399                         MDP5_PIPE_SRC_STRIDE_B_P2(fb->pitches[2]) |
 400                         MDP5_PIPE_SRC_STRIDE_B_P3(fb->pitches[3]));
 401
 402         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC0_ADDR(pipe),
 403                         msm_framebuffer_iova(fb, mdp5_kms->id, 0));
 404         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC1_ADDR(pipe),
 405                         msm_framebuffer_iova(fb, mdp5_kms->id, 1));
 406         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC2_ADDR(pipe),
 407                         msm_framebuffer_iova(fb, mdp5_kms->id, 2));
 408         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC3_ADDR(pipe),
 409                         msm_framebuffer_iova(fb, mdp5_kms->id, 3));
 410
 411         plane->fb = fb;
 412 }
 413
 414 /* Note: mdp5_plane->pipe_lock must be locked */
 415 static void csc_disable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe)
 416 {
 417         uint32_t value = mdp5_read(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe)) &
 418                          ~MDP5_PIPE_OP_MODE_CSC_1_EN;
 419
 420         mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), value);
 421 }
 422
 423 /* Note: mdp5_plane->pipe_lock must be locked */
 424 static void csc_enable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe,
 425                 struct csc_cfg *csc)
 426 {
 427         uint32_t  i, mode = 0; /* RGB, no CSC */
 428         uint32_t *matrix;
 429
 430         if (unlikely(!csc))
 431                 return;
 432
 433         if ((csc->type == CSC_YUV2RGB) || (CSC_YUV2YUV == csc->type))
 434                 mode |= MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT(DATA_FORMAT_YUV);
 435         if ((csc->type == CSC_RGB2YUV) || (CSC_YUV2YUV == csc->type))
 436                 mode |= MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT(DATA_FORMAT_YUV);
 437         mode |= MDP5_PIPE_OP_MODE_CSC_1_EN;
 438         mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), mode);
 439
 440         matrix = csc->matrix;
 441         mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(pipe),
 442                         MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11(matrix[0]) |
 443                         MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12(matrix[1]));
 444         mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(pipe),
 445                         MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13(matrix[2]) |
 446                         MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21(matrix[3]));
 447         mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(pipe),
 448                         MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22(matrix[4]) |
 449                         MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23(matrix[5]));
 450         mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(pipe),
 451                         MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31(matrix[6]) |
 452                         MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32(matrix[7]));
 453         mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(pipe),
 454                         MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33(matrix[8]));
 455
 456         for (i = 0; i < ARRAY_SIZE(csc->pre_bias); i++) {
 457                 uint32_t *pre_clamp = csc->pre_clamp;
 458                 uint32_t *post_clamp = csc->post_clamp;
 459
 460                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_CLAMP(pipe, i),
 461                         MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH(pre_clamp[2*i+1]) |
 462                         MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW(pre_clamp[2*i]));
 463
 464                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_CLAMP(pipe, i),
 465                         MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH(post_clamp[2*i+1]) |
 466                         MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW(post_clamp[2*i]));
 467
 468                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_BIAS(pipe, i),
 469                         MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE(csc->pre_bias[i]));
 470
 471                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_BIAS(pipe, i),
 472                         MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE(csc->post_bias[i]));
 473         }
 474 }
 475
 476 #define PHASE_STEP_SHIFT        21
 477 #define DOWN_SCALE_RATIO_MAX    32      /* 2^(26-21) */
 478
 479 static int calc_phase_step(uint32_t src, uint32_t dst, uint32_t *out_phase)
 480 {
 481         uint32_t unit;
 482
 483         if (src == 0 || dst == 0)
 484                 return -EINVAL;
 485
 486         /*
 487          * PHASE_STEP_X/Y is coded on 26 bits (25:0),
 488          * where 2^21 represents the unity "1" in fixed-point hardware design.
 489          * This leaves 5 bits for the integer part (downscale case):
 490          *      -> maximum downscale ratio = 0b1_1111 = 31
 491          */
 492         if (src > (dst * DOWN_SCALE_RATIO_MAX))
 493                 return -EOVERFLOW;
 494
 495         unit = 1 << PHASE_STEP_SHIFT;
 496         *out_phase = mult_frac(unit, src, dst);
 497
 498         return 0;
 499 }
 500
 501 static int calc_scalex_steps(struct drm_plane *plane,
 502                 uint32_t pixel_format, uint32_t src, uint32_t dest,
 503                 uint32_t phasex_steps[COMP_MAX])
 504 {
 505         struct mdp5_kms *mdp5_kms = get_kms(plane);
 506         struct device *dev = mdp5_kms->dev->dev;
 507         uint32_t phasex_step;
 508         unsigned int hsub;
 509         int ret;
 510
 511         ret = calc_phase_step(src, dest, &phasex_step);
 512         if (ret) {
 513                 dev_err(dev, "X scaling (%d->%d) failed: %d\n", src, dest, ret);
 514                 return ret;
 515         }
 516
 517         hsub = drm_format_horz_chroma_subsampling(pixel_format);
 518
 519         phasex_steps[COMP_0]   = phasex_step;
 520         phasex_steps[COMP_3]   = phasex_step;
 521         phasex_steps[COMP_1_2] = phasex_step / hsub;
 522
 523         return 0;
 524 }
 525
 526 static int calc_scaley_steps(struct drm_plane *plane,
 527                 uint32_t pixel_format, uint32_t src, uint32_t dest,
 528                 uint32_t phasey_steps[COMP_MAX])
 529 {
 530         struct mdp5_kms *mdp5_kms = get_kms(plane);
 531         struct device *dev = mdp5_kms->dev->dev;
 532         uint32_t phasey_step;
 533         unsigned int vsub;
 534         int ret;
 535
 536         ret = calc_phase_step(src, dest, &phasey_step);
 537         if (ret) {
 538                 dev_err(dev, "Y scaling (%d->%d) failed: %d\n", src, dest, ret);
 539                 return ret;
 540         }
 541
 542         vsub = drm_format_vert_chroma_subsampling(pixel_format);
 543
 544         phasey_steps[COMP_0]   = phasey_step;
 545         phasey_steps[COMP_3]   = phasey_step;
 546         phasey_steps[COMP_1_2] = phasey_step / vsub;
 547
 548         return 0;
 549 }
 550
 551 static uint32_t get_scale_config(const struct mdp_format *format,
 552                 uint32_t src, uint32_t dst, bool horz)
 553 {
 554         bool scaling = format->is_yuv ? true : (src != dst);
 555         uint32_t sub, pix_fmt = format->base.pixel_format;
 556         uint32_t ya_filter, uv_filter;
 557         bool yuv = format->is_yuv;
 558
 559         if (!scaling)
 560                 return 0;
 561
 562         if (yuv) {
 563                 sub = horz ? drm_format_horz_chroma_subsampling(pix_fmt) :
 564                              drm_format_vert_chroma_subsampling(pix_fmt);
 565                 uv_filter = ((src / sub) <= dst) ?
 566                                    SCALE_FILTER_BIL : SCALE_FILTER_PCMN;
 567         }
 568         ya_filter = (src <= dst) ? SCALE_FILTER_BIL : SCALE_FILTER_PCMN;
 569
 570         if (horz)
 571                 return  MDP5_PIPE_SCALE_CONFIG_SCALEX_EN |
 572                         MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(ya_filter) |
 573                         MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(ya_filter) |
 574                         COND(yuv, MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2(uv_filter));
 575         else
 576                 return  MDP5_PIPE_SCALE_CONFIG_SCALEY_EN |
 577                         MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(ya_filter) |
 578                         MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3(ya_filter) |
 579                         COND(yuv, MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(uv_filter));
 580 }
 581
 582 static void calc_pixel_ext(const struct mdp_format *format,
 583                 uint32_t src, uint32_t dst, uint32_t phase_step[2],
 584                 int pix_ext_edge1[COMP_MAX], int pix_ext_edge2[COMP_MAX],
 585                 bool horz)
 586 {
 587         bool scaling = format->is_yuv ? true : (src != dst);
 588         int i;
 589
 590         /*
 591          * Note:
 592          * We assume here that:
 593          *     1. PCMN filter is used for downscale
 594          *     2. bilinear filter is used for upscale
 595          *     3. we are in a single pipe configuration
 596          */
 597
 598         for (i = 0; i < COMP_MAX; i++) {
 599                 pix_ext_edge1[i] = 0;
 600                 pix_ext_edge2[i] = scaling ? 1 : 0;
 601         }
 602 }
 603
 604 static void mdp5_write_pixel_ext(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe,
 605         const struct mdp_format *format,
 606         uint32_t src_w, int pe_left[COMP_MAX], int pe_right[COMP_MAX],
 607         uint32_t src_h, int pe_top[COMP_MAX], int pe_bottom[COMP_MAX])
 608 {
 609         uint32_t pix_fmt = format->base.pixel_format;
 610         uint32_t lr, tb, req;
 611         int i;
 612
 613         for (i = 0; i < COMP_MAX; i++) {
 614                 uint32_t roi_w = src_w;
 615                 uint32_t roi_h = src_h;
 616
 617                 if (format->is_yuv && i == COMP_1_2) {
 618                         roi_w /= drm_format_horz_chroma_subsampling(pix_fmt);
 619                         roi_h /= drm_format_vert_chroma_subsampling(pix_fmt);
 620                 }
 621
 622                 lr  = (pe_left[i] >= 0) ?
 623                         MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT(pe_left[i]) :
 624                         MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF(pe_left[i]);
 625
 626                 lr |= (pe_right[i] >= 0) ?
 627                         MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT(pe_right[i]) :
 628                         MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF(pe_right[i]);
 629
 630                 tb  = (pe_top[i] >= 0) ?
 631                         MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT(pe_top[i]) :
 632                         MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF(pe_top[i]);
 633
 634                 tb |= (pe_bottom[i] >= 0) ?
 635                         MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT(pe_bottom[i]) :
 636                         MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF(pe_bottom[i]);
 637
 638                 req  = MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT(roi_w +
 639                                 pe_left[i] + pe_right[i]);
 640
 641                 req |= MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM(roi_h +
 642                                 pe_top[i] + pe_bottom[i]);
 643
 644                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_LR(pipe, i), lr);
 645                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_TB(pipe, i), tb);
 646                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(pipe, i), req);
 647
 648                 DBG("comp-%d (L/R): rpt=%d/%d, ovf=%d/%d, req=%d", i,
 649                         FIELD(lr,  MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT),
 650                         FIELD(lr,  MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT),
 651                         FIELD(lr,  MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF),
 652                         FIELD(lr,  MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF),
 653                         FIELD(req, MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT));
 654
 655                 DBG("comp-%d (T/B): rpt=%d/%d, ovf=%d/%d, req=%d", i,
 656                         FIELD(tb,  MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT),
 657                         FIELD(tb,  MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT),
 658                         FIELD(tb,  MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF),
 659                         FIELD(tb,  MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF),
 660                         FIELD(req, MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM));
 661         }
 662 }
 663
 664
 665 static int mdp5_plane_mode_set(struct drm_plane *plane,
 666                 struct drm_crtc *crtc, struct drm_framebuffer *fb,
 667                 int crtc_x, int crtc_y,
 668                 unsigned int crtc_w, unsigned int crtc_h,
 669                 uint32_t src_x, uint32_t src_y,
 670                 uint32_t src_w, uint32_t src_h)
 671 {
 672         struct drm_plane_state *pstate = plane->state;
 673         struct mdp5_hw_pipe *hwpipe = to_mdp5_plane_state(pstate)->hwpipe;
 674         struct mdp5_kms *mdp5_kms = get_kms(plane);
 675         enum mdp5_pipe pipe = hwpipe->pipe;
 676         const struct mdp_format *format;
 677         uint32_t nplanes, config = 0;
 678         uint32_t phasex_step[COMP_MAX] = {0,}, phasey_step[COMP_MAX] = {0,};
 679         bool pe = hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT;
 680         int pe_left[COMP_MAX], pe_right[COMP_MAX];
 681         int pe_top[COMP_MAX], pe_bottom[COMP_MAX];
 682         uint32_t hdecm = 0, vdecm = 0;
 683         uint32_t pix_format;
 684         unsigned int rotation;
 685         bool vflip, hflip;
 686         unsigned long flags;
 687         int ret;
 688
 689         nplanes = drm_format_num_planes(fb->pixel_format);
 690
 691         /* bad formats should already be rejected: */
 692         if (WARN_ON(nplanes > pipe2nclients(pipe)))
 693                 return -EINVAL;
 694
 695         format = to_mdp_format(msm_framebuffer_format(fb));
 696         pix_format = format->base.pixel_format;
 697
 698         /* src values are in Q16 fixed point, convert to integer: */
 699         src_x = src_x >> 16;
 700         src_y = src_y >> 16;
 701         src_w = src_w >> 16;
 702         src_h = src_h >> 16;
 703
 704         DBG("%s: FB[%u] %u,%u,%u,%u -> CRTC[%u] %d,%d,%u,%u", plane->name,
 705                         fb->base.id, src_x, src_y, src_w, src_h,
 706                         crtc->base.id, crtc_x, crtc_y, crtc_w, crtc_h);
 707
 708         ret = calc_scalex_steps(plane, pix_format, src_w, crtc_w, phasex_step);
 709         if (ret)
 710                 return ret;
 711
 712         ret = calc_scaley_steps(plane, pix_format, src_h, crtc_h, phasey_step);
 713         if (ret)
 714                 return ret;
 715
 716         if (hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT) {
 717                 calc_pixel_ext(format, src_w, crtc_w, phasex_step,
 718                                          pe_left, pe_right, true);
 719                 calc_pixel_ext(format, src_h, crtc_h, phasey_step,
 720                                         pe_top, pe_bottom, false);
 721         }
 722
 723         /* TODO calc hdecm, vdecm */
 724
 725         /* SCALE is used to both scale and up-sample chroma components */
 726         config |= get_scale_config(format, src_w, crtc_w, true);
 727         config |= get_scale_config(format, src_h, crtc_h, false);
 728         DBG("scale config = %x", config);
 729
 730         rotation = drm_rotation_simplify(pstate->rotation,
 731                                          DRM_ROTATE_0 |
 732                                          DRM_REFLECT_X |
 733                                          DRM_REFLECT_Y);
 734         hflip = !!(rotation & DRM_REFLECT_X);
 735         vflip = !!(rotation & DRM_REFLECT_Y);
 736
 737         spin_lock_irqsave(&hwpipe->pipe_lock, flags);
 738
 739         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_IMG_SIZE(pipe),
 740                         MDP5_PIPE_SRC_IMG_SIZE_WIDTH(min(fb->width, src_w)) |
 741                         MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(min(fb->height, src_h)));
 742
 743         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_SIZE(pipe),
 744                         MDP5_PIPE_SRC_SIZE_WIDTH(src_w) |
 745                         MDP5_PIPE_SRC_SIZE_HEIGHT(src_h));
 746
 747         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_XY(pipe),
 748                         MDP5_PIPE_SRC_XY_X(src_x) |
 749                         MDP5_PIPE_SRC_XY_Y(src_y));
 750
 751         mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_SIZE(pipe),
 752                         MDP5_PIPE_OUT_SIZE_WIDTH(crtc_w) |
 753                         MDP5_PIPE_OUT_SIZE_HEIGHT(crtc_h));
 754
 755         mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_XY(pipe),
 756                         MDP5_PIPE_OUT_XY_X(crtc_x) |
 757                         MDP5_PIPE_OUT_XY_Y(crtc_y));
 758
 759         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_FORMAT(pipe),
 760                         MDP5_PIPE_SRC_FORMAT_A_BPC(format->bpc_a) |
 761                         MDP5_PIPE_SRC_FORMAT_R_BPC(format->bpc_r) |
 762                         MDP5_PIPE_SRC_FORMAT_G_BPC(format->bpc_g) |
 763                         MDP5_PIPE_SRC_FORMAT_B_BPC(format->bpc_b) |
 764                         COND(format->alpha_enable, MDP5_PIPE_SRC_FORMAT_ALPHA_ENABLE) |
 765                         MDP5_PIPE_SRC_FORMAT_CPP(format->cpp - 1) |
 766                         MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(format->unpack_count - 1) |
 767                         COND(format->unpack_tight, MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT) |
 768                         MDP5_PIPE_SRC_FORMAT_FETCH_TYPE(format->fetch_type) |
 769                         MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(format->chroma_sample));
 770
 771         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_UNPACK(pipe),
 772                         MDP5_PIPE_SRC_UNPACK_ELEM0(format->unpack[0]) |
 773                         MDP5_PIPE_SRC_UNPACK_ELEM1(format->unpack[1]) |
 774                         MDP5_PIPE_SRC_UNPACK_ELEM2(format->unpack[2]) |
 775                         MDP5_PIPE_SRC_UNPACK_ELEM3(format->unpack[3]));
 776
 777         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_OP_MODE(pipe),
 778                         (hflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_LR : 0) |
 779                         (vflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_UD : 0) |
 780                         COND(pe, MDP5_PIPE_SRC_OP_MODE_SW_PIX_EXT_OVERRIDE) |
 781                         MDP5_PIPE_SRC_OP_MODE_BWC(BWC_LOSSLESS));
 782
 783         /* not using secure mode: */
 784         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(pipe), 0);
 785
 786         if (hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT)
 787                 mdp5_write_pixel_ext(mdp5_kms, pipe, format,
 788                                 src_w, pe_left, pe_right,
 789                                 src_h, pe_top, pe_bottom);
 790
 791         if (hwpipe->caps & MDP_PIPE_CAP_SCALE) {
 792                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_X(pipe),
 793                                 phasex_step[COMP_0]);
 794                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(pipe),
 795                                 phasey_step[COMP_0]);
 796                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(pipe),
 797                                 phasex_step[COMP_1_2]);
 798                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(pipe),
 799                                 phasey_step[COMP_1_2]);
 800                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_DECIMATION(pipe),
 801                                 MDP5_PIPE_DECIMATION_VERT(vdecm) |
 802                                 MDP5_PIPE_DECIMATION_HORZ(hdecm));
 803                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CONFIG(pipe), config);
 804         }
 805
 806         if (hwpipe->caps & MDP_PIPE_CAP_CSC) {
 807                 if (MDP_FORMAT_IS_YUV(format))
 808                         csc_enable(mdp5_kms, pipe,
 809                                         mdp_get_default_csc_cfg(CSC_YUV2RGB));
 810                 else
 811                         csc_disable(mdp5_kms, pipe);
 812         }
 813
 814         set_scanout_locked(plane, fb);
 815
 816         spin_unlock_irqrestore(&hwpipe->pipe_lock, flags);
 817
 818         return ret;
 819 }
 820
 821 enum mdp5_pipe mdp5_plane_pipe(struct drm_plane *plane)
 822 {
 823         struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state);
 824
 825         if (WARN_ON(!pstate->hwpipe))
 826                 return 0;
 827
 828         return pstate->hwpipe->pipe;
 829 }
 830
 831 uint32_t mdp5_plane_get_flush(struct drm_plane *plane)
 832 {
 833         struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state);
 834
 835         if (WARN_ON(!pstate->hwpipe))
 836                 return 0;
 837
 838         return pstate->hwpipe->flush_mask;
 839 }
 840
 841 /* initialize plane */
 842 struct drm_plane *mdp5_plane_init(struct drm_device *dev, bool primary)
 843 {
 844         struct drm_plane *plane = NULL;
 845         struct mdp5_plane *mdp5_plane;
 846         int ret;
 847         enum drm_plane_type type;
 848
 849         mdp5_plane = kzalloc(sizeof(*mdp5_plane), GFP_KERNEL);
 850         if (!mdp5_plane) {
 851                 ret = -ENOMEM;
 852                 goto fail;
 853         }
 854
 855         plane = &mdp5_plane->base;
 856
 857         mdp5_plane->nformats = mdp_get_formats(mdp5_plane->formats,
 858                 ARRAY_SIZE(mdp5_plane->formats), false);
 859
 860         type = primary ? DRM_PLANE_TYPE_PRIMARY : DRM_PLANE_TYPE_OVERLAY;
 861         ret = drm_universal_plane_init(dev, plane, 0xff, &mdp5_plane_funcs,
 862                                  mdp5_plane->formats, mdp5_plane->nformats,
 863                                  type, NULL);
 864         if (ret)
 865                 goto fail;
 866
 867         drm_plane_helper_add(plane, &mdp5_plane_helper_funcs);
 868
 869         mdp5_plane_install_properties(plane, &plane->base);
 870
 871         return plane;
 872
 873 fail:
 874         if (plane)
 875                 mdp5_plane_destroy(plane);
 876
 877         return ERR_PTR(ret);
 878 }