drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c

   1 /*
   2  * Copyright (C) 2014-2015 The Linux Foundation. All rights reserved.
   3  * Copyright (C) 2013 Red Hat
   4  * Author: Rob Clark <robdclark@gmail.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published by
   8  * the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include <drm/drm_print.h>
  20 #include "mdp5_kms.h"
  21
  22 struct mdp5_plane {
  23         struct drm_plane base;
  24
  25         spinlock_t pipe_lock;     /* protect REG_MDP5_PIPE_* registers */
  26
  27         uint32_t nformats;
  28         uint32_t formats[32];
  29 };
  30 #define to_mdp5_plane(x) container_of(x, struct mdp5_plane, base)
  31
  32 static int mdp5_plane_mode_set(struct drm_plane *plane,
  33                 struct drm_crtc *crtc, struct drm_framebuffer *fb,
  34                 struct drm_rect *src, struct drm_rect *dest);
  35
  36 static int mdp5_update_cursor_plane_legacy(struct drm_plane *plane,
  37                 struct drm_crtc *crtc,
  38                 struct drm_framebuffer *fb,
  39                 int crtc_x, int crtc_y,
  40                 unsigned int crtc_w, unsigned int crtc_h,
  41                 uint32_t src_x, uint32_t src_y,
  42                 uint32_t src_w, uint32_t src_h,
  43                 struct drm_modeset_acquire_ctx *ctx);
  44
  45 static struct mdp5_kms *get_kms(struct drm_plane *plane)
  46 {
  47         struct msm_drm_private *priv = plane->dev->dev_private;
  48         return to_mdp5_kms(to_mdp_kms(priv->kms));
  49 }
  50
  51 static bool plane_enabled(struct drm_plane_state *state)
  52 {
  53         return state->visible;
  54 }
  55
  56 static void mdp5_plane_destroy(struct drm_plane *plane)
  57 {
  58         struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
  59
  60         drm_plane_helper_disable(plane);
  61         drm_plane_cleanup(plane);
  62
  63         kfree(mdp5_plane);
  64 }
  65
  66 static void mdp5_plane_install_rotation_property(struct drm_device *dev,
  67                 struct drm_plane *plane)
  68 {
  69         drm_plane_create_rotation_property(plane,
  70                                            DRM_ROTATE_0,
  71                                            DRM_ROTATE_0 |
  72                                            DRM_ROTATE_180 |
  73                                            DRM_REFLECT_X |
  74                                            DRM_REFLECT_Y);
  75 }
  76
  77 /* helper to install properties which are common to planes and crtcs */
  78 static void mdp5_plane_install_properties(struct drm_plane *plane,
  79                 struct drm_mode_object *obj)
  80 {
  81         struct drm_device *dev = plane->dev;
  82         struct msm_drm_private *dev_priv = dev->dev_private;
  83         struct drm_property *prop;
  84
  85 #define INSTALL_PROPERTY(name, NAME, init_val, fnc, ...) do { \
  86                 prop = dev_priv->plane_property[PLANE_PROP_##NAME]; \
  87                 if (!prop) { \
  88                         prop = drm_property_##fnc(dev, 0, #name, \
  89                                 ##__VA_ARGS__); \
  90                         if (!prop) { \
  91                                 dev_warn(dev->dev, \
  92                                         "Create property %s failed\n", \
  93                                         #name); \
  94                                 return; \
  95                         } \
  96                         dev_priv->plane_property[PLANE_PROP_##NAME] = prop; \
  97                 } \
  98                 drm_object_attach_property(&plane->base, prop, init_val); \
  99         } while (0)
 100
 101 #define INSTALL_RANGE_PROPERTY(name, NAME, min, max, init_val) \
 102                 INSTALL_PROPERTY(name, NAME, init_val, \
 103                                 create_range, min, max)
 104
 105 #define INSTALL_ENUM_PROPERTY(name, NAME, init_val) \
 106                 INSTALL_PROPERTY(name, NAME, init_val, \
 107                                 create_enum, name##_prop_enum_list, \
 108                                 ARRAY_SIZE(name##_prop_enum_list))
 109
 110         INSTALL_RANGE_PROPERTY(zpos, ZPOS, 1, 255, 1);
 111
 112         mdp5_plane_install_rotation_property(dev, plane);
 113
 114 #undef INSTALL_RANGE_PROPERTY
 115 #undef INSTALL_ENUM_PROPERTY
 116 #undef INSTALL_PROPERTY
 117 }
 118
 119 static int mdp5_plane_atomic_set_property(struct drm_plane *plane,
 120                 struct drm_plane_state *state, struct drm_property *property,
 121                 uint64_t val)
 122 {
 123         struct drm_device *dev = plane->dev;
 124         struct mdp5_plane_state *pstate;
 125         struct msm_drm_private *dev_priv = dev->dev_private;
 126         int ret = 0;
 127
 128         pstate = to_mdp5_plane_state(state);
 129
 130 #define SET_PROPERTY(name, NAME, type) do { \
 131                 if (dev_priv->plane_property[PLANE_PROP_##NAME] == property) { \
 132                         pstate->name = (type)val; \
 133                         DBG("Set property %s %d", #name, (type)val); \
 134                         goto done; \
 135                 } \
 136         } while (0)
 137
 138         SET_PROPERTY(zpos, ZPOS, uint8_t);
 139
 140         dev_err(dev->dev, "Invalid property\n");
 141         ret = -EINVAL;
 142 done:
 143         return ret;
 144 #undef SET_PROPERTY
 145 }
 146
 147 static int mdp5_plane_atomic_get_property(struct drm_plane *plane,
 148                 const struct drm_plane_state *state,
 149                 struct drm_property *property, uint64_t *val)
 150 {
 151         struct drm_device *dev = plane->dev;
 152         struct mdp5_plane_state *pstate;
 153         struct msm_drm_private *dev_priv = dev->dev_private;
 154         int ret = 0;
 155
 156         pstate = to_mdp5_plane_state(state);
 157
 158 #define GET_PROPERTY(name, NAME, type) do { \
 159                 if (dev_priv->plane_property[PLANE_PROP_##NAME] == property) { \
 160                         *val = pstate->name; \
 161                         DBG("Get property %s %lld", #name, *val); \
 162                         goto done; \
 163                 } \
 164         } while (0)
 165
 166         GET_PROPERTY(zpos, ZPOS, uint8_t);
 167
 168         dev_err(dev->dev, "Invalid property\n");
 169         ret = -EINVAL;
 170 done:
 171         return ret;
 172 #undef SET_PROPERTY
 173 }
 174
 175 static void
 176 mdp5_plane_atomic_print_state(struct drm_printer *p,
 177                 const struct drm_plane_state *state)
 178 {
 179         struct mdp5_plane_state *pstate = to_mdp5_plane_state(state);
 180         struct mdp5_kms *mdp5_kms = get_kms(state->plane);
 181
 182         drm_printf(p, "\thwpipe=%s\n", pstate->hwpipe ?
 183                         pstate->hwpipe->name : "(null)");
 184         if (mdp5_kms->caps & MDP_CAP_SRC_SPLIT)
 185                 drm_printf(p, "\tright-hwpipe=%s\n",
 186                            pstate->r_hwpipe ? pstate->r_hwpipe->name :
 187                                               "(null)");
 188         drm_printf(p, "\tpremultiplied=%u\n", pstate->premultiplied);
 189         drm_printf(p, "\tzpos=%u\n", pstate->zpos);
 190         drm_printf(p, "\talpha=%u\n", pstate->alpha);
 191         drm_printf(p, "\tstage=%s\n", stage2name(pstate->stage));
 192 }
 193
 194 static void mdp5_plane_reset(struct drm_plane *plane)
 195 {
 196         struct mdp5_plane_state *mdp5_state;
 197
 198         if (plane->state && plane->state->fb)
 199                 drm_framebuffer_unreference(plane->state->fb);
 200
 201         kfree(to_mdp5_plane_state(plane->state));
 202         mdp5_state = kzalloc(sizeof(*mdp5_state), GFP_KERNEL);
 203
 204         /* assign default blend parameters */
 205         mdp5_state->alpha = 255;
 206         mdp5_state->premultiplied = 0;
 207
 208         if (plane->type == DRM_PLANE_TYPE_PRIMARY)
 209                 mdp5_state->zpos = STAGE_BASE;
 210         else
 211                 mdp5_state->zpos = STAGE0 + drm_plane_index(plane);
 212
 213         mdp5_state->base.plane = plane;
 214
 215         plane->state = &mdp5_state->base;
 216 }
 217
 218 static struct drm_plane_state *
 219 mdp5_plane_duplicate_state(struct drm_plane *plane)
 220 {
 221         struct mdp5_plane_state *mdp5_state;
 222
 223         if (WARN_ON(!plane->state))
 224                 return NULL;
 225
 226         mdp5_state = kmemdup(to_mdp5_plane_state(plane->state),
 227                         sizeof(*mdp5_state), GFP_KERNEL);
 228
 229         if (mdp5_state && mdp5_state->base.fb)
 230                 drm_framebuffer_reference(mdp5_state->base.fb);
 231
 232         return &mdp5_state->base;
 233 }
 234
 235 static void mdp5_plane_destroy_state(struct drm_plane *plane,
 236                 struct drm_plane_state *state)
 237 {
 238         struct mdp5_plane_state *pstate = to_mdp5_plane_state(state);
 239
 240         if (state->fb)
 241                 drm_framebuffer_unreference(state->fb);
 242
 243         kfree(pstate);
 244 }
 245
 246 static const struct drm_plane_funcs mdp5_plane_funcs = {
 247                 .update_plane = drm_atomic_helper_update_plane,
 248                 .disable_plane = drm_atomic_helper_disable_plane,
 249                 .destroy = mdp5_plane_destroy,
 250                 .set_property = drm_atomic_helper_plane_set_property,
 251                 .atomic_set_property = mdp5_plane_atomic_set_property,
 252                 .atomic_get_property = mdp5_plane_atomic_get_property,
 253                 .reset = mdp5_plane_reset,
 254                 .atomic_duplicate_state = mdp5_plane_duplicate_state,
 255                 .atomic_destroy_state = mdp5_plane_destroy_state,
 256                 .atomic_print_state = mdp5_plane_atomic_print_state,
 257 };
 258
 259 static const struct drm_plane_funcs mdp5_cursor_plane_funcs = {
 260                 .update_plane = mdp5_update_cursor_plane_legacy,
 261                 .disable_plane = drm_atomic_helper_disable_plane,
 262                 .destroy = mdp5_plane_destroy,
 263                 .set_property = drm_atomic_helper_plane_set_property,
 264                 .atomic_set_property = mdp5_plane_atomic_set_property,
 265                 .atomic_get_property = mdp5_plane_atomic_get_property,
 266                 .reset = mdp5_plane_reset,
 267                 .atomic_duplicate_state = mdp5_plane_duplicate_state,
 268                 .atomic_destroy_state = mdp5_plane_destroy_state,
 269                 .atomic_print_state = mdp5_plane_atomic_print_state,
 270 };
 271
 272 static int mdp5_plane_prepare_fb(struct drm_plane *plane,
 273                                  struct drm_plane_state *new_state)
 274 {
 275         struct mdp5_kms *mdp5_kms = get_kms(plane);
 276         struct drm_framebuffer *fb = new_state->fb;
 277
 278         if (!new_state->fb)
 279                 return 0;
 280
 281         DBG("%s: prepare: FB[%u]", plane->name, fb->base.id);
 282         return msm_framebuffer_prepare(fb, mdp5_kms->id);
 283 }
 284
 285 static void mdp5_plane_cleanup_fb(struct drm_plane *plane,
 286                                   struct drm_plane_state *old_state)
 287 {
 288         struct mdp5_kms *mdp5_kms = get_kms(plane);
 289         struct drm_framebuffer *fb = old_state->fb;
 290
 291         if (!fb)
 292                 return;
 293
 294         DBG("%s: cleanup: FB[%u]", plane->name, fb->base.id);
 295         msm_framebuffer_cleanup(fb, mdp5_kms->id);
 296 }
 297
 298 #define FRAC_16_16(mult, div)    (((mult) << 16) / (div))
 299 static int mdp5_plane_atomic_check_with_state(struct drm_crtc_state *crtc_state,
 300                                               struct drm_plane_state *state)
 301 {
 302         struct mdp5_plane_state *mdp5_state = to_mdp5_plane_state(state);
 303         struct drm_plane *plane = state->plane;
 304         struct drm_plane_state *old_state = plane->state;
 305         struct mdp5_cfg *config = mdp5_cfg_get_config(get_kms(plane)->cfg);
 306         bool new_hwpipe = false;
 307         bool need_right_hwpipe = false;
 308         uint32_t max_width, max_height;
 309         bool out_of_bounds = false;
 310         uint32_t caps = 0;
 311         struct drm_rect clip;
 312         int min_scale, max_scale;
 313         int ret;
 314
 315         DBG("%s: check (%d -> %d)", plane->name,
 316                         plane_enabled(old_state), plane_enabled(state));
 317
 318         max_width = config->hw->lm.max_width << 16;
 319         max_height = config->hw->lm.max_height << 16;
 320
 321         /* Make sure source dimensions are within bounds. */
 322         if (state->src_h > max_height)
 323                 out_of_bounds = true;
 324
 325         if (state->src_w > max_width) {
 326                 /* If source split is supported, we can go up to 2x
 327                  * the max LM width, but we'd need to stage another
 328                  * hwpipe to the right LM. So, the drm_plane would
 329                  * consist of 2 hwpipes.
 330                  */
 331                 if (config->hw->mdp.caps & MDP_CAP_SRC_SPLIT &&
 332                     (state->src_w <= 2 * max_width))
 333                         need_right_hwpipe = true;
 334                 else
 335                         out_of_bounds = true;
 336         }
 337
 338         if (out_of_bounds) {
 339                 struct drm_rect src = drm_plane_state_src(state);
 340                 DBG("Invalid source size "DRM_RECT_FP_FMT,
 341                                 DRM_RECT_FP_ARG(&src));
 342                 return -ERANGE;
 343         }
 344
 345         clip.x1 = 0;
 346         clip.y1 = 0;
 347         clip.x2 = crtc_state->adjusted_mode.hdisplay;
 348         clip.y2 = crtc_state->adjusted_mode.vdisplay;
 349         min_scale = FRAC_16_16(1, 8);
 350         max_scale = FRAC_16_16(8, 1);
 351
 352         ret = drm_plane_helper_check_state(state, &clip, min_scale,
 353                                            max_scale, true, true);
 354         if (ret)
 355                 return ret;
 356
 357         if (plane_enabled(state)) {
 358                 unsigned int rotation;
 359                 const struct mdp_format *format;
 360                 struct mdp5_kms *mdp5_kms = get_kms(plane);
 361                 uint32_t blkcfg = 0;
 362
 363                 format = to_mdp_format(msm_framebuffer_format(state->fb));
 364                 if (MDP_FORMAT_IS_YUV(format))
 365                         caps |= MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC;
 366
 367                 if (((state->src_w >> 16) != state->crtc_w) ||
 368                                 ((state->src_h >> 16) != state->crtc_h))
 369                         caps |= MDP_PIPE_CAP_SCALE;
 370
 371                 rotation = drm_rotation_simplify(state->rotation,
 372                                                  DRM_ROTATE_0 |
 373                                                  DRM_REFLECT_X |
 374                                                  DRM_REFLECT_Y);
 375
 376                 if (rotation & DRM_REFLECT_X)
 377                         caps |= MDP_PIPE_CAP_HFLIP;
 378
 379                 if (rotation & DRM_REFLECT_Y)
 380                         caps |= MDP_PIPE_CAP_VFLIP;
 381
 382                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
 383                         caps |= MDP_PIPE_CAP_CURSOR;
 384
 385                 /* (re)allocate hw pipe if we don't have one or caps-mismatch: */
 386                 if (!mdp5_state->hwpipe || (caps & ~mdp5_state->hwpipe->caps))
 387                         new_hwpipe = true;
 388
 389                 /*
 390                  * (re)allocte hw pipe if we're either requesting for 2 hw pipes
 391                  * or we're switching from 2 hw pipes to 1 hw pipe because the
 392                  * new src_w can be supported by 1 hw pipe itself.
 393                  */
 394                 if ((need_right_hwpipe && !mdp5_state->r_hwpipe) ||
 395                     (!need_right_hwpipe && mdp5_state->r_hwpipe))
 396                         new_hwpipe = true;
 397
 398                 if (mdp5_kms->smp) {
 399                         const struct mdp_format *format =
 400                                 to_mdp_format(msm_framebuffer_format(state->fb));
 401
 402                         blkcfg = mdp5_smp_calculate(mdp5_kms->smp, format,
 403                                         state->src_w >> 16, false);
 404
 405                         if (mdp5_state->hwpipe && (mdp5_state->hwpipe->blkcfg != blkcfg))
 406                                 new_hwpipe = true;
 407                 }
 408
 409                 /* (re)assign hwpipe if needed, otherwise keep old one: */
 410                 if (new_hwpipe) {
 411                         /* TODO maybe we want to re-assign hwpipe sometimes
 412                          * in cases when we no-longer need some caps to make
 413                          * it available for other planes?
 414                          */
 415                         struct mdp5_hw_pipe *old_hwpipe = mdp5_state->hwpipe;
 416                         struct mdp5_hw_pipe *old_right_hwpipe =
 417                                                           mdp5_state->r_hwpipe;
 418
 419                         mdp5_state->hwpipe = mdp5_pipe_assign(state->state,
 420                                         plane, caps, blkcfg);
 421                         if (IS_ERR(mdp5_state->hwpipe)) {
 422                                 DBG("%s: failed to assign hwpipe!", plane->name);
 423                                 return PTR_ERR(mdp5_state->hwpipe);
 424                         }
 425
 426                         if (need_right_hwpipe) {
 427                                 mdp5_state->r_hwpipe =
 428                                         mdp5_pipe_assign(state->state, plane,
 429                                                          caps, blkcfg);
 430                                 if (IS_ERR(mdp5_state->r_hwpipe)) {
 431                                         DBG("%s: failed to assign right hwpipe",
 432                                             plane->name);
 433                                         return PTR_ERR(mdp5_state->r_hwpipe);
 434                                 }
 435                         } else {
 436                                 /*
 437                                  * set it to NULL so that the driver knows we
 438                                  * don't have a right hwpipe when committing a
 439                                  * new state
 440                                  */
 441                                 mdp5_state->r_hwpipe = NULL;
 442                         }
 443
 444                         mdp5_pipe_release(state->state, old_hwpipe);
 445                         mdp5_pipe_release(state->state, old_right_hwpipe);
 446                 }
 447         }
 448
 449         return 0;
 450 }
 451
 452 static int mdp5_plane_atomic_check(struct drm_plane *plane,
 453                                    struct drm_plane_state *state)
 454 {
 455         struct drm_crtc *crtc;
 456         struct drm_crtc_state *crtc_state;
 457
 458         crtc = state->crtc ? state->crtc : plane->state->crtc;
 459         if (!crtc)
 460                 return 0;
 461
 462         crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc);
 463         if (WARN_ON(!crtc_state))
 464                 return -EINVAL;
 465
 466         return mdp5_plane_atomic_check_with_state(crtc_state, state);
 467 }
 468
 469 static void mdp5_plane_atomic_update(struct drm_plane *plane,
 470                                      struct drm_plane_state *old_state)
 471 {
 472         struct drm_plane_state *state = plane->state;
 473
 474         DBG("%s: update", plane->name);
 475
 476         if (plane_enabled(state)) {
 477                 int ret;
 478
 479                 ret = mdp5_plane_mode_set(plane,
 480                                 state->crtc, state->fb,
 481                                 &state->src, &state->dst);
 482                 /* atomic_check should have ensured that this doesn't fail */
 483                 WARN_ON(ret < 0);
 484         }
 485 }
 486
 487 static const struct drm_plane_helper_funcs mdp5_plane_helper_funcs = {
 488                 .prepare_fb = mdp5_plane_prepare_fb,
 489                 .cleanup_fb = mdp5_plane_cleanup_fb,
 490                 .atomic_check = mdp5_plane_atomic_check,
 491                 .atomic_update = mdp5_plane_atomic_update,
 492 };
 493
 494 static void set_scanout_locked(struct mdp5_kms *mdp5_kms,
 495                                enum mdp5_pipe pipe,
 496                                struct drm_framebuffer *fb)
 497 {
 498         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_A(pipe),
 499                         MDP5_PIPE_SRC_STRIDE_A_P0(fb->pitches[0]) |
 500                         MDP5_PIPE_SRC_STRIDE_A_P1(fb->pitches[1]));
 501
 502         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_B(pipe),
 503                         MDP5_PIPE_SRC_STRIDE_B_P2(fb->pitches[2]) |
 504                         MDP5_PIPE_SRC_STRIDE_B_P3(fb->pitches[3]));
 505
 506         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC0_ADDR(pipe),
 507                         msm_framebuffer_iova(fb, mdp5_kms->id, 0));
 508         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC1_ADDR(pipe),
 509                         msm_framebuffer_iova(fb, mdp5_kms->id, 1));
 510         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC2_ADDR(pipe),
 511                         msm_framebuffer_iova(fb, mdp5_kms->id, 2));
 512         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC3_ADDR(pipe),
 513                         msm_framebuffer_iova(fb, mdp5_kms->id, 3));
 514 }
 515
 516 /* Note: mdp5_plane->pipe_lock must be locked */
 517 static void csc_disable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe)
 518 {
 519         uint32_t value = mdp5_read(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe)) &
 520                          ~MDP5_PIPE_OP_MODE_CSC_1_EN;
 521
 522         mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), value);
 523 }
 524
 525 /* Note: mdp5_plane->pipe_lock must be locked */
 526 static void csc_enable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe,
 527                 struct csc_cfg *csc)
 528 {
 529         uint32_t  i, mode = 0; /* RGB, no CSC */
 530         uint32_t *matrix;
 531
 532         if (unlikely(!csc))
 533                 return;
 534
 535         if ((csc->type == CSC_YUV2RGB) || (CSC_YUV2YUV == csc->type))
 536                 mode |= MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT(DATA_FORMAT_YUV);
 537         if ((csc->type == CSC_RGB2YUV) || (CSC_YUV2YUV == csc->type))
 538                 mode |= MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT(DATA_FORMAT_YUV);
 539         mode |= MDP5_PIPE_OP_MODE_CSC_1_EN;
 540         mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), mode);
 541
 542         matrix = csc->matrix;
 543         mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(pipe),
 544                         MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11(matrix[0]) |
 545                         MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12(matrix[1]));
 546         mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(pipe),
 547                         MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13(matrix[2]) |
 548                         MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21(matrix[3]));
 549         mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(pipe),
 550                         MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22(matrix[4]) |
 551                         MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23(matrix[5]));
 552         mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(pipe),
 553                         MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31(matrix[6]) |
 554                         MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32(matrix[7]));
 555         mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(pipe),
 556                         MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33(matrix[8]));
 557
 558         for (i = 0; i < ARRAY_SIZE(csc->pre_bias); i++) {
 559                 uint32_t *pre_clamp = csc->pre_clamp;
 560                 uint32_t *post_clamp = csc->post_clamp;
 561
 562                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_CLAMP(pipe, i),
 563                         MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH(pre_clamp[2*i+1]) |
 564                         MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW(pre_clamp[2*i]));
 565
 566                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_CLAMP(pipe, i),
 567                         MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH(post_clamp[2*i+1]) |
 568                         MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW(post_clamp[2*i]));
 569
 570                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_BIAS(pipe, i),
 571                         MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE(csc->pre_bias[i]));
 572
 573                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_BIAS(pipe, i),
 574                         MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE(csc->post_bias[i]));
 575         }
 576 }
 577
 578 #define PHASE_STEP_SHIFT        21
 579 #define DOWN_SCALE_RATIO_MAX    32      /* 2^(26-21) */
 580
 581 static int calc_phase_step(uint32_t src, uint32_t dst, uint32_t *out_phase)
 582 {
 583         uint32_t unit;
 584
 585         if (src == 0 || dst == 0)
 586                 return -EINVAL;
 587
 588         /*
 589          * PHASE_STEP_X/Y is coded on 26 bits (25:0),
 590          * where 2^21 represents the unity "1" in fixed-point hardware design.
 591          * This leaves 5 bits for the integer part (downscale case):
 592          *      -> maximum downscale ratio = 0b1_1111 = 31
 593          */
 594         if (src > (dst * DOWN_SCALE_RATIO_MAX))
 595                 return -EOVERFLOW;
 596
 597         unit = 1 << PHASE_STEP_SHIFT;
 598         *out_phase = mult_frac(unit, src, dst);
 599
 600         return 0;
 601 }
 602
 603 static int calc_scalex_steps(struct drm_plane *plane,
 604                 uint32_t pixel_format, uint32_t src, uint32_t dest,
 605                 uint32_t phasex_steps[COMP_MAX])
 606 {
 607         struct mdp5_kms *mdp5_kms = get_kms(plane);
 608         struct device *dev = mdp5_kms->dev->dev;
 609         uint32_t phasex_step;
 610         unsigned int hsub;
 611         int ret;
 612
 613         ret = calc_phase_step(src, dest, &phasex_step);
 614         if (ret) {
 615                 dev_err(dev, "X scaling (%d->%d) failed: %d\n", src, dest, ret);
 616                 return ret;
 617         }
 618
 619         hsub = drm_format_horz_chroma_subsampling(pixel_format);
 620
 621         phasex_steps[COMP_0]   = phasex_step;
 622         phasex_steps[COMP_3]   = phasex_step;
 623         phasex_steps[COMP_1_2] = phasex_step / hsub;
 624
 625         return 0;
 626 }
 627
 628 static int calc_scaley_steps(struct drm_plane *plane,
 629                 uint32_t pixel_format, uint32_t src, uint32_t dest,
 630                 uint32_t phasey_steps[COMP_MAX])
 631 {
 632         struct mdp5_kms *mdp5_kms = get_kms(plane);
 633         struct device *dev = mdp5_kms->dev->dev;
 634         uint32_t phasey_step;
 635         unsigned int vsub;
 636         int ret;
 637
 638         ret = calc_phase_step(src, dest, &phasey_step);
 639         if (ret) {
 640                 dev_err(dev, "Y scaling (%d->%d) failed: %d\n", src, dest, ret);
 641                 return ret;
 642         }
 643
 644         vsub = drm_format_vert_chroma_subsampling(pixel_format);
 645
 646         phasey_steps[COMP_0]   = phasey_step;
 647         phasey_steps[COMP_3]   = phasey_step;
 648         phasey_steps[COMP_1_2] = phasey_step / vsub;
 649
 650         return 0;
 651 }
 652
 653 static uint32_t get_scale_config(const struct mdp_format *format,
 654                 uint32_t src, uint32_t dst, bool horz)
 655 {
 656         bool scaling = format->is_yuv ? true : (src != dst);
 657         uint32_t sub, pix_fmt = format->base.pixel_format;
 658         uint32_t ya_filter, uv_filter;
 659         bool yuv = format->is_yuv;
 660
 661         if (!scaling)
 662                 return 0;
 663
 664         if (yuv) {
 665                 sub = horz ? drm_format_horz_chroma_subsampling(pix_fmt) :
 666                              drm_format_vert_chroma_subsampling(pix_fmt);
 667                 uv_filter = ((src / sub) <= dst) ?
 668                                    SCALE_FILTER_BIL : SCALE_FILTER_PCMN;
 669         }
 670         ya_filter = (src <= dst) ? SCALE_FILTER_BIL : SCALE_FILTER_PCMN;
 671
 672         if (horz)
 673                 return  MDP5_PIPE_SCALE_CONFIG_SCALEX_EN |
 674                         MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(ya_filter) |
 675                         MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(ya_filter) |
 676                         COND(yuv, MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2(uv_filter));
 677         else
 678                 return  MDP5_PIPE_SCALE_CONFIG_SCALEY_EN |
 679                         MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(ya_filter) |
 680                         MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3(ya_filter) |
 681                         COND(yuv, MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(uv_filter));
 682 }
 683
 684 static void calc_pixel_ext(const struct mdp_format *format,
 685                 uint32_t src, uint32_t dst, uint32_t phase_step[2],
 686                 int pix_ext_edge1[COMP_MAX], int pix_ext_edge2[COMP_MAX],
 687                 bool horz)
 688 {
 689         bool scaling = format->is_yuv ? true : (src != dst);
 690         int i;
 691
 692         /*
 693          * Note:
 694          * We assume here that:
 695          *     1. PCMN filter is used for downscale
 696          *     2. bilinear filter is used for upscale
 697          *     3. we are in a single pipe configuration
 698          */
 699
 700         for (i = 0; i < COMP_MAX; i++) {
 701                 pix_ext_edge1[i] = 0;
 702                 pix_ext_edge2[i] = scaling ? 1 : 0;
 703         }
 704 }
 705
 706 static void mdp5_write_pixel_ext(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe,
 707         const struct mdp_format *format,
 708         uint32_t src_w, int pe_left[COMP_MAX], int pe_right[COMP_MAX],
 709         uint32_t src_h, int pe_top[COMP_MAX], int pe_bottom[COMP_MAX])
 710 {
 711         uint32_t pix_fmt = format->base.pixel_format;
 712         uint32_t lr, tb, req;
 713         int i;
 714
 715         for (i = 0; i < COMP_MAX; i++) {
 716                 uint32_t roi_w = src_w;
 717                 uint32_t roi_h = src_h;
 718
 719                 if (format->is_yuv && i == COMP_1_2) {
 720                         roi_w /= drm_format_horz_chroma_subsampling(pix_fmt);
 721                         roi_h /= drm_format_vert_chroma_subsampling(pix_fmt);
 722                 }
 723
 724                 lr  = (pe_left[i] >= 0) ?
 725                         MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT(pe_left[i]) :
 726                         MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF(pe_left[i]);
 727
 728                 lr |= (pe_right[i] >= 0) ?
 729                         MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT(pe_right[i]) :
 730                         MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF(pe_right[i]);
 731
 732                 tb  = (pe_top[i] >= 0) ?
 733                         MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT(pe_top[i]) :
 734                         MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF(pe_top[i]);
 735
 736                 tb |= (pe_bottom[i] >= 0) ?
 737                         MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT(pe_bottom[i]) :
 738                         MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF(pe_bottom[i]);
 739
 740                 req  = MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT(roi_w +
 741                                 pe_left[i] + pe_right[i]);
 742
 743                 req |= MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM(roi_h +
 744                                 pe_top[i] + pe_bottom[i]);
 745
 746                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_LR(pipe, i), lr);
 747                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_TB(pipe, i), tb);
 748                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(pipe, i), req);
 749
 750                 DBG("comp-%d (L/R): rpt=%d/%d, ovf=%d/%d, req=%d", i,
 751                         FIELD(lr,  MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT),
 752                         FIELD(lr,  MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT),
 753                         FIELD(lr,  MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF),
 754                         FIELD(lr,  MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF),
 755                         FIELD(req, MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT));
 756
 757                 DBG("comp-%d (T/B): rpt=%d/%d, ovf=%d/%d, req=%d", i,
 758                         FIELD(tb,  MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT),
 759                         FIELD(tb,  MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT),
 760                         FIELD(tb,  MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF),
 761                         FIELD(tb,  MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF),
 762                         FIELD(req, MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM));
 763         }
 764 }
 765
 766 struct pixel_ext {
 767         int left[COMP_MAX];
 768         int right[COMP_MAX];
 769         int top[COMP_MAX];
 770         int bottom[COMP_MAX];
 771 };
 772
 773 struct phase_step {
 774         u32 x[COMP_MAX];
 775         u32 y[COMP_MAX];
 776 };
 777
 778 static void mdp5_hwpipe_mode_set(struct mdp5_kms *mdp5_kms,
 779                                  struct mdp5_hw_pipe *hwpipe,
 780                                  struct drm_framebuffer *fb,
 781                                  struct phase_step *step,
 782                                  struct pixel_ext *pe,
 783                                  u32 scale_config, u32 hdecm, u32 vdecm,
 784                                  bool hflip, bool vflip,
 785                                  int crtc_x, int crtc_y,
 786                                  unsigned int crtc_w, unsigned int crtc_h,
 787                                  u32 src_img_w, u32 src_img_h,
 788                                  u32 src_x, u32 src_y,
 789                                  u32 src_w, u32 src_h)
 790 {
 791         enum mdp5_pipe pipe = hwpipe->pipe;
 792         bool has_pe = hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT;
 793         const struct mdp_format *format =
 794                         to_mdp_format(msm_framebuffer_format(fb));
 795
 796         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_IMG_SIZE(pipe),
 797                         MDP5_PIPE_SRC_IMG_SIZE_WIDTH(src_img_w) |
 798                         MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(src_img_h));
 799
 800         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_SIZE(pipe),
 801                         MDP5_PIPE_SRC_SIZE_WIDTH(src_w) |
 802                         MDP5_PIPE_SRC_SIZE_HEIGHT(src_h));
 803
 804         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_XY(pipe),
 805                         MDP5_PIPE_SRC_XY_X(src_x) |
 806                         MDP5_PIPE_SRC_XY_Y(src_y));
 807
 808         mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_SIZE(pipe),
 809                         MDP5_PIPE_OUT_SIZE_WIDTH(crtc_w) |
 810                         MDP5_PIPE_OUT_SIZE_HEIGHT(crtc_h));
 811
 812         mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_XY(pipe),
 813                         MDP5_PIPE_OUT_XY_X(crtc_x) |
 814                         MDP5_PIPE_OUT_XY_Y(crtc_y));
 815
 816         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_FORMAT(pipe),
 817                         MDP5_PIPE_SRC_FORMAT_A_BPC(format->bpc_a) |
 818                         MDP5_PIPE_SRC_FORMAT_R_BPC(format->bpc_r) |
 819                         MDP5_PIPE_SRC_FORMAT_G_BPC(format->bpc_g) |
 820                         MDP5_PIPE_SRC_FORMAT_B_BPC(format->bpc_b) |
 821                         COND(format->alpha_enable, MDP5_PIPE_SRC_FORMAT_ALPHA_ENABLE) |
 822                         MDP5_PIPE_SRC_FORMAT_CPP(format->cpp - 1) |
 823                         MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(format->unpack_count - 1) |
 824                         COND(format->unpack_tight, MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT) |
 825                         MDP5_PIPE_SRC_FORMAT_FETCH_TYPE(format->fetch_type) |
 826                         MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(format->chroma_sample));
 827
 828         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_UNPACK(pipe),
 829                         MDP5_PIPE_SRC_UNPACK_ELEM0(format->unpack[0]) |
 830                         MDP5_PIPE_SRC_UNPACK_ELEM1(format->unpack[1]) |
 831                         MDP5_PIPE_SRC_UNPACK_ELEM2(format->unpack[2]) |
 832                         MDP5_PIPE_SRC_UNPACK_ELEM3(format->unpack[3]));
 833
 834         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_OP_MODE(pipe),
 835                         (hflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_LR : 0) |
 836                         (vflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_UD : 0) |
 837                         COND(has_pe, MDP5_PIPE_SRC_OP_MODE_SW_PIX_EXT_OVERRIDE) |
 838                         MDP5_PIPE_SRC_OP_MODE_BWC(BWC_LOSSLESS));
 839
 840         /* not using secure mode: */
 841         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(pipe), 0);
 842
 843         if (hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT)
 844                 mdp5_write_pixel_ext(mdp5_kms, pipe, format,
 845                                 src_w, pe->left, pe->right,
 846                                 src_h, pe->top, pe->bottom);
 847
 848         if (hwpipe->caps & MDP_PIPE_CAP_SCALE) {
 849                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_X(pipe),
 850                                 step->x[COMP_0]);
 851                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(pipe),
 852                                 step->y[COMP_0]);
 853                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(pipe),
 854                                 step->x[COMP_1_2]);
 855                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(pipe),
 856                                 step->y[COMP_1_2]);
 857                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_DECIMATION(pipe),
 858                                 MDP5_PIPE_DECIMATION_VERT(vdecm) |
 859                                 MDP5_PIPE_DECIMATION_HORZ(hdecm));
 860                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CONFIG(pipe),
 861                            scale_config);
 862         }
 863
 864         if (hwpipe->caps & MDP_PIPE_CAP_CSC) {
 865                 if (MDP_FORMAT_IS_YUV(format))
 866                         csc_enable(mdp5_kms, pipe,
 867                                         mdp_get_default_csc_cfg(CSC_YUV2RGB));
 868                 else
 869                         csc_disable(mdp5_kms, pipe);
 870         }
 871
 872         set_scanout_locked(mdp5_kms, pipe, fb);
 873 }
 874
 875 static int mdp5_plane_mode_set(struct drm_plane *plane,
 876                 struct drm_crtc *crtc, struct drm_framebuffer *fb,
 877                 struct drm_rect *src, struct drm_rect *dest)
 878 {
 879         struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
 880         struct drm_plane_state *pstate = plane->state;
 881         struct mdp5_hw_pipe *hwpipe = to_mdp5_plane_state(pstate)->hwpipe;
 882         struct mdp5_kms *mdp5_kms = get_kms(plane);
 883         enum mdp5_pipe pipe = hwpipe->pipe;
 884         struct mdp5_hw_pipe *right_hwpipe;
 885         const struct mdp_format *format;
 886         uint32_t nplanes, config = 0;
 887         struct phase_step step = { 0 };
 888         struct pixel_ext pe = { 0 };
 889         uint32_t hdecm = 0, vdecm = 0;
 890         uint32_t pix_format;
 891         unsigned int rotation;
 892         bool vflip, hflip;
 893         int crtc_x, crtc_y;
 894         unsigned int crtc_w, crtc_h;
 895         uint32_t src_x, src_y;
 896         uint32_t src_w, src_h;
 897         uint32_t src_img_w, src_img_h;
 898         uint32_t src_x_r;
 899         int crtc_x_r;
 900         unsigned long flags;
 901         int ret;
 902
 903         nplanes = fb->format->num_planes;
 904
 905         /* bad formats should already be rejected: */
 906         if (WARN_ON(nplanes > pipe2nclients(pipe)))
 907                 return -EINVAL;
 908
 909         format = to_mdp_format(msm_framebuffer_format(fb));
 910         pix_format = format->base.pixel_format;
 911
 912         src_x = src->x1;
 913         src_y = src->y1;
 914         src_w = drm_rect_width(src);
 915         src_h = drm_rect_height(src);
 916
 917         crtc_x = dest->x1;
 918         crtc_y = dest->y1;
 919         crtc_w = drm_rect_width(dest);
 920         crtc_h = drm_rect_height(dest);
 921
 922         /* src values are in Q16 fixed point, convert to integer: */
 923         src_x = src_x >> 16;
 924         src_y = src_y >> 16;
 925         src_w = src_w >> 16;
 926         src_h = src_h >> 16;
 927
 928         src_img_w = min(fb->width, src_w);
 929         src_img_h = min(fb->height, src_h);
 930
 931         DBG("%s: FB[%u] %u,%u,%u,%u -> CRTC[%u] %d,%d,%u,%u", plane->name,
 932                         fb->base.id, src_x, src_y, src_w, src_h,
 933                         crtc->base.id, crtc_x, crtc_y, crtc_w, crtc_h);
 934
 935         right_hwpipe = to_mdp5_plane_state(pstate)->r_hwpipe;
 936         if (right_hwpipe) {
 937                 /*
 938                  * if the plane comprises of 2 hw pipes, assume that the width
 939                  * is split equally across them. The only parameters that varies
 940                  * between the 2 pipes are src_x and crtc_x
 941                  */
 942                 crtc_w /= 2;
 943                 src_w /= 2;
 944                 src_img_w /= 2;
 945
 946                 crtc_x_r = crtc_x + crtc_w;
 947                 src_x_r = src_x + src_w;
 948         }
 949
 950         ret = calc_scalex_steps(plane, pix_format, src_w, crtc_w, step.x);
 951         if (ret)
 952                 return ret;
 953
 954         ret = calc_scaley_steps(plane, pix_format, src_h, crtc_h, step.y);
 955         if (ret)
 956                 return ret;
 957
 958         if (hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT) {
 959                 calc_pixel_ext(format, src_w, crtc_w, step.x,
 960                                pe.left, pe.right, true);
 961                 calc_pixel_ext(format, src_h, crtc_h, step.y,
 962                                pe.top, pe.bottom, false);
 963         }
 964
 965         /* TODO calc hdecm, vdecm */
 966
 967         /* SCALE is used to both scale and up-sample chroma components */
 968         config |= get_scale_config(format, src_w, crtc_w, true);
 969         config |= get_scale_config(format, src_h, crtc_h, false);
 970         DBG("scale config = %x", config);
 971
 972         rotation = drm_rotation_simplify(pstate->rotation,
 973                                          DRM_ROTATE_0 |
 974                                          DRM_REFLECT_X |
 975                                          DRM_REFLECT_Y);
 976         hflip = !!(rotation & DRM_REFLECT_X);
 977         vflip = !!(rotation & DRM_REFLECT_Y);
 978
 979         spin_lock_irqsave(&mdp5_plane->pipe_lock, flags);
 980
 981         mdp5_hwpipe_mode_set(mdp5_kms, hwpipe, fb, &step, &pe,
 982                              config, hdecm, vdecm, hflip, vflip,
 983                              crtc_x, crtc_y, crtc_w, crtc_h,
 984                              src_img_w, src_img_h,
 985                              src_x, src_y, src_w, src_h);
 986         if (right_hwpipe)
 987                 mdp5_hwpipe_mode_set(mdp5_kms, right_hwpipe, fb, &step, &pe,
 988                                      config, hdecm, vdecm, hflip, vflip,
 989                                      crtc_x_r, crtc_y, crtc_w, crtc_h,
 990                                      src_img_w, src_img_h,
 991                                      src_x_r, src_y, src_w, src_h);
 992
 993         spin_unlock_irqrestore(&mdp5_plane->pipe_lock, flags);
 994
 995         plane->fb = fb;
 996
 997         return ret;
 998 }
 999
1000 static int mdp5_update_cursor_plane_legacy(struct drm_plane *plane,
1001                         struct drm_crtc *crtc, struct drm_framebuffer *fb,
1002                         int crtc_x, int crtc_y,
1003                         unsigned int crtc_w, unsigned int crtc_h,
1004                         uint32_t src_x, uint32_t src_y,
1005                         uint32_t src_w, uint32_t src_h,
1006                         struct drm_modeset_acquire_ctx *ctx)
1007 {
1008         struct drm_plane_state *plane_state, *new_plane_state;
1009         struct mdp5_plane_state *mdp5_pstate;
1010         struct drm_crtc_state *crtc_state = crtc->state;
1011         int ret;
1012
1013         if (!crtc_state->active || drm_atomic_crtc_needs_modeset(crtc_state))
1014                 goto slow;
1015
1016         plane_state = plane->state;
1017         mdp5_pstate = to_mdp5_plane_state(plane_state);
1018
1019         /* don't use fast path if we don't have a hwpipe allocated yet */
1020         if (!mdp5_pstate->hwpipe)
1021                 goto slow;
1022
1023         /* only allow changing of position(crtc x/y or src x/y) in fast path */
1024         if (plane_state->crtc != crtc ||
1025             plane_state->src_w != src_w ||
1026             plane_state->src_h != src_h ||
1027             plane_state->crtc_w != crtc_w ||
1028             plane_state->crtc_h != crtc_h ||
1029             !plane_state->fb ||
1030             plane_state->fb != fb)
1031                 goto slow;
1032
1033         new_plane_state = mdp5_plane_duplicate_state(plane);
1034         if (!new_plane_state)
1035                 return -ENOMEM;
1036
1037         new_plane_state->src_x = src_x;
1038         new_plane_state->src_y = src_y;
1039         new_plane_state->src_w = src_w;
1040         new_plane_state->src_h = src_h;
1041         new_plane_state->crtc_x = crtc_x;
1042         new_plane_state->crtc_y = crtc_y;
1043         new_plane_state->crtc_w = crtc_w;
1044         new_plane_state->crtc_h = crtc_h;
1045
1046         ret = mdp5_plane_atomic_check_with_state(crtc_state, new_plane_state);
1047         if (ret)
1048                 goto slow_free;
1049
1050         if (new_plane_state->visible) {
1051                 struct mdp5_ctl *ctl;
1052                 struct mdp5_pipeline *pipeline = mdp5_crtc_get_pipeline(crtc);
1053
1054                 ret = mdp5_plane_mode_set(plane, crtc, fb,
1055                                           &new_plane_state->src,
1056                                           &new_plane_state->dst);
1057                 WARN_ON(ret < 0);
1058
1059                 ctl = mdp5_crtc_get_ctl(crtc);
1060
1061                 mdp5_ctl_commit(ctl, pipeline, mdp5_plane_get_flush(plane));
1062         }
1063
1064         *to_mdp5_plane_state(plane_state) =
1065                 *to_mdp5_plane_state(new_plane_state);
1066
1067         mdp5_plane_destroy_state(plane, new_plane_state);
1068
1069         return 0;
1070 slow_free:
1071         mdp5_plane_destroy_state(plane, new_plane_state);
1072 slow:
1073         return drm_atomic_helper_update_plane(plane, crtc, fb,
1074                                               crtc_x, crtc_y, crtc_w, crtc_h,
1075                                               src_x, src_y, src_w, src_h, ctx);
1076 }
1077
1078 /*
1079  * Use this func and the one below only after the atomic state has been
1080  * successfully swapped
1081  */
1082 enum mdp5_pipe mdp5_plane_pipe(struct drm_plane *plane)
1083 {
1084         struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state);
1085
1086         if (WARN_ON(!pstate->hwpipe))
1087                 return SSPP_NONE;
1088
1089         return pstate->hwpipe->pipe;
1090 }
1091
1092 enum mdp5_pipe mdp5_plane_right_pipe(struct drm_plane *plane)
1093 {
1094         struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state);
1095
1096         if (!pstate->r_hwpipe)
1097                 return SSPP_NONE;
1098
1099         return pstate->r_hwpipe->pipe;
1100 }
1101
1102 uint32_t mdp5_plane_get_flush(struct drm_plane *plane)
1103 {
1104         struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state);
1105         u32 mask;
1106
1107         if (WARN_ON(!pstate->hwpipe))
1108                 return 0;
1109
1110         mask = pstate->hwpipe->flush_mask;
1111
1112         if (pstate->r_hwpipe)
1113                 mask |= pstate->r_hwpipe->flush_mask;
1114
1115         return mask;
1116 }
1117
1118 /* initialize plane */
1119 struct drm_plane *mdp5_plane_init(struct drm_device *dev,
1120                                   enum drm_plane_type type)
1121 {
1122         struct drm_plane *plane = NULL;
1123         struct mdp5_plane *mdp5_plane;
1124         int ret;
1125
1126         mdp5_plane = kzalloc(sizeof(*mdp5_plane), GFP_KERNEL);
1127         if (!mdp5_plane) {
1128                 ret = -ENOMEM;
1129                 goto fail;
1130         }
1131
1132         plane = &mdp5_plane->base;
1133
1134         mdp5_plane->nformats = mdp_get_formats(mdp5_plane->formats,
1135                 ARRAY_SIZE(mdp5_plane->formats), false);
1136
1137         spin_lock_init(&mdp5_plane->pipe_lock);
1138
1139         if (type == DRM_PLANE_TYPE_CURSOR)
1140                 ret = drm_universal_plane_init(dev, plane, 0xff,
1141                                 &mdp5_cursor_plane_funcs,
1142                                 mdp5_plane->formats, mdp5_plane->nformats,
1143                                 type, NULL);
1144         else
1145                 ret = drm_universal_plane_init(dev, plane, 0xff,
1146                                 &mdp5_plane_funcs,
1147                                 mdp5_plane->formats, mdp5_plane->nformats,
1148                                 type, NULL);
1149         if (ret)
1150                 goto fail;
1151
1152         drm_plane_helper_add(plane, &mdp5_plane_helper_funcs);
1153
1154         mdp5_plane_install_properties(plane, &plane->base);
1155
1156         return plane;
1157
1158 fail:
1159         if (plane)
1160                 mdp5_plane_destroy(plane);
1161
1162         return ERR_PTR(ret);
1163 }