2 * Copyright (C) 2014-2015 The Linux Foundation. All rights reserved.
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published by
8 * the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
19 #include <drm/drm_print.h>
23 struct drm_plane base;
28 #define to_mdp5_plane(x) container_of(x, struct mdp5_plane, base)
30 static int mdp5_plane_mode_set(struct drm_plane *plane,
31 struct drm_crtc *crtc, struct drm_framebuffer *fb,
32 int crtc_x, int crtc_y,
33 unsigned int crtc_w, unsigned int crtc_h,
34 uint32_t src_x, uint32_t src_y,
35 uint32_t src_w, uint32_t src_h);
37 static void set_scanout_locked(struct drm_plane *plane,
38 struct drm_framebuffer *fb);
40 static struct mdp5_kms *get_kms(struct drm_plane *plane)
42 struct msm_drm_private *priv = plane->dev->dev_private;
43 return to_mdp5_kms(to_mdp_kms(priv->kms));
46 static bool plane_enabled(struct drm_plane_state *state)
48 return state->fb && state->crtc;
51 static void mdp5_plane_destroy(struct drm_plane *plane)
53 struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
55 drm_plane_helper_disable(plane);
56 drm_plane_cleanup(plane);
61 static void mdp5_plane_install_rotation_property(struct drm_device *dev,
62 struct drm_plane *plane)
64 drm_plane_create_rotation_property(plane,
72 /* helper to install properties which are common to planes and crtcs */
73 static void mdp5_plane_install_properties(struct drm_plane *plane,
74 struct drm_mode_object *obj)
76 struct drm_device *dev = plane->dev;
77 struct msm_drm_private *dev_priv = dev->dev_private;
78 struct drm_property *prop;
80 #define INSTALL_PROPERTY(name, NAME, init_val, fnc, ...) do { \
81 prop = dev_priv->plane_property[PLANE_PROP_##NAME]; \
83 prop = drm_property_##fnc(dev, 0, #name, \
87 "Create property %s failed\n", \
91 dev_priv->plane_property[PLANE_PROP_##NAME] = prop; \
93 drm_object_attach_property(&plane->base, prop, init_val); \
96 #define INSTALL_RANGE_PROPERTY(name, NAME, min, max, init_val) \
97 INSTALL_PROPERTY(name, NAME, init_val, \
98 create_range, min, max)
100 #define INSTALL_ENUM_PROPERTY(name, NAME, init_val) \
101 INSTALL_PROPERTY(name, NAME, init_val, \
102 create_enum, name##_prop_enum_list, \
103 ARRAY_SIZE(name##_prop_enum_list))
105 INSTALL_RANGE_PROPERTY(zpos, ZPOS, 1, 255, 1);
107 mdp5_plane_install_rotation_property(dev, plane);
109 #undef INSTALL_RANGE_PROPERTY
110 #undef INSTALL_ENUM_PROPERTY
111 #undef INSTALL_PROPERTY
114 static int mdp5_plane_atomic_set_property(struct drm_plane *plane,
115 struct drm_plane_state *state, struct drm_property *property,
118 struct drm_device *dev = plane->dev;
119 struct mdp5_plane_state *pstate;
120 struct msm_drm_private *dev_priv = dev->dev_private;
123 pstate = to_mdp5_plane_state(state);
125 #define SET_PROPERTY(name, NAME, type) do { \
126 if (dev_priv->plane_property[PLANE_PROP_##NAME] == property) { \
127 pstate->name = (type)val; \
128 DBG("Set property %s %d", #name, (type)val); \
133 SET_PROPERTY(zpos, ZPOS, uint8_t);
135 dev_err(dev->dev, "Invalid property\n");
142 static int mdp5_plane_atomic_get_property(struct drm_plane *plane,
143 const struct drm_plane_state *state,
144 struct drm_property *property, uint64_t *val)
146 struct drm_device *dev = plane->dev;
147 struct mdp5_plane_state *pstate;
148 struct msm_drm_private *dev_priv = dev->dev_private;
151 pstate = to_mdp5_plane_state(state);
153 #define GET_PROPERTY(name, NAME, type) do { \
154 if (dev_priv->plane_property[PLANE_PROP_##NAME] == property) { \
155 *val = pstate->name; \
156 DBG("Get property %s %lld", #name, *val); \
161 GET_PROPERTY(zpos, ZPOS, uint8_t);
163 dev_err(dev->dev, "Invalid property\n");
171 mdp5_plane_atomic_print_state(struct drm_printer *p,
172 const struct drm_plane_state *state)
174 struct mdp5_plane_state *pstate = to_mdp5_plane_state(state);
176 drm_printf(p, "\thwpipe=%s\n", pstate->hwpipe ?
177 pstate->hwpipe->name : "(null)");
178 drm_printf(p, "\tpremultiplied=%u\n", pstate->premultiplied);
179 drm_printf(p, "\tzpos=%u\n", pstate->zpos);
180 drm_printf(p, "\talpha=%u\n", pstate->alpha);
181 drm_printf(p, "\tstage=%s\n", stage2name(pstate->stage));
182 drm_printf(p, "\tpending=%u\n", pstate->pending);
185 static void mdp5_plane_reset(struct drm_plane *plane)
187 struct mdp5_plane_state *mdp5_state;
189 if (plane->state && plane->state->fb)
190 drm_framebuffer_unreference(plane->state->fb);
192 kfree(to_mdp5_plane_state(plane->state));
193 mdp5_state = kzalloc(sizeof(*mdp5_state), GFP_KERNEL);
195 /* assign default blend parameters */
196 mdp5_state->alpha = 255;
197 mdp5_state->premultiplied = 0;
199 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
200 mdp5_state->zpos = STAGE_BASE;
202 mdp5_state->zpos = STAGE0 + drm_plane_index(plane);
204 mdp5_state->base.plane = plane;
206 plane->state = &mdp5_state->base;
209 static struct drm_plane_state *
210 mdp5_plane_duplicate_state(struct drm_plane *plane)
212 struct mdp5_plane_state *mdp5_state;
214 if (WARN_ON(!plane->state))
217 mdp5_state = kmemdup(to_mdp5_plane_state(plane->state),
218 sizeof(*mdp5_state), GFP_KERNEL);
220 if (mdp5_state && mdp5_state->base.fb)
221 drm_framebuffer_reference(mdp5_state->base.fb);
223 mdp5_state->pending = false;
225 return &mdp5_state->base;
228 static void mdp5_plane_destroy_state(struct drm_plane *plane,
229 struct drm_plane_state *state)
231 struct mdp5_plane_state *pstate = to_mdp5_plane_state(state);
234 drm_framebuffer_unreference(state->fb);
239 static const struct drm_plane_funcs mdp5_plane_funcs = {
240 .update_plane = drm_atomic_helper_update_plane,
241 .disable_plane = drm_atomic_helper_disable_plane,
242 .destroy = mdp5_plane_destroy,
243 .set_property = drm_atomic_helper_plane_set_property,
244 .atomic_set_property = mdp5_plane_atomic_set_property,
245 .atomic_get_property = mdp5_plane_atomic_get_property,
246 .reset = mdp5_plane_reset,
247 .atomic_duplicate_state = mdp5_plane_duplicate_state,
248 .atomic_destroy_state = mdp5_plane_destroy_state,
249 .atomic_print_state = mdp5_plane_atomic_print_state,
252 static int mdp5_plane_prepare_fb(struct drm_plane *plane,
253 struct drm_plane_state *new_state)
255 struct mdp5_kms *mdp5_kms = get_kms(plane);
256 struct drm_framebuffer *fb = new_state->fb;
261 DBG("%s: prepare: FB[%u]", plane->name, fb->base.id);
262 return msm_framebuffer_prepare(fb, mdp5_kms->id);
265 static void mdp5_plane_cleanup_fb(struct drm_plane *plane,
266 struct drm_plane_state *old_state)
268 struct mdp5_kms *mdp5_kms = get_kms(plane);
269 struct drm_framebuffer *fb = old_state->fb;
274 DBG("%s: cleanup: FB[%u]", plane->name, fb->base.id);
275 msm_framebuffer_cleanup(fb, mdp5_kms->id);
278 static int mdp5_plane_atomic_check(struct drm_plane *plane,
279 struct drm_plane_state *state)
281 struct mdp5_plane_state *mdp5_state = to_mdp5_plane_state(state);
282 struct drm_plane_state *old_state = plane->state;
283 struct mdp5_cfg *config = mdp5_cfg_get_config(get_kms(plane)->cfg);
284 bool new_hwpipe = false;
285 uint32_t max_width, max_height;
288 DBG("%s: check (%d -> %d)", plane->name,
289 plane_enabled(old_state), plane_enabled(state));
291 /* We don't allow faster-than-vblank updates.. if we did add this
292 * some day, we would need to disallow in cases where hwpipe
295 if (WARN_ON(to_mdp5_plane_state(old_state)->pending))
298 max_width = config->hw->lm.max_width << 16;
299 max_height = config->hw->lm.max_height << 16;
301 /* Make sure source dimensions are within bounds. */
302 if ((state->src_w > max_width) || (state->src_h > max_height)) {
303 struct drm_rect src = drm_plane_state_src(state);
304 DBG("Invalid source size "DRM_RECT_FP_FMT,
305 DRM_RECT_FP_ARG(&src));
309 if (plane_enabled(state)) {
310 unsigned int rotation;
311 const struct mdp_format *format;
312 struct mdp5_kms *mdp5_kms = get_kms(plane);
315 format = to_mdp_format(msm_framebuffer_format(state->fb));
316 if (MDP_FORMAT_IS_YUV(format))
317 caps |= MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC;
319 if (((state->src_w >> 16) != state->crtc_w) ||
320 ((state->src_h >> 16) != state->crtc_h))
321 caps |= MDP_PIPE_CAP_SCALE;
323 rotation = drm_rotation_simplify(state->rotation,
328 if (rotation & DRM_REFLECT_X)
329 caps |= MDP_PIPE_CAP_HFLIP;
331 if (rotation & DRM_REFLECT_Y)
332 caps |= MDP_PIPE_CAP_VFLIP;
334 /* (re)allocate hw pipe if we don't have one or caps-mismatch: */
335 if (!mdp5_state->hwpipe || (caps & ~mdp5_state->hwpipe->caps))
339 const struct mdp_format *format =
340 to_mdp_format(msm_framebuffer_format(state->fb));
342 blkcfg = mdp5_smp_calculate(mdp5_kms->smp, format,
343 state->src_w >> 16, false);
345 if (mdp5_state->hwpipe && (mdp5_state->hwpipe->blkcfg != blkcfg))
349 /* (re)assign hwpipe if needed, otherwise keep old one: */
351 /* TODO maybe we want to re-assign hwpipe sometimes
352 * in cases when we no-longer need some caps to make
353 * it available for other planes?
355 struct mdp5_hw_pipe *old_hwpipe = mdp5_state->hwpipe;
356 mdp5_state->hwpipe = mdp5_pipe_assign(state->state,
357 plane, caps, blkcfg);
358 if (IS_ERR(mdp5_state->hwpipe)) {
359 DBG("%s: failed to assign hwpipe!", plane->name);
360 return PTR_ERR(mdp5_state->hwpipe);
362 mdp5_pipe_release(state->state, old_hwpipe);
369 static void mdp5_plane_atomic_update(struct drm_plane *plane,
370 struct drm_plane_state *old_state)
372 struct drm_plane_state *state = plane->state;
373 struct mdp5_plane_state *mdp5_state = to_mdp5_plane_state(state);
375 DBG("%s: update", plane->name);
377 mdp5_state->pending = true;
379 if (plane_enabled(state)) {
382 ret = mdp5_plane_mode_set(plane,
383 state->crtc, state->fb,
384 state->crtc_x, state->crtc_y,
385 state->crtc_w, state->crtc_h,
386 state->src_x, state->src_y,
387 state->src_w, state->src_h);
388 /* atomic_check should have ensured that this doesn't fail */
393 static const struct drm_plane_helper_funcs mdp5_plane_helper_funcs = {
394 .prepare_fb = mdp5_plane_prepare_fb,
395 .cleanup_fb = mdp5_plane_cleanup_fb,
396 .atomic_check = mdp5_plane_atomic_check,
397 .atomic_update = mdp5_plane_atomic_update,
400 static void set_scanout_locked(struct drm_plane *plane,
401 struct drm_framebuffer *fb)
403 struct mdp5_kms *mdp5_kms = get_kms(plane);
404 struct mdp5_hw_pipe *hwpipe = to_mdp5_plane_state(plane->state)->hwpipe;
405 enum mdp5_pipe pipe = hwpipe->pipe;
407 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_A(pipe),
408 MDP5_PIPE_SRC_STRIDE_A_P0(fb->pitches[0]) |
409 MDP5_PIPE_SRC_STRIDE_A_P1(fb->pitches[1]));
411 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_B(pipe),
412 MDP5_PIPE_SRC_STRIDE_B_P2(fb->pitches[2]) |
413 MDP5_PIPE_SRC_STRIDE_B_P3(fb->pitches[3]));
415 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC0_ADDR(pipe),
416 msm_framebuffer_iova(fb, mdp5_kms->id, 0));
417 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC1_ADDR(pipe),
418 msm_framebuffer_iova(fb, mdp5_kms->id, 1));
419 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC2_ADDR(pipe),
420 msm_framebuffer_iova(fb, mdp5_kms->id, 2));
421 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC3_ADDR(pipe),
422 msm_framebuffer_iova(fb, mdp5_kms->id, 3));
427 /* Note: mdp5_plane->pipe_lock must be locked */
428 static void csc_disable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe)
430 uint32_t value = mdp5_read(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe)) &
431 ~MDP5_PIPE_OP_MODE_CSC_1_EN;
433 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), value);
436 /* Note: mdp5_plane->pipe_lock must be locked */
437 static void csc_enable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe,
440 uint32_t i, mode = 0; /* RGB, no CSC */
446 if ((csc->type == CSC_YUV2RGB) || (CSC_YUV2YUV == csc->type))
447 mode |= MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT(DATA_FORMAT_YUV);
448 if ((csc->type == CSC_RGB2YUV) || (CSC_YUV2YUV == csc->type))
449 mode |= MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT(DATA_FORMAT_YUV);
450 mode |= MDP5_PIPE_OP_MODE_CSC_1_EN;
451 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), mode);
453 matrix = csc->matrix;
454 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(pipe),
455 MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11(matrix[0]) |
456 MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12(matrix[1]));
457 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(pipe),
458 MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13(matrix[2]) |
459 MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21(matrix[3]));
460 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(pipe),
461 MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22(matrix[4]) |
462 MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23(matrix[5]));
463 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(pipe),
464 MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31(matrix[6]) |
465 MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32(matrix[7]));
466 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(pipe),
467 MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33(matrix[8]));
469 for (i = 0; i < ARRAY_SIZE(csc->pre_bias); i++) {
470 uint32_t *pre_clamp = csc->pre_clamp;
471 uint32_t *post_clamp = csc->post_clamp;
473 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_CLAMP(pipe, i),
474 MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH(pre_clamp[2*i+1]) |
475 MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW(pre_clamp[2*i]));
477 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_CLAMP(pipe, i),
478 MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH(post_clamp[2*i+1]) |
479 MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW(post_clamp[2*i]));
481 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_BIAS(pipe, i),
482 MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE(csc->pre_bias[i]));
484 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_BIAS(pipe, i),
485 MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE(csc->post_bias[i]));
489 #define PHASE_STEP_SHIFT 21
490 #define DOWN_SCALE_RATIO_MAX 32 /* 2^(26-21) */
492 static int calc_phase_step(uint32_t src, uint32_t dst, uint32_t *out_phase)
496 if (src == 0 || dst == 0)
500 * PHASE_STEP_X/Y is coded on 26 bits (25:0),
501 * where 2^21 represents the unity "1" in fixed-point hardware design.
502 * This leaves 5 bits for the integer part (downscale case):
503 * -> maximum downscale ratio = 0b1_1111 = 31
505 if (src > (dst * DOWN_SCALE_RATIO_MAX))
508 unit = 1 << PHASE_STEP_SHIFT;
509 *out_phase = mult_frac(unit, src, dst);
514 static int calc_scalex_steps(struct drm_plane *plane,
515 uint32_t pixel_format, uint32_t src, uint32_t dest,
516 uint32_t phasex_steps[COMP_MAX])
518 struct mdp5_kms *mdp5_kms = get_kms(plane);
519 struct device *dev = mdp5_kms->dev->dev;
520 uint32_t phasex_step;
524 ret = calc_phase_step(src, dest, &phasex_step);
526 dev_err(dev, "X scaling (%d->%d) failed: %d\n", src, dest, ret);
530 hsub = drm_format_horz_chroma_subsampling(pixel_format);
532 phasex_steps[COMP_0] = phasex_step;
533 phasex_steps[COMP_3] = phasex_step;
534 phasex_steps[COMP_1_2] = phasex_step / hsub;
539 static int calc_scaley_steps(struct drm_plane *plane,
540 uint32_t pixel_format, uint32_t src, uint32_t dest,
541 uint32_t phasey_steps[COMP_MAX])
543 struct mdp5_kms *mdp5_kms = get_kms(plane);
544 struct device *dev = mdp5_kms->dev->dev;
545 uint32_t phasey_step;
549 ret = calc_phase_step(src, dest, &phasey_step);
551 dev_err(dev, "Y scaling (%d->%d) failed: %d\n", src, dest, ret);
555 vsub = drm_format_vert_chroma_subsampling(pixel_format);
557 phasey_steps[COMP_0] = phasey_step;
558 phasey_steps[COMP_3] = phasey_step;
559 phasey_steps[COMP_1_2] = phasey_step / vsub;
564 static uint32_t get_scale_config(const struct mdp_format *format,
565 uint32_t src, uint32_t dst, bool horz)
567 bool scaling = format->is_yuv ? true : (src != dst);
568 uint32_t sub, pix_fmt = format->base.pixel_format;
569 uint32_t ya_filter, uv_filter;
570 bool yuv = format->is_yuv;
576 sub = horz ? drm_format_horz_chroma_subsampling(pix_fmt) :
577 drm_format_vert_chroma_subsampling(pix_fmt);
578 uv_filter = ((src / sub) <= dst) ?
579 SCALE_FILTER_BIL : SCALE_FILTER_PCMN;
581 ya_filter = (src <= dst) ? SCALE_FILTER_BIL : SCALE_FILTER_PCMN;
584 return MDP5_PIPE_SCALE_CONFIG_SCALEX_EN |
585 MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(ya_filter) |
586 MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(ya_filter) |
587 COND(yuv, MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2(uv_filter));
589 return MDP5_PIPE_SCALE_CONFIG_SCALEY_EN |
590 MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(ya_filter) |
591 MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3(ya_filter) |
592 COND(yuv, MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(uv_filter));
595 static void calc_pixel_ext(const struct mdp_format *format,
596 uint32_t src, uint32_t dst, uint32_t phase_step[2],
597 int pix_ext_edge1[COMP_MAX], int pix_ext_edge2[COMP_MAX],
600 bool scaling = format->is_yuv ? true : (src != dst);
605 * We assume here that:
606 * 1. PCMN filter is used for downscale
607 * 2. bilinear filter is used for upscale
608 * 3. we are in a single pipe configuration
611 for (i = 0; i < COMP_MAX; i++) {
612 pix_ext_edge1[i] = 0;
613 pix_ext_edge2[i] = scaling ? 1 : 0;
617 static void mdp5_write_pixel_ext(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe,
618 const struct mdp_format *format,
619 uint32_t src_w, int pe_left[COMP_MAX], int pe_right[COMP_MAX],
620 uint32_t src_h, int pe_top[COMP_MAX], int pe_bottom[COMP_MAX])
622 uint32_t pix_fmt = format->base.pixel_format;
623 uint32_t lr, tb, req;
626 for (i = 0; i < COMP_MAX; i++) {
627 uint32_t roi_w = src_w;
628 uint32_t roi_h = src_h;
630 if (format->is_yuv && i == COMP_1_2) {
631 roi_w /= drm_format_horz_chroma_subsampling(pix_fmt);
632 roi_h /= drm_format_vert_chroma_subsampling(pix_fmt);
635 lr = (pe_left[i] >= 0) ?
636 MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT(pe_left[i]) :
637 MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF(pe_left[i]);
639 lr |= (pe_right[i] >= 0) ?
640 MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT(pe_right[i]) :
641 MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF(pe_right[i]);
643 tb = (pe_top[i] >= 0) ?
644 MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT(pe_top[i]) :
645 MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF(pe_top[i]);
647 tb |= (pe_bottom[i] >= 0) ?
648 MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT(pe_bottom[i]) :
649 MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF(pe_bottom[i]);
651 req = MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT(roi_w +
652 pe_left[i] + pe_right[i]);
654 req |= MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM(roi_h +
655 pe_top[i] + pe_bottom[i]);
657 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_LR(pipe, i), lr);
658 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_TB(pipe, i), tb);
659 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(pipe, i), req);
661 DBG("comp-%d (L/R): rpt=%d/%d, ovf=%d/%d, req=%d", i,
662 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT),
663 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT),
664 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF),
665 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF),
666 FIELD(req, MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT));
668 DBG("comp-%d (T/B): rpt=%d/%d, ovf=%d/%d, req=%d", i,
669 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT),
670 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT),
671 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF),
672 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF),
673 FIELD(req, MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM));
678 static int mdp5_plane_mode_set(struct drm_plane *plane,
679 struct drm_crtc *crtc, struct drm_framebuffer *fb,
680 int crtc_x, int crtc_y,
681 unsigned int crtc_w, unsigned int crtc_h,
682 uint32_t src_x, uint32_t src_y,
683 uint32_t src_w, uint32_t src_h)
685 struct drm_plane_state *pstate = plane->state;
686 struct mdp5_hw_pipe *hwpipe = to_mdp5_plane_state(pstate)->hwpipe;
687 struct mdp5_kms *mdp5_kms = get_kms(plane);
688 enum mdp5_pipe pipe = hwpipe->pipe;
689 const struct mdp_format *format;
690 uint32_t nplanes, config = 0;
691 uint32_t phasex_step[COMP_MAX] = {0,}, phasey_step[COMP_MAX] = {0,};
692 bool pe = hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT;
693 int pe_left[COMP_MAX], pe_right[COMP_MAX];
694 int pe_top[COMP_MAX], pe_bottom[COMP_MAX];
695 uint32_t hdecm = 0, vdecm = 0;
697 unsigned int rotation;
702 nplanes = drm_format_num_planes(fb->pixel_format);
704 /* bad formats should already be rejected: */
705 if (WARN_ON(nplanes > pipe2nclients(pipe)))
708 format = to_mdp_format(msm_framebuffer_format(fb));
709 pix_format = format->base.pixel_format;
711 /* src values are in Q16 fixed point, convert to integer: */
717 DBG("%s: FB[%u] %u,%u,%u,%u -> CRTC[%u] %d,%d,%u,%u", plane->name,
718 fb->base.id, src_x, src_y, src_w, src_h,
719 crtc->base.id, crtc_x, crtc_y, crtc_w, crtc_h);
721 ret = calc_scalex_steps(plane, pix_format, src_w, crtc_w, phasex_step);
725 ret = calc_scaley_steps(plane, pix_format, src_h, crtc_h, phasey_step);
729 if (hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT) {
730 calc_pixel_ext(format, src_w, crtc_w, phasex_step,
731 pe_left, pe_right, true);
732 calc_pixel_ext(format, src_h, crtc_h, phasey_step,
733 pe_top, pe_bottom, false);
736 /* TODO calc hdecm, vdecm */
738 /* SCALE is used to both scale and up-sample chroma components */
739 config |= get_scale_config(format, src_w, crtc_w, true);
740 config |= get_scale_config(format, src_h, crtc_h, false);
741 DBG("scale config = %x", config);
743 rotation = drm_rotation_simplify(pstate->rotation,
747 hflip = !!(rotation & DRM_REFLECT_X);
748 vflip = !!(rotation & DRM_REFLECT_Y);
750 spin_lock_irqsave(&hwpipe->pipe_lock, flags);
752 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_IMG_SIZE(pipe),
753 MDP5_PIPE_SRC_IMG_SIZE_WIDTH(min(fb->width, src_w)) |
754 MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(min(fb->height, src_h)));
756 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_SIZE(pipe),
757 MDP5_PIPE_SRC_SIZE_WIDTH(src_w) |
758 MDP5_PIPE_SRC_SIZE_HEIGHT(src_h));
760 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_XY(pipe),
761 MDP5_PIPE_SRC_XY_X(src_x) |
762 MDP5_PIPE_SRC_XY_Y(src_y));
764 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_SIZE(pipe),
765 MDP5_PIPE_OUT_SIZE_WIDTH(crtc_w) |
766 MDP5_PIPE_OUT_SIZE_HEIGHT(crtc_h));
768 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_XY(pipe),
769 MDP5_PIPE_OUT_XY_X(crtc_x) |
770 MDP5_PIPE_OUT_XY_Y(crtc_y));
772 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_FORMAT(pipe),
773 MDP5_PIPE_SRC_FORMAT_A_BPC(format->bpc_a) |
774 MDP5_PIPE_SRC_FORMAT_R_BPC(format->bpc_r) |
775 MDP5_PIPE_SRC_FORMAT_G_BPC(format->bpc_g) |
776 MDP5_PIPE_SRC_FORMAT_B_BPC(format->bpc_b) |
777 COND(format->alpha_enable, MDP5_PIPE_SRC_FORMAT_ALPHA_ENABLE) |
778 MDP5_PIPE_SRC_FORMAT_CPP(format->cpp - 1) |
779 MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(format->unpack_count - 1) |
780 COND(format->unpack_tight, MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT) |
781 MDP5_PIPE_SRC_FORMAT_FETCH_TYPE(format->fetch_type) |
782 MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(format->chroma_sample));
784 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_UNPACK(pipe),
785 MDP5_PIPE_SRC_UNPACK_ELEM0(format->unpack[0]) |
786 MDP5_PIPE_SRC_UNPACK_ELEM1(format->unpack[1]) |
787 MDP5_PIPE_SRC_UNPACK_ELEM2(format->unpack[2]) |
788 MDP5_PIPE_SRC_UNPACK_ELEM3(format->unpack[3]));
790 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_OP_MODE(pipe),
791 (hflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_LR : 0) |
792 (vflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_UD : 0) |
793 COND(pe, MDP5_PIPE_SRC_OP_MODE_SW_PIX_EXT_OVERRIDE) |
794 MDP5_PIPE_SRC_OP_MODE_BWC(BWC_LOSSLESS));
796 /* not using secure mode: */
797 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(pipe), 0);
799 if (hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT)
800 mdp5_write_pixel_ext(mdp5_kms, pipe, format,
801 src_w, pe_left, pe_right,
802 src_h, pe_top, pe_bottom);
804 if (hwpipe->caps & MDP_PIPE_CAP_SCALE) {
805 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_X(pipe),
806 phasex_step[COMP_0]);
807 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(pipe),
808 phasey_step[COMP_0]);
809 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(pipe),
810 phasex_step[COMP_1_2]);
811 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(pipe),
812 phasey_step[COMP_1_2]);
813 mdp5_write(mdp5_kms, REG_MDP5_PIPE_DECIMATION(pipe),
814 MDP5_PIPE_DECIMATION_VERT(vdecm) |
815 MDP5_PIPE_DECIMATION_HORZ(hdecm));
816 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CONFIG(pipe), config);
819 if (hwpipe->caps & MDP_PIPE_CAP_CSC) {
820 if (MDP_FORMAT_IS_YUV(format))
821 csc_enable(mdp5_kms, pipe,
822 mdp_get_default_csc_cfg(CSC_YUV2RGB));
824 csc_disable(mdp5_kms, pipe);
827 set_scanout_locked(plane, fb);
829 spin_unlock_irqrestore(&hwpipe->pipe_lock, flags);
834 enum mdp5_pipe mdp5_plane_pipe(struct drm_plane *plane)
836 struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state);
838 if (WARN_ON(!pstate->hwpipe))
841 return pstate->hwpipe->pipe;
844 uint32_t mdp5_plane_get_flush(struct drm_plane *plane)
846 struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state);
848 if (WARN_ON(!pstate->hwpipe))
851 return pstate->hwpipe->flush_mask;
854 /* called after vsync in thread context */
855 void mdp5_plane_complete_commit(struct drm_plane *plane,
856 struct drm_plane_state *state)
858 struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state);
860 pstate->pending = false;
863 /* initialize plane */
864 struct drm_plane *mdp5_plane_init(struct drm_device *dev, bool primary)
866 struct drm_plane *plane = NULL;
867 struct mdp5_plane *mdp5_plane;
869 enum drm_plane_type type;
871 mdp5_plane = kzalloc(sizeof(*mdp5_plane), GFP_KERNEL);
877 plane = &mdp5_plane->base;
879 mdp5_plane->nformats = mdp_get_formats(mdp5_plane->formats,
880 ARRAY_SIZE(mdp5_plane->formats), false);
882 type = primary ? DRM_PLANE_TYPE_PRIMARY : DRM_PLANE_TYPE_OVERLAY;
883 ret = drm_universal_plane_init(dev, plane, 0xff, &mdp5_plane_funcs,
884 mdp5_plane->formats, mdp5_plane->nformats,
889 drm_plane_helper_add(plane, &mdp5_plane_helper_funcs);
891 mdp5_plane_install_properties(plane, &plane->base);
897 mdp5_plane_destroy(plane);