drivers/gpu/drm/msm/mdp4/mdp4_kms.c

   1 /*
   2  * Copyright (C) 2013 Red Hat
   3  * Author: Rob Clark <robdclark@gmail.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18
  19 #include "msm_drv.h"
  20 #include "mdp4_kms.h"
  21
  22 #include <mach/iommu.h>
  23
  24 static struct mdp4_platform_config *mdp4_get_config(struct platform_device *dev);
  25
  26 static int mdp4_hw_init(struct msm_kms *kms)
  27 {
  28         struct mdp4_kms *mdp4_kms = to_mdp4_kms(kms);
  29         struct drm_device *dev = mdp4_kms->dev;
  30         uint32_t version, major, minor, dmap_cfg, vg_cfg;
  31         unsigned long clk;
  32         int ret = 0;
  33
  34         pm_runtime_get_sync(dev->dev);
  35
  36         version = mdp4_read(mdp4_kms, REG_MDP4_VERSION);
  37
  38         major = FIELD(version, MDP4_VERSION_MAJOR);
  39         minor = FIELD(version, MDP4_VERSION_MINOR);
  40
  41         DBG("found MDP version v%d.%d", major, minor);
  42
  43         if (major != 4) {
  44                 dev_err(dev->dev, "unexpected MDP version: v%d.%d\n",
  45                                 major, minor);
  46                 ret = -ENXIO;
  47                 goto out;
  48         }
  49
  50         mdp4_kms->rev = minor;
  51
  52         if (mdp4_kms->dsi_pll_vdda) {
  53                 if ((mdp4_kms->rev == 2) || (mdp4_kms->rev == 4)) {
  54                         ret = regulator_set_voltage(mdp4_kms->dsi_pll_vdda,
  55                                         1200000, 1200000);
  56                         if (ret) {
  57                                 dev_err(dev->dev,
  58                                         "failed to set dsi_pll_vdda voltage: %d\n", ret);
  59                                 goto out;
  60                         }
  61                 }
  62         }
  63
  64         if (mdp4_kms->dsi_pll_vddio) {
  65                 if (mdp4_kms->rev == 2) {
  66                         ret = regulator_set_voltage(mdp4_kms->dsi_pll_vddio,
  67                                         1800000, 1800000);
  68                         if (ret) {
  69                                 dev_err(dev->dev,
  70                                         "failed to set dsi_pll_vddio voltage: %d\n", ret);
  71                                 goto out;
  72                         }
  73                 }
  74         }
  75
  76         if (mdp4_kms->rev > 1) {
  77                 mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER0, 0x0707ffff);
  78                 mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER1, 0x03073f3f);
  79         }
  80
  81         mdp4_write(mdp4_kms, REG_MDP4_PORTMAP_MODE, 0x3);
  82
  83         /* max read pending cmd config, 3 pending requests: */
  84         mdp4_write(mdp4_kms, REG_MDP4_READ_CNFG, 0x02222);
  85
  86         clk = clk_get_rate(mdp4_kms->clk);
  87
  88         if ((mdp4_kms->rev >= 1) || (clk >= 90000000)) {
  89                 dmap_cfg = 0x47;     /* 16 bytes-burst x 8 req */
  90                 vg_cfg = 0x47;       /* 16 bytes-burs x 8 req */
  91         } else {
  92                 dmap_cfg = 0x27;     /* 8 bytes-burst x 8 req */
  93                 vg_cfg = 0x43;       /* 16 bytes-burst x 4 req */
  94         }
  95
  96         DBG("fetch config: dmap=%02x, vg=%02x", dmap_cfg, vg_cfg);
  97
  98         mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_P), dmap_cfg);
  99         mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_E), dmap_cfg);
 100
 101         mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG1), vg_cfg);
 102         mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG2), vg_cfg);
 103         mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB1), vg_cfg);
 104         mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB2), vg_cfg);
 105
 106         if (mdp4_kms->rev >= 2)
 107                 mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG_UPDATE_METHOD, 1);
 108
 109         /* disable CSC matrix / YUV by default: */
 110         mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG1), 0);
 111         mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG2), 0);
 112         mdp4_write(mdp4_kms, REG_MDP4_DMA_P_OP_MODE, 0);
 113         mdp4_write(mdp4_kms, REG_MDP4_DMA_S_OP_MODE, 0);
 114         mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(1), 0);
 115         mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(2), 0);
 116
 117         if (mdp4_kms->rev > 1)
 118                 mdp4_write(mdp4_kms, REG_MDP4_RESET_STATUS, 1);
 119
 120 out:
 121         pm_runtime_put_sync(dev->dev);
 122
 123         return ret;
 124 }
 125
 126 static long mdp4_round_pixclk(struct msm_kms *kms, unsigned long rate,
 127                 struct drm_encoder *encoder)
 128 {
 129         /* if we had >1 encoder, we'd need something more clever: */
 130         return mdp4_dtv_round_pixclk(encoder, rate);
 131 }
 132
 133 static void mdp4_preclose(struct msm_kms *kms, struct drm_file *file)
 134 {
 135         struct mdp4_kms *mdp4_kms = to_mdp4_kms(kms);
 136         struct msm_drm_private *priv = mdp4_kms->dev->dev_private;
 137         unsigned i;
 138
 139         for (i = 0; i < priv->num_crtcs; i++)
 140                 mdp4_crtc_cancel_pending_flip(priv->crtcs[i]);
 141 }
 142
 143 static void mdp4_destroy(struct msm_kms *kms)
 144 {
 145         struct mdp4_kms *mdp4_kms = to_mdp4_kms(kms);
 146         kfree(mdp4_kms);
 147 }
 148
 149 static const struct msm_kms_funcs kms_funcs = {
 150                 .hw_init         = mdp4_hw_init,
 151                 .irq_preinstall  = mdp4_irq_preinstall,
 152                 .irq_postinstall = mdp4_irq_postinstall,
 153                 .irq_uninstall   = mdp4_irq_uninstall,
 154                 .irq             = mdp4_irq,
 155                 .enable_vblank   = mdp4_enable_vblank,
 156                 .disable_vblank  = mdp4_disable_vblank,
 157                 .get_format      = mdp4_get_format,
 158                 .round_pixclk    = mdp4_round_pixclk,
 159                 .preclose        = mdp4_preclose,
 160                 .destroy         = mdp4_destroy,
 161 };
 162
 163 int mdp4_disable(struct mdp4_kms *mdp4_kms)
 164 {
 165         DBG("");
 166
 167         clk_disable_unprepare(mdp4_kms->clk);
 168         if (mdp4_kms->pclk)
 169                 clk_disable_unprepare(mdp4_kms->pclk);
 170         clk_disable_unprepare(mdp4_kms->lut_clk);
 171
 172         return 0;
 173 }
 174
 175 int mdp4_enable(struct mdp4_kms *mdp4_kms)
 176 {
 177         DBG("");
 178
 179         clk_prepare_enable(mdp4_kms->clk);
 180         if (mdp4_kms->pclk)
 181                 clk_prepare_enable(mdp4_kms->pclk);
 182         clk_prepare_enable(mdp4_kms->lut_clk);
 183
 184         return 0;
 185 }
 186
 187 static int modeset_init(struct mdp4_kms *mdp4_kms)
 188 {
 189         struct drm_device *dev = mdp4_kms->dev;
 190         struct msm_drm_private *priv = dev->dev_private;
 191         struct drm_plane *plane;
 192         struct drm_crtc *crtc;
 193         struct drm_encoder *encoder;
 194         int ret;
 195
 196         /*
 197          *  NOTE: this is a bit simplistic until we add support
 198          * for more than just RGB1->DMA_E->DTV->HDMI
 199          */
 200
 201         /* the CRTCs get constructed with a private plane: */
 202         plane = mdp4_plane_init(dev, RGB1, true);
 203         if (IS_ERR(plane)) {
 204                 dev_err(dev->dev, "failed to construct plane for RGB1\n");
 205                 ret = PTR_ERR(plane);
 206                 goto fail;
 207         }
 208
 209         crtc  = mdp4_crtc_init(dev, plane, priv->num_crtcs, 1, DMA_E);
 210         if (IS_ERR(crtc)) {
 211                 dev_err(dev->dev, "failed to construct crtc for DMA_E\n");
 212                 ret = PTR_ERR(crtc);
 213                 goto fail;
 214         }
 215         priv->crtcs[priv->num_crtcs++] = crtc;
 216
 217         encoder = mdp4_dtv_encoder_init(dev);
 218         if (IS_ERR(encoder)) {
 219                 dev_err(dev->dev, "failed to construct DTV encoder\n");
 220                 ret = PTR_ERR(encoder);
 221                 goto fail;
 222         }
 223         encoder->possible_crtcs = 0x1;     /* DTV can be hooked to DMA_E */
 224         priv->encoders[priv->num_encoders++] = encoder;
 225
 226         ret = hdmi_init(dev, encoder);
 227         if (ret) {
 228                 dev_err(dev->dev, "failed to initialize HDMI\n");
 229                 goto fail;
 230         }
 231
 232         return 0;
 233
 234 fail:
 235         return ret;
 236 }
 237
 238 static const char *iommu_ports[] = {
 239                 "mdp_port0_cb0", "mdp_port1_cb0",
 240 };
 241
 242 struct msm_kms *mdp4_kms_init(struct drm_device *dev)
 243 {
 244         struct platform_device *pdev = dev->platformdev;
 245         struct mdp4_platform_config *config = mdp4_get_config(pdev);
 246         struct mdp4_kms *mdp4_kms;
 247         struct msm_kms *kms = NULL;
 248         int ret;
 249
 250         mdp4_kms = kzalloc(sizeof(*mdp4_kms), GFP_KERNEL);
 251         if (!mdp4_kms) {
 252                 dev_err(dev->dev, "failed to allocate kms\n");
 253                 ret = -ENOMEM;
 254                 goto fail;
 255         }
 256
 257         kms = &mdp4_kms->base;
 258         kms->funcs = &kms_funcs;
 259
 260         mdp4_kms->dev = dev;
 261
 262         mdp4_kms->mmio = msm_ioremap(pdev, NULL, "MDP4");
 263         if (IS_ERR(mdp4_kms->mmio)) {
 264                 ret = PTR_ERR(mdp4_kms->mmio);
 265                 goto fail;
 266         }
 267
 268         mdp4_kms->dsi_pll_vdda = devm_regulator_get(&pdev->dev, "dsi_pll_vdda");
 269         if (IS_ERR(mdp4_kms->dsi_pll_vdda))
 270                 mdp4_kms->dsi_pll_vdda = NULL;
 271
 272         mdp4_kms->dsi_pll_vddio = devm_regulator_get(&pdev->dev, "dsi_pll_vddio");
 273         if (IS_ERR(mdp4_kms->dsi_pll_vddio))
 274                 mdp4_kms->dsi_pll_vddio = NULL;
 275
 276         mdp4_kms->vdd = devm_regulator_get(&pdev->dev, "vdd");
 277         if (IS_ERR(mdp4_kms->vdd))
 278                 mdp4_kms->vdd = NULL;
 279
 280         if (mdp4_kms->vdd) {
 281                 ret = regulator_enable(mdp4_kms->vdd);
 282                 if (ret) {
 283                         dev_err(dev->dev, "failed to enable regulator vdd: %d\n", ret);
 284                         goto fail;
 285                 }
 286         }
 287
 288         mdp4_kms->clk = devm_clk_get(&pdev->dev, "core_clk");
 289         if (IS_ERR(mdp4_kms->clk)) {
 290                 dev_err(dev->dev, "failed to get core_clk\n");
 291                 ret = PTR_ERR(mdp4_kms->clk);
 292                 goto fail;
 293         }
 294
 295         mdp4_kms->pclk = devm_clk_get(&pdev->dev, "iface_clk");
 296         if (IS_ERR(mdp4_kms->pclk))
 297                 mdp4_kms->pclk = NULL;
 298
 299         // XXX if (rev >= MDP_REV_42) { ???
 300         mdp4_kms->lut_clk = devm_clk_get(&pdev->dev, "lut_clk");
 301         if (IS_ERR(mdp4_kms->lut_clk)) {
 302                 dev_err(dev->dev, "failed to get lut_clk\n");
 303                 ret = PTR_ERR(mdp4_kms->lut_clk);
 304                 goto fail;
 305         }
 306
 307         clk_set_rate(mdp4_kms->clk, config->max_clk);
 308         clk_set_rate(mdp4_kms->lut_clk, config->max_clk);
 309
 310         if (!config->iommu) {
 311                 dev_err(dev->dev, "no iommu\n");
 312                 ret = -ENXIO;
 313                 goto fail;
 314         }
 315
 316         /* make sure things are off before attaching iommu (bootloader could
 317          * have left things on, in which case we'll start getting faults if
 318          * we don't disable):
 319          */
 320         mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 0);
 321         mdp4_write(mdp4_kms, REG_MDP4_LCDC_ENABLE, 0);
 322         mdp4_write(mdp4_kms, REG_MDP4_DSI_ENABLE, 0);
 323         mdelay(16);
 324
 325         ret = msm_iommu_attach(dev, config->iommu,
 326                         iommu_ports, ARRAY_SIZE(iommu_ports));
 327         if (ret)
 328                 goto fail;
 329
 330         mdp4_kms->id = msm_register_iommu(dev, config->iommu);
 331         if (mdp4_kms->id < 0) {
 332                 ret = mdp4_kms->id;
 333                 dev_err(dev->dev, "failed to register mdp4 iommu: %d\n", ret);
 334                 goto fail;
 335         }
 336
 337         ret = modeset_init(mdp4_kms);
 338         if (ret) {
 339                 dev_err(dev->dev, "modeset_init failed: %d\n", ret);
 340                 goto fail;
 341         }
 342
 343         return kms;
 344
 345 fail:
 346         if (kms)
 347                 mdp4_destroy(kms);
 348         return ERR_PTR(ret);
 349 }
 350
 351 static struct mdp4_platform_config *mdp4_get_config(struct platform_device *dev)
 352 {
 353         static struct mdp4_platform_config config = {};
 354 #ifdef CONFIG_OF
 355         /* TODO */
 356 #else
 357         if (cpu_is_apq8064())
 358                 config.max_clk = 266667000;
 359         else
 360                 config.max_clk = 200000000;
 361
 362         config.iommu = msm_get_iommu_domain(DISPLAY_READ_DOMAIN);
 363 #endif
 364         return &config;
 365 }