drivers/gpu/drm/msm/mdp4/mdp4_kms.c

   1 /*
   2  * Copyright (C) 2013 Red Hat
   3  * Author: Rob Clark <robdclark@gmail.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18
  19 #include "msm_drv.h"
  20 #include "mdp4_kms.h"
  21
  22 static struct mdp4_platform_config *mdp4_get_config(struct platform_device *dev);
  23
  24 static int mdp4_hw_init(struct msm_kms *kms)
  25 {
  26         struct mdp4_kms *mdp4_kms = to_mdp4_kms(kms);
  27         struct drm_device *dev = mdp4_kms->dev;
  28         uint32_t version, major, minor, dmap_cfg, vg_cfg;
  29         unsigned long clk;
  30         int ret = 0;
  31
  32         pm_runtime_get_sync(dev->dev);
  33
  34         version = mdp4_read(mdp4_kms, REG_MDP4_VERSION);
  35
  36         major = FIELD(version, MDP4_VERSION_MAJOR);
  37         minor = FIELD(version, MDP4_VERSION_MINOR);
  38
  39         DBG("found MDP version v%d.%d", major, minor);
  40
  41         if (major != 4) {
  42                 dev_err(dev->dev, "unexpected MDP version: v%d.%d\n",
  43                                 major, minor);
  44                 ret = -ENXIO;
  45                 goto out;
  46         }
  47
  48         mdp4_kms->rev = minor;
  49
  50         if (mdp4_kms->dsi_pll_vdda) {
  51                 if ((mdp4_kms->rev == 2) || (mdp4_kms->rev == 4)) {
  52                         ret = regulator_set_voltage(mdp4_kms->dsi_pll_vdda,
  53                                         1200000, 1200000);
  54                         if (ret) {
  55                                 dev_err(dev->dev,
  56                                         "failed to set dsi_pll_vdda voltage: %d\n", ret);
  57                                 goto out;
  58                         }
  59                 }
  60         }
  61
  62         if (mdp4_kms->dsi_pll_vddio) {
  63                 if (mdp4_kms->rev == 2) {
  64                         ret = regulator_set_voltage(mdp4_kms->dsi_pll_vddio,
  65                                         1800000, 1800000);
  66                         if (ret) {
  67                                 dev_err(dev->dev,
  68                                         "failed to set dsi_pll_vddio voltage: %d\n", ret);
  69                                 goto out;
  70                         }
  71                 }
  72         }
  73
  74         if (mdp4_kms->rev > 1) {
  75                 mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER0, 0x0707ffff);
  76                 mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER1, 0x03073f3f);
  77         }
  78
  79         mdp4_write(mdp4_kms, REG_MDP4_PORTMAP_MODE, 0x3);
  80
  81         /* max read pending cmd config, 3 pending requests: */
  82         mdp4_write(mdp4_kms, REG_MDP4_READ_CNFG, 0x02222);
  83
  84         clk = clk_get_rate(mdp4_kms->clk);
  85
  86         if ((mdp4_kms->rev >= 1) || (clk >= 90000000)) {
  87                 dmap_cfg = 0x47;     /* 16 bytes-burst x 8 req */
  88                 vg_cfg = 0x47;       /* 16 bytes-burs x 8 req */
  89         } else {
  90                 dmap_cfg = 0x27;     /* 8 bytes-burst x 8 req */
  91                 vg_cfg = 0x43;       /* 16 bytes-burst x 4 req */
  92         }
  93
  94         DBG("fetch config: dmap=%02x, vg=%02x", dmap_cfg, vg_cfg);
  95
  96         mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_P), dmap_cfg);
  97         mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_E), dmap_cfg);
  98
  99         mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG1), vg_cfg);
 100         mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG2), vg_cfg);
 101         mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB1), vg_cfg);
 102         mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB2), vg_cfg);
 103
 104         if (mdp4_kms->rev >= 2)
 105                 mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG_UPDATE_METHOD, 1);
 106
 107         /* disable CSC matrix / YUV by default: */
 108         mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG1), 0);
 109         mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG2), 0);
 110         mdp4_write(mdp4_kms, REG_MDP4_DMA_P_OP_MODE, 0);
 111         mdp4_write(mdp4_kms, REG_MDP4_DMA_S_OP_MODE, 0);
 112         mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(1), 0);
 113         mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(2), 0);
 114
 115         if (mdp4_kms->rev > 1)
 116                 mdp4_write(mdp4_kms, REG_MDP4_RESET_STATUS, 1);
 117
 118 out:
 119         pm_runtime_put_sync(dev->dev);
 120
 121         return ret;
 122 }
 123
 124 static long mdp4_round_pixclk(struct msm_kms *kms, unsigned long rate,
 125                 struct drm_encoder *encoder)
 126 {
 127         /* if we had >1 encoder, we'd need something more clever: */
 128         return mdp4_dtv_round_pixclk(encoder, rate);
 129 }
 130
 131 static void mdp4_preclose(struct msm_kms *kms, struct drm_file *file)
 132 {
 133         struct mdp4_kms *mdp4_kms = to_mdp4_kms(kms);
 134         struct msm_drm_private *priv = mdp4_kms->dev->dev_private;
 135         unsigned i;
 136
 137         for (i = 0; i < priv->num_crtcs; i++)
 138                 mdp4_crtc_cancel_pending_flip(priv->crtcs[i], file);
 139 }
 140
 141 static void mdp4_destroy(struct msm_kms *kms)
 142 {
 143         struct mdp4_kms *mdp4_kms = to_mdp4_kms(kms);
 144         kfree(mdp4_kms);
 145 }
 146
 147 static const struct msm_kms_funcs kms_funcs = {
 148                 .hw_init         = mdp4_hw_init,
 149                 .irq_preinstall  = mdp4_irq_preinstall,
 150                 .irq_postinstall = mdp4_irq_postinstall,
 151                 .irq_uninstall   = mdp4_irq_uninstall,
 152                 .irq             = mdp4_irq,
 153                 .enable_vblank   = mdp4_enable_vblank,
 154                 .disable_vblank  = mdp4_disable_vblank,
 155                 .get_format      = mdp4_get_format,
 156                 .round_pixclk    = mdp4_round_pixclk,
 157                 .preclose        = mdp4_preclose,
 158                 .destroy         = mdp4_destroy,
 159 };
 160
 161 int mdp4_disable(struct mdp4_kms *mdp4_kms)
 162 {
 163         DBG("");
 164
 165         clk_disable_unprepare(mdp4_kms->clk);
 166         if (mdp4_kms->pclk)
 167                 clk_disable_unprepare(mdp4_kms->pclk);
 168         clk_disable_unprepare(mdp4_kms->lut_clk);
 169
 170         return 0;
 171 }
 172
 173 int mdp4_enable(struct mdp4_kms *mdp4_kms)
 174 {
 175         DBG("");
 176
 177         clk_prepare_enable(mdp4_kms->clk);
 178         if (mdp4_kms->pclk)
 179                 clk_prepare_enable(mdp4_kms->pclk);
 180         clk_prepare_enable(mdp4_kms->lut_clk);
 181
 182         return 0;
 183 }
 184
 185 static int modeset_init(struct mdp4_kms *mdp4_kms)
 186 {
 187         struct drm_device *dev = mdp4_kms->dev;
 188         struct msm_drm_private *priv = dev->dev_private;
 189         struct drm_plane *plane;
 190         struct drm_crtc *crtc;
 191         struct drm_encoder *encoder;
 192         int ret;
 193
 194         /*
 195          *  NOTE: this is a bit simplistic until we add support
 196          * for more than just RGB1->DMA_E->DTV->HDMI
 197          */
 198
 199         /* construct non-private planes: */
 200         plane = mdp4_plane_init(dev, VG1, false);
 201         if (IS_ERR(plane)) {
 202                 dev_err(dev->dev, "failed to construct plane for VG1\n");
 203                 ret = PTR_ERR(plane);
 204                 goto fail;
 205         }
 206         priv->planes[priv->num_planes++] = plane;
 207
 208         plane = mdp4_plane_init(dev, VG2, false);
 209         if (IS_ERR(plane)) {
 210                 dev_err(dev->dev, "failed to construct plane for VG2\n");
 211                 ret = PTR_ERR(plane);
 212                 goto fail;
 213         }
 214         priv->planes[priv->num_planes++] = plane;
 215
 216         /* the CRTCs get constructed with a private plane: */
 217         plane = mdp4_plane_init(dev, RGB1, true);
 218         if (IS_ERR(plane)) {
 219                 dev_err(dev->dev, "failed to construct plane for RGB1\n");
 220                 ret = PTR_ERR(plane);
 221                 goto fail;
 222         }
 223
 224         crtc  = mdp4_crtc_init(dev, plane, priv->num_crtcs, 1, DMA_E);
 225         if (IS_ERR(crtc)) {
 226                 dev_err(dev->dev, "failed to construct crtc for DMA_E\n");
 227                 ret = PTR_ERR(crtc);
 228                 goto fail;
 229         }
 230         priv->crtcs[priv->num_crtcs++] = crtc;
 231
 232         encoder = mdp4_dtv_encoder_init(dev);
 233         if (IS_ERR(encoder)) {
 234                 dev_err(dev->dev, "failed to construct DTV encoder\n");
 235                 ret = PTR_ERR(encoder);
 236                 goto fail;
 237         }
 238         encoder->possible_crtcs = 0x1;     /* DTV can be hooked to DMA_E */
 239         priv->encoders[priv->num_encoders++] = encoder;
 240
 241         ret = hdmi_init(dev, encoder);
 242         if (ret) {
 243                 dev_err(dev->dev, "failed to initialize HDMI\n");
 244                 goto fail;
 245         }
 246
 247         return 0;
 248
 249 fail:
 250         return ret;
 251 }
 252
 253 static const char *iommu_ports[] = {
 254                 "mdp_port0_cb0", "mdp_port1_cb0",
 255 };
 256
 257 struct msm_kms *mdp4_kms_init(struct drm_device *dev)
 258 {
 259         struct platform_device *pdev = dev->platformdev;
 260         struct mdp4_platform_config *config = mdp4_get_config(pdev);
 261         struct mdp4_kms *mdp4_kms;
 262         struct msm_kms *kms = NULL;
 263         int ret;
 264
 265         mdp4_kms = kzalloc(sizeof(*mdp4_kms), GFP_KERNEL);
 266         if (!mdp4_kms) {
 267                 dev_err(dev->dev, "failed to allocate kms\n");
 268                 ret = -ENOMEM;
 269                 goto fail;
 270         }
 271
 272         kms = &mdp4_kms->base;
 273         kms->funcs = &kms_funcs;
 274
 275         mdp4_kms->dev = dev;
 276
 277         mdp4_kms->mmio = msm_ioremap(pdev, NULL, "MDP4");
 278         if (IS_ERR(mdp4_kms->mmio)) {
 279                 ret = PTR_ERR(mdp4_kms->mmio);
 280                 goto fail;
 281         }
 282
 283         mdp4_kms->dsi_pll_vdda = devm_regulator_get(&pdev->dev, "dsi_pll_vdda");
 284         if (IS_ERR(mdp4_kms->dsi_pll_vdda))
 285                 mdp4_kms->dsi_pll_vdda = NULL;
 286
 287         mdp4_kms->dsi_pll_vddio = devm_regulator_get(&pdev->dev, "dsi_pll_vddio");
 288         if (IS_ERR(mdp4_kms->dsi_pll_vddio))
 289                 mdp4_kms->dsi_pll_vddio = NULL;
 290
 291         mdp4_kms->vdd = devm_regulator_get(&pdev->dev, "vdd");
 292         if (IS_ERR(mdp4_kms->vdd))
 293                 mdp4_kms->vdd = NULL;
 294
 295         if (mdp4_kms->vdd) {
 296                 ret = regulator_enable(mdp4_kms->vdd);
 297                 if (ret) {
 298                         dev_err(dev->dev, "failed to enable regulator vdd: %d\n", ret);
 299                         goto fail;
 300                 }
 301         }
 302
 303         mdp4_kms->clk = devm_clk_get(&pdev->dev, "core_clk");
 304         if (IS_ERR(mdp4_kms->clk)) {
 305                 dev_err(dev->dev, "failed to get core_clk\n");
 306                 ret = PTR_ERR(mdp4_kms->clk);
 307                 goto fail;
 308         }
 309
 310         mdp4_kms->pclk = devm_clk_get(&pdev->dev, "iface_clk");
 311         if (IS_ERR(mdp4_kms->pclk))
 312                 mdp4_kms->pclk = NULL;
 313
 314         // XXX if (rev >= MDP_REV_42) { ???
 315         mdp4_kms->lut_clk = devm_clk_get(&pdev->dev, "lut_clk");
 316         if (IS_ERR(mdp4_kms->lut_clk)) {
 317                 dev_err(dev->dev, "failed to get lut_clk\n");
 318                 ret = PTR_ERR(mdp4_kms->lut_clk);
 319                 goto fail;
 320         }
 321
 322         clk_set_rate(mdp4_kms->clk, config->max_clk);
 323         clk_set_rate(mdp4_kms->lut_clk, config->max_clk);
 324
 325         if (!config->iommu) {
 326                 dev_err(dev->dev, "no iommu\n");
 327                 ret = -ENXIO;
 328                 goto fail;
 329         }
 330
 331         /* make sure things are off before attaching iommu (bootloader could
 332          * have left things on, in which case we'll start getting faults if
 333          * we don't disable):
 334          */
 335         mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 0);
 336         mdp4_write(mdp4_kms, REG_MDP4_LCDC_ENABLE, 0);
 337         mdp4_write(mdp4_kms, REG_MDP4_DSI_ENABLE, 0);
 338         mdelay(16);
 339
 340         ret = msm_iommu_attach(dev, config->iommu,
 341                         iommu_ports, ARRAY_SIZE(iommu_ports));
 342         if (ret)
 343                 goto fail;
 344
 345         mdp4_kms->id = msm_register_iommu(dev, config->iommu);
 346         if (mdp4_kms->id < 0) {
 347                 ret = mdp4_kms->id;
 348                 dev_err(dev->dev, "failed to register mdp4 iommu: %d\n", ret);
 349                 goto fail;
 350         }
 351
 352         ret = modeset_init(mdp4_kms);
 353         if (ret) {
 354                 dev_err(dev->dev, "modeset_init failed: %d\n", ret);
 355                 goto fail;
 356         }
 357
 358         return kms;
 359
 360 fail:
 361         if (kms)
 362                 mdp4_destroy(kms);
 363         return ERR_PTR(ret);
 364 }
 365
 366 static struct mdp4_platform_config *mdp4_get_config(struct platform_device *dev)
 367 {
 368         static struct mdp4_platform_config config = {};
 369 #ifdef CONFIG_OF
 370         /* TODO */
 371 #else
 372         if (cpu_is_apq8064())
 373                 config.max_clk = 266667000;
 374         else
 375                 config.max_clk = 200000000;
 376
 377         config.iommu = msm_get_iommu_domain(DISPLAY_READ_DOMAIN);
 378 #endif
 379         return &config;
 380 }