drivers/gpu/drm/nouveau/core/engine/disp/nv50.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <core/object.h>
  26 #include <core/parent.h>
  27 #include <core/handle.h>
  28 #include <core/class.h>
  29
  30 #include <subdev/bios.h>
  31 #include <subdev/bios/dcb.h>
  32 #include <subdev/bios/disp.h>
  33 #include <subdev/bios/init.h>
  34 #include <subdev/bios/pll.h>
  35 #include <subdev/devinit.h>
  36 #include <subdev/timer.h>
  37 #include <subdev/fb.h>
  38
  39 #include "nv50.h"
  40
  41 /*******************************************************************************
  42  * EVO channel base class
  43  ******************************************************************************/
  44
  45 int
  46 nv50_disp_chan_create_(struct nouveau_object *parent,
  47                        struct nouveau_object *engine,
  48                        struct nouveau_oclass *oclass, int chid,
  49                        int length, void **pobject)
  50 {
  51         struct nv50_disp_base *base = (void *)parent;
  52         struct nv50_disp_chan *chan;
  53         int ret;
  54
  55         if (base->chan & (1 << chid))
  56                 return -EBUSY;
  57         base->chan |= (1 << chid);
  58
  59         ret = nouveau_namedb_create_(parent, engine, oclass, 0, NULL,
  60                                      (1ULL << NVDEV_ENGINE_DMAOBJ),
  61                                      length, pobject);
  62         chan = *pobject;
  63         if (ret)
  64                 return ret;
  65
  66         chan->chid = chid;
  67         return 0;
  68 }
  69
  70 void
  71 nv50_disp_chan_destroy(struct nv50_disp_chan *chan)
  72 {
  73         struct nv50_disp_base *base = (void *)nv_object(chan)->parent;
  74         base->chan &= ~(1 << chan->chid);
  75         nouveau_namedb_destroy(&chan->base);
  76 }
  77
  78 u32
  79 nv50_disp_chan_rd32(struct nouveau_object *object, u64 addr)
  80 {
  81         struct nv50_disp_priv *priv = (void *)object->engine;
  82         struct nv50_disp_chan *chan = (void *)object;
  83         return nv_rd32(priv, 0x640000 + (chan->chid * 0x1000) + addr);
  84 }
  85
  86 void
  87 nv50_disp_chan_wr32(struct nouveau_object *object, u64 addr, u32 data)
  88 {
  89         struct nv50_disp_priv *priv = (void *)object->engine;
  90         struct nv50_disp_chan *chan = (void *)object;
  91         nv_wr32(priv, 0x640000 + (chan->chid * 0x1000) + addr, data);
  92 }
  93
  94 /*******************************************************************************
  95  * EVO DMA channel base class
  96  ******************************************************************************/
  97
  98 static int
  99 nv50_disp_dmac_object_attach(struct nouveau_object *parent,
 100                              struct nouveau_object *object, u32 name)
 101 {
 102         struct nv50_disp_base *base = (void *)parent->parent;
 103         struct nv50_disp_chan *chan = (void *)parent;
 104         u32 addr = nv_gpuobj(object)->node->offset;
 105         u32 chid = chan->chid;
 106         u32 data = (chid << 28) | (addr << 10) | chid;
 107         return nouveau_ramht_insert(base->ramht, chid, name, data);
 108 }
 109
 110 static void
 111 nv50_disp_dmac_object_detach(struct nouveau_object *parent, int cookie)
 112 {
 113         struct nv50_disp_base *base = (void *)parent->parent;
 114         nouveau_ramht_remove(base->ramht, cookie);
 115 }
 116
 117 int
 118 nv50_disp_dmac_create_(struct nouveau_object *parent,
 119                        struct nouveau_object *engine,
 120                        struct nouveau_oclass *oclass, u32 pushbuf, int chid,
 121                        int length, void **pobject)
 122 {
 123         struct nv50_disp_dmac *dmac;
 124         int ret;
 125
 126         ret = nv50_disp_chan_create_(parent, engine, oclass, chid,
 127                                      length, pobject);
 128         dmac = *pobject;
 129         if (ret)
 130                 return ret;
 131
 132         dmac->pushdma = (void *)nouveau_handle_ref(parent, pushbuf);
 133         if (!dmac->pushdma)
 134                 return -ENOENT;
 135
 136         switch (nv_mclass(dmac->pushdma)) {
 137         case 0x0002:
 138         case 0x003d:
 139                 if (dmac->pushdma->limit - dmac->pushdma->start != 0xfff)
 140                         return -EINVAL;
 141
 142                 switch (dmac->pushdma->target) {
 143                 case NV_MEM_TARGET_VRAM:
 144                         dmac->push = 0x00000000 | dmac->pushdma->start >> 8;
 145                         break;
 146                 case NV_MEM_TARGET_PCI_NOSNOOP:
 147                         dmac->push = 0x00000003 | dmac->pushdma->start >> 8;
 148                         break;
 149                 default:
 150                         return -EINVAL;
 151                 }
 152                 break;
 153         default:
 154                 return -EINVAL;
 155         }
 156
 157         return 0;
 158 }
 159
 160 void
 161 nv50_disp_dmac_dtor(struct nouveau_object *object)
 162 {
 163         struct nv50_disp_dmac *dmac = (void *)object;
 164         nouveau_object_ref(NULL, (struct nouveau_object **)&dmac->pushdma);
 165         nv50_disp_chan_destroy(&dmac->base);
 166 }
 167
 168 static int
 169 nv50_disp_dmac_init(struct nouveau_object *object)
 170 {
 171         struct nv50_disp_priv *priv = (void *)object->engine;
 172         struct nv50_disp_dmac *dmac = (void *)object;
 173         int chid = dmac->base.chid;
 174         int ret;
 175
 176         ret = nv50_disp_chan_init(&dmac->base);
 177         if (ret)
 178                 return ret;
 179
 180         /* enable error reporting */
 181         nv_mask(priv, 0x610028, 0x00010001 << chid, 0x00010001 << chid);
 182
 183         /* initialise channel for dma command submission */
 184         nv_wr32(priv, 0x610204 + (chid * 0x0010), dmac->push);
 185         nv_wr32(priv, 0x610208 + (chid * 0x0010), 0x00010000);
 186         nv_wr32(priv, 0x61020c + (chid * 0x0010), chid);
 187         nv_mask(priv, 0x610200 + (chid * 0x0010), 0x00000010, 0x00000010);
 188         nv_wr32(priv, 0x640000 + (chid * 0x1000), 0x00000000);
 189         nv_wr32(priv, 0x610200 + (chid * 0x0010), 0x00000013);
 190
 191         /* wait for it to go inactive */
 192         if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x80000000, 0x00000000)) {
 193                 nv_error(dmac, "init timeout, 0x%08x\n",
 194                          nv_rd32(priv, 0x610200 + (chid * 0x10)));
 195                 return -EBUSY;
 196         }
 197
 198         return 0;
 199 }
 200
 201 static int
 202 nv50_disp_dmac_fini(struct nouveau_object *object, bool suspend)
 203 {
 204         struct nv50_disp_priv *priv = (void *)object->engine;
 205         struct nv50_disp_dmac *dmac = (void *)object;
 206         int chid = dmac->base.chid;
 207
 208         /* deactivate channel */
 209         nv_mask(priv, 0x610200 + (chid * 0x0010), 0x00001010, 0x00001000);
 210         nv_mask(priv, 0x610200 + (chid * 0x0010), 0x00000003, 0x00000000);
 211         if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x001e0000, 0x00000000)) {
 212                 nv_error(dmac, "fini timeout, 0x%08x\n",
 213                          nv_rd32(priv, 0x610200 + (chid * 0x10)));
 214                 if (suspend)
 215                         return -EBUSY;
 216         }
 217
 218         /* disable error reporting */
 219         nv_mask(priv, 0x610028, 0x00010001 << chid, 0x00000000 << chid);
 220
 221         return nv50_disp_chan_fini(&dmac->base, suspend);
 222 }
 223
 224 /*******************************************************************************
 225  * EVO master channel object
 226  ******************************************************************************/
 227
 228 static int
 229 nv50_disp_mast_ctor(struct nouveau_object *parent,
 230                     struct nouveau_object *engine,
 231                     struct nouveau_oclass *oclass, void *data, u32 size,
 232                     struct nouveau_object **pobject)
 233 {
 234         struct nv50_display_mast_class *args = data;
 235         struct nv50_disp_dmac *mast;
 236         int ret;
 237
 238         if (size < sizeof(*args))
 239                 return -EINVAL;
 240
 241         ret = nv50_disp_dmac_create_(parent, engine, oclass, args->pushbuf,
 242                                      0, sizeof(*mast), (void **)&mast);
 243         *pobject = nv_object(mast);
 244         if (ret)
 245                 return ret;
 246
 247         nv_parent(mast)->object_attach = nv50_disp_dmac_object_attach;
 248         nv_parent(mast)->object_detach = nv50_disp_dmac_object_detach;
 249         return 0;
 250 }
 251
 252 static int
 253 nv50_disp_mast_init(struct nouveau_object *object)
 254 {
 255         struct nv50_disp_priv *priv = (void *)object->engine;
 256         struct nv50_disp_dmac *mast = (void *)object;
 257         int ret;
 258
 259         ret = nv50_disp_chan_init(&mast->base);
 260         if (ret)
 261                 return ret;
 262
 263         /* enable error reporting */
 264         nv_mask(priv, 0x610028, 0x00010001, 0x00010001);
 265
 266         /* attempt to unstick channel from some unknown state */
 267         if ((nv_rd32(priv, 0x610200) & 0x009f0000) == 0x00020000)
 268                 nv_mask(priv, 0x610200, 0x00800000, 0x00800000);
 269         if ((nv_rd32(priv, 0x610200) & 0x003f0000) == 0x00030000)
 270                 nv_mask(priv, 0x610200, 0x00600000, 0x00600000);
 271
 272         /* initialise channel for dma command submission */
 273         nv_wr32(priv, 0x610204, mast->push);
 274         nv_wr32(priv, 0x610208, 0x00010000);
 275         nv_wr32(priv, 0x61020c, 0x00000000);
 276         nv_mask(priv, 0x610200, 0x00000010, 0x00000010);
 277         nv_wr32(priv, 0x640000, 0x00000000);
 278         nv_wr32(priv, 0x610200, 0x01000013);
 279
 280         /* wait for it to go inactive */
 281         if (!nv_wait(priv, 0x610200, 0x80000000, 0x00000000)) {
 282                 nv_error(mast, "init: 0x%08x\n", nv_rd32(priv, 0x610200));
 283                 return -EBUSY;
 284         }
 285
 286         return 0;
 287 }
 288
 289 static int
 290 nv50_disp_mast_fini(struct nouveau_object *object, bool suspend)
 291 {
 292         struct nv50_disp_priv *priv = (void *)object->engine;
 293         struct nv50_disp_dmac *mast = (void *)object;
 294
 295         /* deactivate channel */
 296         nv_mask(priv, 0x610200, 0x00000010, 0x00000000);
 297         nv_mask(priv, 0x610200, 0x00000003, 0x00000000);
 298         if (!nv_wait(priv, 0x610200, 0x001e0000, 0x00000000)) {
 299                 nv_error(mast, "fini: 0x%08x\n", nv_rd32(priv, 0x610200));
 300                 if (suspend)
 301                         return -EBUSY;
 302         }
 303
 304         /* disable error reporting */
 305         nv_mask(priv, 0x610028, 0x00010001, 0x00000000);
 306
 307         return nv50_disp_chan_fini(&mast->base, suspend);
 308 }
 309
 310 struct nouveau_ofuncs
 311 nv50_disp_mast_ofuncs = {
 312         .ctor = nv50_disp_mast_ctor,
 313         .dtor = nv50_disp_dmac_dtor,
 314         .init = nv50_disp_mast_init,
 315         .fini = nv50_disp_mast_fini,
 316         .rd32 = nv50_disp_chan_rd32,
 317         .wr32 = nv50_disp_chan_wr32,
 318 };
 319
 320 /*******************************************************************************
 321  * EVO sync channel objects
 322  ******************************************************************************/
 323
 324 static int
 325 nv50_disp_sync_ctor(struct nouveau_object *parent,
 326                     struct nouveau_object *engine,
 327                     struct nouveau_oclass *oclass, void *data, u32 size,
 328                     struct nouveau_object **pobject)
 329 {
 330         struct nv50_display_sync_class *args = data;
 331         struct nv50_disp_dmac *dmac;
 332         int ret;
 333
 334         if (size < sizeof(*args) || args->head > 1)
 335                 return -EINVAL;
 336
 337         ret = nv50_disp_dmac_create_(parent, engine, oclass, args->pushbuf,
 338                                      1 + args->head, sizeof(*dmac),
 339                                      (void **)&dmac);
 340         *pobject = nv_object(dmac);
 341         if (ret)
 342                 return ret;
 343
 344         nv_parent(dmac)->object_attach = nv50_disp_dmac_object_attach;
 345         nv_parent(dmac)->object_detach = nv50_disp_dmac_object_detach;
 346         return 0;
 347 }
 348
 349 struct nouveau_ofuncs
 350 nv50_disp_sync_ofuncs = {
 351         .ctor = nv50_disp_sync_ctor,
 352         .dtor = nv50_disp_dmac_dtor,
 353         .init = nv50_disp_dmac_init,
 354         .fini = nv50_disp_dmac_fini,
 355         .rd32 = nv50_disp_chan_rd32,
 356         .wr32 = nv50_disp_chan_wr32,
 357 };
 358
 359 /*******************************************************************************
 360  * EVO overlay channel objects
 361  ******************************************************************************/
 362
 363 static int
 364 nv50_disp_ovly_ctor(struct nouveau_object *parent,
 365                     struct nouveau_object *engine,
 366                     struct nouveau_oclass *oclass, void *data, u32 size,
 367                     struct nouveau_object **pobject)
 368 {
 369         struct nv50_display_ovly_class *args = data;
 370         struct nv50_disp_dmac *dmac;
 371         int ret;
 372
 373         if (size < sizeof(*args) || args->head > 1)
 374                 return -EINVAL;
 375
 376         ret = nv50_disp_dmac_create_(parent, engine, oclass, args->pushbuf,
 377                                      3 + args->head, sizeof(*dmac),
 378                                      (void **)&dmac);
 379         *pobject = nv_object(dmac);
 380         if (ret)
 381                 return ret;
 382
 383         nv_parent(dmac)->object_attach = nv50_disp_dmac_object_attach;
 384         nv_parent(dmac)->object_detach = nv50_disp_dmac_object_detach;
 385         return 0;
 386 }
 387
 388 struct nouveau_ofuncs
 389 nv50_disp_ovly_ofuncs = {
 390         .ctor = nv50_disp_ovly_ctor,
 391         .dtor = nv50_disp_dmac_dtor,
 392         .init = nv50_disp_dmac_init,
 393         .fini = nv50_disp_dmac_fini,
 394         .rd32 = nv50_disp_chan_rd32,
 395         .wr32 = nv50_disp_chan_wr32,
 396 };
 397
 398 /*******************************************************************************
 399  * EVO PIO channel base class
 400  ******************************************************************************/
 401
 402 static int
 403 nv50_disp_pioc_create_(struct nouveau_object *parent,
 404                        struct nouveau_object *engine,
 405                        struct nouveau_oclass *oclass, int chid,
 406                        int length, void **pobject)
 407 {
 408         return nv50_disp_chan_create_(parent, engine, oclass, chid,
 409                                       length, pobject);
 410 }
 411
 412 static void
 413 nv50_disp_pioc_dtor(struct nouveau_object *object)
 414 {
 415         struct nv50_disp_pioc *pioc = (void *)object;
 416         nv50_disp_chan_destroy(&pioc->base);
 417 }
 418
 419 static int
 420 nv50_disp_pioc_init(struct nouveau_object *object)
 421 {
 422         struct nv50_disp_priv *priv = (void *)object->engine;
 423         struct nv50_disp_pioc *pioc = (void *)object;
 424         int chid = pioc->base.chid;
 425         int ret;
 426
 427         ret = nv50_disp_chan_init(&pioc->base);
 428         if (ret)
 429                 return ret;
 430
 431         nv_wr32(priv, 0x610200 + (chid * 0x10), 0x00002000);
 432         if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x00000000, 0x00000000)) {
 433                 nv_error(pioc, "timeout0: 0x%08x\n",
 434                          nv_rd32(priv, 0x610200 + (chid * 0x10)));
 435                 return -EBUSY;
 436         }
 437
 438         nv_wr32(priv, 0x610200 + (chid * 0x10), 0x00000001);
 439         if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x00030000, 0x00010000)) {
 440                 nv_error(pioc, "timeout1: 0x%08x\n",
 441                          nv_rd32(priv, 0x610200 + (chid * 0x10)));
 442                 return -EBUSY;
 443         }
 444
 445         return 0;
 446 }
 447
 448 static int
 449 nv50_disp_pioc_fini(struct nouveau_object *object, bool suspend)
 450 {
 451         struct nv50_disp_priv *priv = (void *)object->engine;
 452         struct nv50_disp_pioc *pioc = (void *)object;
 453         int chid = pioc->base.chid;
 454
 455         nv_mask(priv, 0x610200 + (chid * 0x10), 0x00000001, 0x00000000);
 456         if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x00030000, 0x00000000)) {
 457                 nv_error(pioc, "timeout: 0x%08x\n",
 458                          nv_rd32(priv, 0x610200 + (chid * 0x10)));
 459                 if (suspend)
 460                         return -EBUSY;
 461         }
 462
 463         return nv50_disp_chan_fini(&pioc->base, suspend);
 464 }
 465
 466 /*******************************************************************************
 467  * EVO immediate overlay channel objects
 468  ******************************************************************************/
 469
 470 static int
 471 nv50_disp_oimm_ctor(struct nouveau_object *parent,
 472                     struct nouveau_object *engine,
 473                     struct nouveau_oclass *oclass, void *data, u32 size,
 474                     struct nouveau_object **pobject)
 475 {
 476         struct nv50_display_oimm_class *args = data;
 477         struct nv50_disp_pioc *pioc;
 478         int ret;
 479
 480         if (size < sizeof(*args) || args->head > 1)
 481                 return -EINVAL;
 482
 483         ret = nv50_disp_pioc_create_(parent, engine, oclass, 5 + args->head,
 484                                      sizeof(*pioc), (void **)&pioc);
 485         *pobject = nv_object(pioc);
 486         if (ret)
 487                 return ret;
 488
 489         return 0;
 490 }
 491
 492 struct nouveau_ofuncs
 493 nv50_disp_oimm_ofuncs = {
 494         .ctor = nv50_disp_oimm_ctor,
 495         .dtor = nv50_disp_pioc_dtor,
 496         .init = nv50_disp_pioc_init,
 497         .fini = nv50_disp_pioc_fini,
 498         .rd32 = nv50_disp_chan_rd32,
 499         .wr32 = nv50_disp_chan_wr32,
 500 };
 501
 502 /*******************************************************************************
 503  * EVO cursor channel objects
 504  ******************************************************************************/
 505
 506 static int
 507 nv50_disp_curs_ctor(struct nouveau_object *parent,
 508                     struct nouveau_object *engine,
 509                     struct nouveau_oclass *oclass, void *data, u32 size,
 510                     struct nouveau_object **pobject)
 511 {
 512         struct nv50_display_curs_class *args = data;
 513         struct nv50_disp_pioc *pioc;
 514         int ret;
 515
 516         if (size < sizeof(*args) || args->head > 1)
 517                 return -EINVAL;
 518
 519         ret = nv50_disp_pioc_create_(parent, engine, oclass, 7 + args->head,
 520                                      sizeof(*pioc), (void **)&pioc);
 521         *pobject = nv_object(pioc);
 522         if (ret)
 523                 return ret;
 524
 525         return 0;
 526 }
 527
 528 struct nouveau_ofuncs
 529 nv50_disp_curs_ofuncs = {
 530         .ctor = nv50_disp_curs_ctor,
 531         .dtor = nv50_disp_pioc_dtor,
 532         .init = nv50_disp_pioc_init,
 533         .fini = nv50_disp_pioc_fini,
 534         .rd32 = nv50_disp_chan_rd32,
 535         .wr32 = nv50_disp_chan_wr32,
 536 };
 537
 538 /*******************************************************************************
 539  * Base display object
 540  ******************************************************************************/
 541
 542 int
 543 nv50_disp_base_scanoutpos(struct nouveau_object *object, u32 mthd,
 544                           void *data, u32 size)
 545 {
 546         struct nv50_disp_priv *priv = (void *)object->engine;
 547         struct nv04_display_scanoutpos *args = data;
 548         const int head = (mthd & NV50_DISP_MTHD_HEAD);
 549         u32 blanke, blanks, total;
 550
 551         if (size < sizeof(*args) || head >= priv->head.nr)
 552                 return -EINVAL;
 553         blanke = nv_rd32(priv, 0x610aec + (head * 0x540));
 554         blanks = nv_rd32(priv, 0x610af4 + (head * 0x540));
 555         total  = nv_rd32(priv, 0x610afc + (head * 0x540));
 556
 557         args->vblanke = (blanke & 0xffff0000) >> 16;
 558         args->hblanke = (blanke & 0x0000ffff);
 559         args->vblanks = (blanks & 0xffff0000) >> 16;
 560         args->hblanks = (blanks & 0x0000ffff);
 561         args->vtotal  = ( total & 0xffff0000) >> 16;
 562         args->htotal  = ( total & 0x0000ffff);
 563
 564         args->time[0] = ktime_to_ns(ktime_get());
 565         args->vline   = nv_rd32(priv, 0x616340 + (head * 0x800)) & 0xffff;
 566         args->time[1] = ktime_to_ns(ktime_get()); /* vline read locks hline */
 567         args->hline   = nv_rd32(priv, 0x616344 + (head * 0x800)) & 0xffff;
 568         return 0;
 569 }
 570
 571 static void
 572 nv50_disp_base_vblank_enable(struct nouveau_event *event, int head)
 573 {
 574         nv_mask(event->priv, 0x61002c, (4 << head), (4 << head));
 575 }
 576
 577 static void
 578 nv50_disp_base_vblank_disable(struct nouveau_event *event, int head)
 579 {
 580         nv_mask(event->priv, 0x61002c, (4 << head), 0);
 581 }
 582
 583 static int
 584 nv50_disp_base_ctor(struct nouveau_object *parent,
 585                     struct nouveau_object *engine,
 586                     struct nouveau_oclass *oclass, void *data, u32 size,
 587                     struct nouveau_object **pobject)
 588 {
 589         struct nv50_disp_priv *priv = (void *)engine;
 590         struct nv50_disp_base *base;
 591         int ret;
 592
 593         ret = nouveau_parent_create(parent, engine, oclass, 0,
 594                                     priv->sclass, 0, &base);
 595         *pobject = nv_object(base);
 596         if (ret)
 597                 return ret;
 598
 599         priv->base.vblank->priv = priv;
 600         priv->base.vblank->enable = nv50_disp_base_vblank_enable;
 601         priv->base.vblank->disable = nv50_disp_base_vblank_disable;
 602         return nouveau_ramht_new(nv_object(base), nv_object(base), 0x1000, 0,
 603                                 &base->ramht);
 604 }
 605
 606 static void
 607 nv50_disp_base_dtor(struct nouveau_object *object)
 608 {
 609         struct nv50_disp_base *base = (void *)object;
 610         nouveau_ramht_ref(NULL, &base->ramht);
 611         nouveau_parent_destroy(&base->base);
 612 }
 613
 614 static int
 615 nv50_disp_base_init(struct nouveau_object *object)
 616 {
 617         struct nv50_disp_priv *priv = (void *)object->engine;
 618         struct nv50_disp_base *base = (void *)object;
 619         int ret, i;
 620         u32 tmp;
 621
 622         ret = nouveau_parent_init(&base->base);
 623         if (ret)
 624                 return ret;
 625
 626         /* The below segments of code copying values from one register to
 627          * another appear to inform EVO of the display capabilities or
 628          * something similar.  NFI what the 0x614004 caps are for..
 629          */
 630         tmp = nv_rd32(priv, 0x614004);
 631         nv_wr32(priv, 0x610184, tmp);
 632
 633         /* ... CRTC caps */
 634         for (i = 0; i < priv->head.nr; i++) {
 635                 tmp = nv_rd32(priv, 0x616100 + (i * 0x800));
 636                 nv_wr32(priv, 0x610190 + (i * 0x10), tmp);
 637                 tmp = nv_rd32(priv, 0x616104 + (i * 0x800));
 638                 nv_wr32(priv, 0x610194 + (i * 0x10), tmp);
 639                 tmp = nv_rd32(priv, 0x616108 + (i * 0x800));
 640                 nv_wr32(priv, 0x610198 + (i * 0x10), tmp);
 641                 tmp = nv_rd32(priv, 0x61610c + (i * 0x800));
 642                 nv_wr32(priv, 0x61019c + (i * 0x10), tmp);
 643         }
 644
 645         /* ... DAC caps */
 646         for (i = 0; i < priv->dac.nr; i++) {
 647                 tmp = nv_rd32(priv, 0x61a000 + (i * 0x800));
 648                 nv_wr32(priv, 0x6101d0 + (i * 0x04), tmp);
 649         }
 650
 651         /* ... SOR caps */
 652         for (i = 0; i < priv->sor.nr; i++) {
 653                 tmp = nv_rd32(priv, 0x61c000 + (i * 0x800));
 654                 nv_wr32(priv, 0x6101e0 + (i * 0x04), tmp);
 655         }
 656
 657         /* ... PIOR caps */
 658         for (i = 0; i < priv->pior.nr; i++) {
 659                 tmp = nv_rd32(priv, 0x61e000 + (i * 0x800));
 660                 nv_wr32(priv, 0x6101f0 + (i * 0x04), tmp);
 661         }
 662
 663         /* steal display away from vbios, or something like that */
 664         if (nv_rd32(priv, 0x610024) & 0x00000100) {
 665                 nv_wr32(priv, 0x610024, 0x00000100);
 666                 nv_mask(priv, 0x6194e8, 0x00000001, 0x00000000);
 667                 if (!nv_wait(priv, 0x6194e8, 0x00000002, 0x00000000)) {
 668                         nv_error(priv, "timeout acquiring display\n");
 669                         return -EBUSY;
 670                 }
 671         }
 672
 673         /* point at display engine memory area (hash table, objects) */
 674         nv_wr32(priv, 0x610010, (nv_gpuobj(base->ramht)->addr >> 8) | 9);
 675
 676         /* enable supervisor interrupts, disable everything else */
 677         nv_wr32(priv, 0x61002c, 0x00000370);
 678         nv_wr32(priv, 0x610028, 0x00000000);
 679         return 0;
 680 }
 681
 682 static int
 683 nv50_disp_base_fini(struct nouveau_object *object, bool suspend)
 684 {
 685         struct nv50_disp_priv *priv = (void *)object->engine;
 686         struct nv50_disp_base *base = (void *)object;
 687
 688         /* disable all interrupts */
 689         nv_wr32(priv, 0x610024, 0x00000000);
 690         nv_wr32(priv, 0x610020, 0x00000000);
 691
 692         return nouveau_parent_fini(&base->base, suspend);
 693 }
 694
 695 struct nouveau_ofuncs
 696 nv50_disp_base_ofuncs = {
 697         .ctor = nv50_disp_base_ctor,
 698         .dtor = nv50_disp_base_dtor,
 699         .init = nv50_disp_base_init,
 700         .fini = nv50_disp_base_fini,
 701 };
 702
 703 static struct nouveau_omthds
 704 nv50_disp_base_omthds[] = {
 705         { HEAD_MTHD(NV50_DISP_SCANOUTPOS)     , nv50_disp_base_scanoutpos },
 706         { SOR_MTHD(NV50_DISP_SOR_PWR)         , nv50_sor_mthd },
 707         { SOR_MTHD(NV50_DISP_SOR_LVDS_SCRIPT) , nv50_sor_mthd },
 708         { DAC_MTHD(NV50_DISP_DAC_PWR)         , nv50_dac_mthd },
 709         { DAC_MTHD(NV50_DISP_DAC_LOAD)        , nv50_dac_mthd },
 710         { PIOR_MTHD(NV50_DISP_PIOR_PWR)       , nv50_pior_mthd },
 711         { PIOR_MTHD(NV50_DISP_PIOR_TMDS_PWR)  , nv50_pior_mthd },
 712         { PIOR_MTHD(NV50_DISP_PIOR_DP_PWR)    , nv50_pior_mthd },
 713         {},
 714 };
 715
 716 static struct nouveau_oclass
 717 nv50_disp_base_oclass[] = {
 718         { NV50_DISP_CLASS, &nv50_disp_base_ofuncs, nv50_disp_base_omthds },
 719         {}
 720 };
 721
 722 static struct nouveau_oclass
 723 nv50_disp_sclass[] = {
 724         { NV50_DISP_MAST_CLASS, &nv50_disp_mast_ofuncs },
 725         { NV50_DISP_SYNC_CLASS, &nv50_disp_sync_ofuncs },
 726         { NV50_DISP_OVLY_CLASS, &nv50_disp_ovly_ofuncs },
 727         { NV50_DISP_OIMM_CLASS, &nv50_disp_oimm_ofuncs },
 728         { NV50_DISP_CURS_CLASS, &nv50_disp_curs_ofuncs },
 729         {}
 730 };
 731
 732 /*******************************************************************************
 733  * Display context, tracks instmem allocation and prevents more than one
 734  * client using the display hardware at any time.
 735  ******************************************************************************/
 736
 737 static int
 738 nv50_disp_data_ctor(struct nouveau_object *parent,
 739                     struct nouveau_object *engine,
 740                     struct nouveau_oclass *oclass, void *data, u32 size,
 741                     struct nouveau_object **pobject)
 742 {
 743         struct nv50_disp_priv *priv = (void *)engine;
 744         struct nouveau_engctx *ectx;
 745         int ret = -EBUSY;
 746
 747         /* no context needed for channel objects... */
 748         if (nv_mclass(parent) != NV_DEVICE_CLASS) {
 749                 atomic_inc(&parent->refcount);
 750                 *pobject = parent;
 751                 return 1;
 752         }
 753
 754         /* allocate display hardware to client */
 755         mutex_lock(&nv_subdev(priv)->mutex);
 756         if (list_empty(&nv_engine(priv)->contexts)) {
 757                 ret = nouveau_engctx_create(parent, engine, oclass, NULL,
 758                                             0x10000, 0x10000,
 759                                             NVOBJ_FLAG_HEAP, &ectx);
 760                 *pobject = nv_object(ectx);
 761         }
 762         mutex_unlock(&nv_subdev(priv)->mutex);
 763         return ret;
 764 }
 765
 766 struct nouveau_oclass
 767 nv50_disp_cclass = {
 768         .handle = NV_ENGCTX(DISP, 0x50),
 769         .ofuncs = &(struct nouveau_ofuncs) {
 770                 .ctor = nv50_disp_data_ctor,
 771                 .dtor = _nouveau_engctx_dtor,
 772                 .init = _nouveau_engctx_init,
 773                 .fini = _nouveau_engctx_fini,
 774                 .rd32 = _nouveau_engctx_rd32,
 775                 .wr32 = _nouveau_engctx_wr32,
 776         },
 777 };
 778
 779 /*******************************************************************************
 780  * Display engine implementation
 781  ******************************************************************************/
 782
 783 static void
 784 nv50_disp_intr_error(struct nv50_disp_priv *priv)
 785 {
 786         u32 channels = (nv_rd32(priv, 0x610020) & 0x001f0000) >> 16;
 787         u32 addr, data;
 788         int chid;
 789
 790         for (chid = 0; chid < 5; chid++) {
 791                 if (!(channels & (1 << chid)))
 792                         continue;
 793
 794                 nv_wr32(priv, 0x610020, 0x00010000 << chid);
 795                 addr = nv_rd32(priv, 0x610080 + (chid * 0x08));
 796                 data = nv_rd32(priv, 0x610084 + (chid * 0x08));
 797                 nv_wr32(priv, 0x610080 + (chid * 0x08), 0x90000000);
 798
 799                 nv_error(priv, "chid %d mthd 0x%04x data 0x%08x 0x%08x\n",
 800                          chid, addr & 0xffc, data, addr);
 801         }
 802 }
 803
 804 static u16
 805 exec_lookup(struct nv50_disp_priv *priv, int head, int outp, u32 ctrl,
 806             struct dcb_output *dcb, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
 807             struct nvbios_outp *info)
 808 {
 809         struct nouveau_bios *bios = nouveau_bios(priv);
 810         u16 mask, type, data;
 811
 812         if (outp < 4) {
 813                 type = DCB_OUTPUT_ANALOG;
 814                 mask = 0;
 815         } else
 816         if (outp < 8) {
 817                 switch (ctrl & 0x00000f00) {
 818                 case 0x00000000: type = DCB_OUTPUT_LVDS; mask = 1; break;
 819                 case 0x00000100: type = DCB_OUTPUT_TMDS; mask = 1; break;
 820                 case 0x00000200: type = DCB_OUTPUT_TMDS; mask = 2; break;
 821                 case 0x00000500: type = DCB_OUTPUT_TMDS; mask = 3; break;
 822                 case 0x00000800: type = DCB_OUTPUT_DP; mask = 1; break;
 823                 case 0x00000900: type = DCB_OUTPUT_DP; mask = 2; break;
 824                 default:
 825                         nv_error(priv, "unknown SOR mc 0x%08x\n", ctrl);
 826                         return 0x0000;
 827                 }
 828                 outp -= 4;
 829         } else {
 830                 outp = outp - 8;
 831                 type = 0x0010;
 832                 mask = 0;
 833                 switch (ctrl & 0x00000f00) {
 834                 case 0x00000000: type |= priv->pior.type[outp]; break;
 835                 default:
 836                         nv_error(priv, "unknown PIOR mc 0x%08x\n", ctrl);
 837                         return 0x0000;
 838                 }
 839         }
 840
 841         mask  = 0x00c0 & (mask << 6);
 842         mask |= 0x0001 << outp;
 843         mask |= 0x0100 << head;
 844
 845         data = dcb_outp_match(bios, type, mask, ver, hdr, dcb);
 846         if (!data)
 847                 return 0x0000;
 848
 849         /* off-chip encoders require matching the exact encoder type */
 850         if (dcb->location != 0)
 851                 type |= dcb->extdev << 8;
 852
 853         return nvbios_outp_match(bios, type, mask, ver, hdr, cnt, len, info);
 854 }
 855
 856 static bool
 857 exec_script(struct nv50_disp_priv *priv, int head, int id)
 858 {
 859         struct nouveau_bios *bios = nouveau_bios(priv);
 860         struct nvbios_outp info;
 861         struct dcb_output dcb;
 862         u8  ver, hdr, cnt, len;
 863         u16 data;
 864         u32 ctrl = 0x00000000;
 865         u32 reg;
 866         int i;
 867
 868         /* DAC */
 869         for (i = 0; !(ctrl & (1 << head)) && i < priv->dac.nr; i++)
 870                 ctrl = nv_rd32(priv, 0x610b5c + (i * 8));
 871
 872         /* SOR */
 873         if (!(ctrl & (1 << head))) {
 874                 if (nv_device(priv)->chipset  < 0x90 ||
 875                     nv_device(priv)->chipset == 0x92 ||
 876                     nv_device(priv)->chipset == 0xa0) {
 877                         reg = 0x610b74;
 878                 } else {
 879                         reg = 0x610798;
 880                 }
 881                 for (i = 0; !(ctrl & (1 << head)) && i < priv->sor.nr; i++)
 882                         ctrl = nv_rd32(priv, reg + (i * 8));
 883                 i += 4;
 884         }
 885
 886         /* PIOR */
 887         if (!(ctrl & (1 << head))) {
 888                 for (i = 0; !(ctrl & (1 << head)) && i < priv->pior.nr; i++)
 889                         ctrl = nv_rd32(priv, 0x610b84 + (i * 8));
 890                 i += 8;
 891         }
 892
 893         if (!(ctrl & (1 << head)))
 894                 return false;
 895         i--;
 896
 897         data = exec_lookup(priv, head, i, ctrl, &dcb, &ver, &hdr, &cnt, &len, &info);
 898         if (data) {
 899                 struct nvbios_init init = {
 900                         .subdev = nv_subdev(priv),
 901                         .bios = bios,
 902                         .offset = info.script[id],
 903                         .outp = &dcb,
 904                         .crtc = head,
 905                         .execute = 1,
 906                 };
 907
 908                 return nvbios_exec(&init) == 0;
 909         }
 910
 911         return false;
 912 }
 913
 914 static u32
 915 exec_clkcmp(struct nv50_disp_priv *priv, int head, int id, u32 pclk,
 916             struct dcb_output *outp)
 917 {
 918         struct nouveau_bios *bios = nouveau_bios(priv);
 919         struct nvbios_outp info1;
 920         struct nvbios_ocfg info2;
 921         u8  ver, hdr, cnt, len;
 922         u32 ctrl = 0x00000000;
 923         u32 data, conf = ~0;
 924         u32 reg;
 925         int i;
 926
 927         /* DAC */
 928         for (i = 0; !(ctrl & (1 << head)) && i < priv->dac.nr; i++)
 929                 ctrl = nv_rd32(priv, 0x610b58 + (i * 8));
 930
 931         /* SOR */
 932         if (!(ctrl & (1 << head))) {
 933                 if (nv_device(priv)->chipset  < 0x90 ||
 934                     nv_device(priv)->chipset == 0x92 ||
 935                     nv_device(priv)->chipset == 0xa0) {
 936                         reg = 0x610b70;
 937                 } else {
 938                         reg = 0x610794;
 939                 }
 940                 for (i = 0; !(ctrl & (1 << head)) && i < priv->sor.nr; i++)
 941                         ctrl = nv_rd32(priv, reg + (i * 8));
 942                 i += 4;
 943         }
 944
 945         /* PIOR */
 946         if (!(ctrl & (1 << head))) {
 947                 for (i = 0; !(ctrl & (1 << head)) && i < priv->pior.nr; i++)
 948                         ctrl = nv_rd32(priv, 0x610b80 + (i * 8));
 949                 i += 8;
 950         }
 951
 952         if (!(ctrl & (1 << head)))
 953                 return conf;
 954         i--;
 955
 956         data = exec_lookup(priv, head, i, ctrl, outp, &ver, &hdr, &cnt, &len, &info1);
 957         if (!data)
 958                 return conf;
 959
 960         if (outp->location == 0) {
 961                 switch (outp->type) {
 962                 case DCB_OUTPUT_TMDS:
 963                         conf = (ctrl & 0x00000f00) >> 8;
 964                         if (pclk >= 165000)
 965                                 conf |= 0x0100;
 966                         break;
 967                 case DCB_OUTPUT_LVDS:
 968                         conf = priv->sor.lvdsconf;
 969                         break;
 970                 case DCB_OUTPUT_DP:
 971                         conf = (ctrl & 0x00000f00) >> 8;
 972                         break;
 973                 case DCB_OUTPUT_ANALOG:
 974                 default:
 975                         conf = 0x00ff;
 976                         break;
 977                 }
 978         } else {
 979                 conf = (ctrl & 0x00000f00) >> 8;
 980                 pclk = pclk / 2;
 981         }
 982
 983         data = nvbios_ocfg_match(bios, data, conf, &ver, &hdr, &cnt, &len, &info2);
 984         if (data && id < 0xff) {
 985                 data = nvbios_oclk_match(bios, info2.clkcmp[id], pclk);
 986                 if (data) {
 987                         struct nvbios_init init = {
 988                                 .subdev = nv_subdev(priv),
 989                                 .bios = bios,
 990                                 .offset = data,
 991                                 .outp = outp,
 992                                 .crtc = head,
 993                                 .execute = 1,
 994                         };
 995
 996                         nvbios_exec(&init);
 997                 }
 998         }
 999
1000         return conf;
1001 }
1002
1003 static void
1004 nv50_disp_intr_unk10_0(struct nv50_disp_priv *priv, int head)
1005 {
1006         exec_script(priv, head, 1);
1007 }
1008
1009 static void
1010 nv50_disp_intr_unk20_0(struct nv50_disp_priv *priv, int head)
1011 {
1012         exec_script(priv, head, 2);
1013 }
1014
1015 static void
1016 nv50_disp_intr_unk20_1(struct nv50_disp_priv *priv, int head)
1017 {
1018         struct nouveau_devinit *devinit = nouveau_devinit(priv);
1019         u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff;
1020         if (pclk)
1021                 devinit->pll_set(devinit, PLL_VPLL0 + head, pclk);
1022 }
1023
1024 static void
1025 nv50_disp_intr_unk20_2_dp(struct nv50_disp_priv *priv,
1026                           struct dcb_output *outp, u32 pclk)
1027 {
1028         const int link = !(outp->sorconf.link & 1);
1029         const int   or = ffs(outp->or) - 1;
1030         const u32 soff = (  or * 0x800);
1031         const u32 loff = (link * 0x080) + soff;
1032         const u32 ctrl = nv_rd32(priv, 0x610794 + (or * 8));
1033         const u32 symbol = 100000;
1034         u32 dpctrl = nv_rd32(priv, 0x61c10c + loff) & 0x0000f0000;
1035         u32 clksor = nv_rd32(priv, 0x614300 + soff);
1036         int bestTU = 0, bestVTUi = 0, bestVTUf = 0, bestVTUa = 0;
1037         int TU, VTUi, VTUf, VTUa;
1038         u64 link_data_rate, link_ratio, unk;
1039         u32 best_diff = 64 * symbol;
1040         u32 link_nr, link_bw, bits, r;
1041
1042         /* calculate packed data rate for each lane */
1043         if      (dpctrl > 0x00030000) link_nr = 4;
1044         else if (dpctrl > 0x00010000) link_nr = 2;
1045         else                          link_nr = 1;
1046
1047         if (clksor & 0x000c0000)
1048                 link_bw = 270000;
1049         else
1050                 link_bw = 162000;
1051
1052         if      ((ctrl & 0xf0000) == 0x60000) bits = 30;
1053         else if ((ctrl & 0xf0000) == 0x50000) bits = 24;
1054         else                                  bits = 18;
1055
1056         link_data_rate = (pclk * bits / 8) / link_nr;
1057
1058         /* calculate ratio of packed data rate to link symbol rate */
1059         link_ratio = link_data_rate * symbol;
1060         r = do_div(link_ratio, link_bw);
1061
1062         for (TU = 64; TU >= 32; TU--) {
1063                 /* calculate average number of valid symbols in each TU */
1064                 u32 tu_valid = link_ratio * TU;
1065                 u32 calc, diff;
1066
1067                 /* find a hw representation for the fraction.. */
1068                 VTUi = tu_valid / symbol;
1069                 calc = VTUi * symbol;
1070                 diff = tu_valid - calc;
1071                 if (diff) {
1072                         if (diff >= (symbol / 2)) {
1073                                 VTUf = symbol / (symbol - diff);
1074                                 if (symbol - (VTUf * diff))
1075                                         VTUf++;
1076
1077                                 if (VTUf <= 15) {
1078                                         VTUa  = 1;
1079                                         calc += symbol - (symbol / VTUf);
1080                                 } else {
1081                                         VTUa  = 0;
1082                                         VTUf  = 1;
1083                                         calc += symbol;
1084                                 }
1085                         } else {
1086                                 VTUa  = 0;
1087                                 VTUf  = min((int)(symbol / diff), 15);
1088                                 calc += symbol / VTUf;
1089                         }
1090
1091                         diff = calc - tu_valid;
1092                 } else {
1093                         /* no remainder, but the hw doesn't like the fractional
1094                          * part to be zero.  decrement the integer part and
1095                          * have the fraction add a whole symbol back
1096                          */
1097                         VTUa = 0;
1098                         VTUf = 1;
1099                         VTUi--;
1100                 }
1101
1102                 if (diff < best_diff) {
1103                         best_diff = diff;
1104                         bestTU = TU;
1105                         bestVTUa = VTUa;
1106                         bestVTUf = VTUf;
1107                         bestVTUi = VTUi;
1108                         if (diff == 0)
1109                                 break;
1110                 }
1111         }
1112
1113         if (!bestTU) {
1114                 nv_error(priv, "unable to find suitable dp config\n");
1115                 return;
1116         }
1117
1118         /* XXX close to vbios numbers, but not right */
1119         unk  = (symbol - link_ratio) * bestTU;
1120         unk *= link_ratio;
1121         r = do_div(unk, symbol);
1122         r = do_div(unk, symbol);
1123         unk += 6;
1124
1125         nv_mask(priv, 0x61c10c + loff, 0x000001fc, bestTU << 2);
1126         nv_mask(priv, 0x61c128 + loff, 0x010f7f3f, bestVTUa << 24 |
1127                                                    bestVTUf << 16 |
1128                                                    bestVTUi << 8 | unk);
1129 }
1130
1131 static void
1132 nv50_disp_intr_unk20_2(struct nv50_disp_priv *priv, int head)
1133 {
1134         struct dcb_output outp;
1135         u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff;
1136         u32 hval, hreg = 0x614200 + (head * 0x800);
1137         u32 oval, oreg;
1138         u32 mask;
1139         u32 conf = exec_clkcmp(priv, head, 0xff, pclk, &outp);
1140         if (conf != ~0) {
1141                 if (outp.location == 0 && outp.type == DCB_OUTPUT_DP) {
1142                         u32 soff = (ffs(outp.or) - 1) * 0x08;
1143                         u32 ctrl = nv_rd32(priv, 0x610794 + soff);
1144                         u32 datarate;
1145
1146                         switch ((ctrl & 0x000f0000) >> 16) {
1147                         case 6: datarate = pclk * 30 / 8; break;
1148                         case 5: datarate = pclk * 24 / 8; break;
1149                         case 2:
1150                         default:
1151                                 datarate = pclk * 18 / 8;
1152                                 break;
1153                         }
1154
1155                         nouveau_dp_train(&priv->base, priv->sor.dp,
1156                                          &outp, head, datarate);
1157                 }
1158
1159                 exec_clkcmp(priv, head, 0, pclk, &outp);
1160
1161                 if (!outp.location && outp.type == DCB_OUTPUT_ANALOG) {
1162                         oreg = 0x614280 + (ffs(outp.or) - 1) * 0x800;
1163                         oval = 0x00000000;
1164                         hval = 0x00000000;
1165                         mask = 0xffffffff;
1166                 } else
1167                 if (!outp.location) {
1168                         if (outp.type == DCB_OUTPUT_DP)
1169                                 nv50_disp_intr_unk20_2_dp(priv, &outp, pclk);
1170                         oreg = 0x614300 + (ffs(outp.or) - 1) * 0x800;
1171                         oval = (conf & 0x0100) ? 0x00000101 : 0x00000000;
1172                         hval = 0x00000000;
1173                         mask = 0x00000707;
1174                 } else {
1175                         oreg = 0x614380 + (ffs(outp.or) - 1) * 0x800;
1176                         oval = 0x00000001;
1177                         hval = 0x00000001;
1178                         mask = 0x00000707;
1179                 }
1180
1181                 nv_mask(priv, hreg, 0x0000000f, hval);
1182                 nv_mask(priv, oreg, mask, oval);
1183         }
1184 }
1185
1186 /* If programming a TMDS output on a SOR that can also be configured for
1187  * DisplayPort, make sure NV50_SOR_DP_CTRL_ENABLE is forced off.
1188  *
1189  * It looks like the VBIOS TMDS scripts make an attempt at this, however,
1190  * the VBIOS scripts on at least one board I have only switch it off on
1191  * link 0, causing a blank display if the output has previously been
1192  * programmed for DisplayPort.
1193  */
1194 static void
1195 nv50_disp_intr_unk40_0_tmds(struct nv50_disp_priv *priv, struct dcb_output *outp)
1196 {
1197         struct nouveau_bios *bios = nouveau_bios(priv);
1198         const int link = !(outp->sorconf.link & 1);
1199         const int   or = ffs(outp->or) - 1;
1200         const u32 loff = (or * 0x800) + (link * 0x80);
1201         const u16 mask = (outp->sorconf.link << 6) | outp->or;
1202         u8  ver, hdr;
1203
1204         if (dcb_outp_match(bios, DCB_OUTPUT_DP, mask, &ver, &hdr, outp))
1205                 nv_mask(priv, 0x61c10c + loff, 0x00000001, 0x00000000);
1206 }
1207
1208 static void
1209 nv50_disp_intr_unk40_0(struct nv50_disp_priv *priv, int head)
1210 {
1211         struct dcb_output outp;
1212         u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff;
1213         if (exec_clkcmp(priv, head, 1, pclk, &outp) != ~0) {
1214                 if (outp.location == 0 && outp.type == DCB_OUTPUT_TMDS)
1215                         nv50_disp_intr_unk40_0_tmds(priv, &outp);
1216                 else
1217                 if (outp.location == 1 && outp.type == DCB_OUTPUT_DP) {
1218                         u32 soff = (ffs(outp.or) - 1) * 0x08;
1219                         u32 ctrl = nv_rd32(priv, 0x610b84 + soff);
1220                         u32 datarate;
1221
1222                         switch ((ctrl & 0x000f0000) >> 16) {
1223                         case 6: datarate = pclk * 30 / 8; break;
1224                         case 5: datarate = pclk * 24 / 8; break;
1225                         case 2:
1226                         default:
1227                                 datarate = pclk * 18 / 8;
1228                                 break;
1229                         }
1230
1231                         nouveau_dp_train(&priv->base, priv->pior.dp,
1232                                          &outp, head, datarate);
1233                 }
1234         }
1235 }
1236
1237 void
1238 nv50_disp_intr_supervisor(struct work_struct *work)
1239 {
1240         struct nv50_disp_priv *priv =
1241                 container_of(work, struct nv50_disp_priv, supervisor);
1242         u32 super = nv_rd32(priv, 0x610030);
1243         int head;
1244
1245         nv_debug(priv, "supervisor 0x%08x 0x%08x\n", priv->super, super);
1246
1247         if (priv->super & 0x00000010) {
1248                 for (head = 0; head < priv->head.nr; head++) {
1249                         if (!(super & (0x00000020 << head)))
1250                                 continue;
1251                         if (!(super & (0x00000080 << head)))
1252                                 continue;
1253                         nv50_disp_intr_unk10_0(priv, head);
1254                 }
1255         } else
1256         if (priv->super & 0x00000020) {
1257                 for (head = 0; head < priv->head.nr; head++) {
1258                         if (!(super & (0x00000080 << head)))
1259                                 continue;
1260                         nv50_disp_intr_unk20_0(priv, head);
1261                 }
1262                 for (head = 0; head < priv->head.nr; head++) {
1263                         if (!(super & (0x00000200 << head)))
1264                                 continue;
1265                         nv50_disp_intr_unk20_1(priv, head);
1266                 }
1267                 for (head = 0; head < priv->head.nr; head++) {
1268                         if (!(super & (0x00000080 << head)))
1269                                 continue;
1270                         nv50_disp_intr_unk20_2(priv, head);
1271                 }
1272         } else
1273         if (priv->super & 0x00000040) {
1274                 for (head = 0; head < priv->head.nr; head++) {
1275                         if (!(super & (0x00000080 << head)))
1276                                 continue;
1277                         nv50_disp_intr_unk40_0(priv, head);
1278                 }
1279         }
1280
1281         nv_wr32(priv, 0x610030, 0x80000000);
1282 }
1283
1284 void
1285 nv50_disp_intr(struct nouveau_subdev *subdev)
1286 {
1287         struct nv50_disp_priv *priv = (void *)subdev;
1288         u32 intr0 = nv_rd32(priv, 0x610020);
1289         u32 intr1 = nv_rd32(priv, 0x610024);
1290
1291         if (intr0 & 0x001f0000) {
1292                 nv50_disp_intr_error(priv);
1293                 intr0 &= ~0x001f0000;
1294         }
1295
1296         if (intr1 & 0x00000004) {
1297                 nouveau_event_trigger(priv->base.vblank, 0);
1298                 nv_wr32(priv, 0x610024, 0x00000004);
1299                 intr1 &= ~0x00000004;
1300         }
1301
1302         if (intr1 & 0x00000008) {
1303                 nouveau_event_trigger(priv->base.vblank, 1);
1304                 nv_wr32(priv, 0x610024, 0x00000008);
1305                 intr1 &= ~0x00000008;
1306         }
1307
1308         if (intr1 & 0x00000070) {
1309                 priv->super = (intr1 & 0x00000070);
1310                 schedule_work(&priv->supervisor);
1311                 nv_wr32(priv, 0x610024, priv->super);
1312                 intr1 &= ~0x00000070;
1313         }
1314 }
1315
1316 static int
1317 nv50_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
1318                struct nouveau_oclass *oclass, void *data, u32 size,
1319                struct nouveau_object **pobject)
1320 {
1321         struct nv50_disp_priv *priv;
1322         int ret;
1323
1324         ret = nouveau_disp_create(parent, engine, oclass, 2, "PDISP",
1325                                   "display", &priv);
1326         *pobject = nv_object(priv);
1327         if (ret)
1328                 return ret;
1329
1330         nv_engine(priv)->sclass = nv50_disp_base_oclass;
1331         nv_engine(priv)->cclass = &nv50_disp_cclass;
1332         nv_subdev(priv)->intr = nv50_disp_intr;
1333         INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor);
1334         priv->sclass = nv50_disp_sclass;
1335         priv->head.nr = 2;
1336         priv->dac.nr = 3;
1337         priv->sor.nr = 2;
1338         priv->pior.nr = 3;
1339         priv->dac.power = nv50_dac_power;
1340         priv->dac.sense = nv50_dac_sense;
1341         priv->sor.power = nv50_sor_power;
1342         priv->pior.power = nv50_pior_power;
1343         priv->pior.dp = &nv50_pior_dp_func;
1344         return 0;
1345 }
1346
1347 struct nouveau_oclass *
1348 nv50_disp_oclass = &(struct nv50_disp_impl) {
1349         .base.base.handle = NV_ENGINE(DISP, 0x50),
1350         .base.base.ofuncs = &(struct nouveau_ofuncs) {
1351                 .ctor = nv50_disp_ctor,
1352                 .dtor = _nouveau_disp_dtor,
1353                 .init = _nouveau_disp_init,
1354                 .fini = _nouveau_disp_fini,
1355         },
1356 }.base.base;