2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <core/client.h>
26 #include <core/handle.h>
27 #include <core/namedb.h>
28 #include <core/gpuobj.h>
29 #include <core/engctx.h>
30 #include <core/event.h>
31 #include <core/class.h>
32 #include <core/enum.h>
34 #include <subdev/timer.h>
35 #include <subdev/bar.h>
36 #include <subdev/fb.h>
37 #include <subdev/vm.h>
39 #include <engine/dmaobj.h>
40 #include <engine/fifo.h>
42 struct nvc0_fifo_priv {
43 struct nouveau_fifo base;
45 struct work_struct fault;
49 struct nouveau_gpuobj *mem[2];
51 wait_queue_head_t wait;
55 struct nouveau_gpuobj *mem;
56 struct nouveau_vma bar;
61 struct nvc0_fifo_base {
62 struct nouveau_fifo_base base;
63 struct nouveau_gpuobj *pgd;
64 struct nouveau_vm *vm;
67 struct nvc0_fifo_chan {
68 struct nouveau_fifo_chan base;
76 /*******************************************************************************
77 * FIFO channel objects
78 ******************************************************************************/
81 nvc0_fifo_runlist_update(struct nvc0_fifo_priv *priv)
83 struct nouveau_bar *bar = nouveau_bar(priv);
84 struct nouveau_gpuobj *cur;
87 mutex_lock(&nv_subdev(priv)->mutex);
88 cur = priv->runlist.mem[priv->runlist.active];
89 priv->runlist.active = !priv->runlist.active;
91 for (i = 0, p = 0; i < 128; i++) {
92 struct nvc0_fifo_chan *chan = (void *)priv->base.channel[i];
93 if (chan && chan->state == RUNNING) {
94 nv_wo32(cur, p + 0, i);
95 nv_wo32(cur, p + 4, 0x00000004);
101 nv_wr32(priv, 0x002270, cur->addr >> 12);
102 nv_wr32(priv, 0x002274, 0x01f00000 | (p >> 3));
104 if (wait_event_timeout(priv->runlist.wait,
105 !(nv_rd32(priv, 0x00227c) & 0x00100000),
106 msecs_to_jiffies(2000)) == 0)
107 nv_error(priv, "runlist update timeout\n");
108 mutex_unlock(&nv_subdev(priv)->mutex);
112 nvc0_fifo_context_attach(struct nouveau_object *parent,
113 struct nouveau_object *object)
115 struct nouveau_bar *bar = nouveau_bar(parent);
116 struct nvc0_fifo_base *base = (void *)parent->parent;
117 struct nouveau_engctx *ectx = (void *)object;
121 switch (nv_engidx(object->engine)) {
122 case NVDEV_ENGINE_SW : return 0;
123 case NVDEV_ENGINE_GR : addr = 0x0210; break;
124 case NVDEV_ENGINE_COPY0: addr = 0x0230; break;
125 case NVDEV_ENGINE_COPY1: addr = 0x0240; break;
126 case NVDEV_ENGINE_BSP : addr = 0x0270; break;
127 case NVDEV_ENGINE_VP : addr = 0x0250; break;
128 case NVDEV_ENGINE_PPP : addr = 0x0260; break;
133 if (!ectx->vma.node) {
134 ret = nouveau_gpuobj_map_vm(nv_gpuobj(ectx), base->vm,
135 NV_MEM_ACCESS_RW, &ectx->vma);
139 nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12;
142 nv_wo32(base, addr + 0x00, lower_32_bits(ectx->vma.offset) | 4);
143 nv_wo32(base, addr + 0x04, upper_32_bits(ectx->vma.offset));
149 nvc0_fifo_context_detach(struct nouveau_object *parent, bool suspend,
150 struct nouveau_object *object)
152 struct nouveau_bar *bar = nouveau_bar(parent);
153 struct nvc0_fifo_priv *priv = (void *)parent->engine;
154 struct nvc0_fifo_base *base = (void *)parent->parent;
155 struct nvc0_fifo_chan *chan = (void *)parent;
158 switch (nv_engidx(object->engine)) {
159 case NVDEV_ENGINE_SW : return 0;
160 case NVDEV_ENGINE_GR : addr = 0x0210; break;
161 case NVDEV_ENGINE_COPY0: addr = 0x0230; break;
162 case NVDEV_ENGINE_COPY1: addr = 0x0240; break;
163 case NVDEV_ENGINE_BSP : addr = 0x0270; break;
164 case NVDEV_ENGINE_VP : addr = 0x0250; break;
165 case NVDEV_ENGINE_PPP : addr = 0x0260; break;
170 nv_wr32(priv, 0x002634, chan->base.chid);
171 if (!nv_wait(priv, 0x002634, 0xffffffff, chan->base.chid)) {
172 nv_error(priv, "channel %d [%s] kick timeout\n",
173 chan->base.chid, nouveau_client_name(chan));
178 nv_wo32(base, addr + 0x00, 0x00000000);
179 nv_wo32(base, addr + 0x04, 0x00000000);
185 nvc0_fifo_chan_ctor(struct nouveau_object *parent,
186 struct nouveau_object *engine,
187 struct nouveau_oclass *oclass, void *data, u32 size,
188 struct nouveau_object **pobject)
190 struct nouveau_bar *bar = nouveau_bar(parent);
191 struct nvc0_fifo_priv *priv = (void *)engine;
192 struct nvc0_fifo_base *base = (void *)parent;
193 struct nvc0_fifo_chan *chan;
194 struct nv50_channel_ind_class *args = data;
195 u64 usermem, ioffset, ilength;
198 if (size < sizeof(*args))
201 ret = nouveau_fifo_channel_create(parent, engine, oclass, 1,
202 priv->user.bar.offset, 0x1000,
204 (1ULL << NVDEV_ENGINE_SW) |
205 (1ULL << NVDEV_ENGINE_GR) |
206 (1ULL << NVDEV_ENGINE_COPY0) |
207 (1ULL << NVDEV_ENGINE_COPY1) |
208 (1ULL << NVDEV_ENGINE_BSP) |
209 (1ULL << NVDEV_ENGINE_VP) |
210 (1ULL << NVDEV_ENGINE_PPP), &chan);
211 *pobject = nv_object(chan);
215 nv_parent(chan)->context_attach = nvc0_fifo_context_attach;
216 nv_parent(chan)->context_detach = nvc0_fifo_context_detach;
218 usermem = chan->base.chid * 0x1000;
219 ioffset = args->ioffset;
220 ilength = order_base_2(args->ilength / 8);
222 for (i = 0; i < 0x1000; i += 4)
223 nv_wo32(priv->user.mem, usermem + i, 0x00000000);
225 nv_wo32(base, 0x08, lower_32_bits(priv->user.mem->addr + usermem));
226 nv_wo32(base, 0x0c, upper_32_bits(priv->user.mem->addr + usermem));
227 nv_wo32(base, 0x10, 0x0000face);
228 nv_wo32(base, 0x30, 0xfffff902);
229 nv_wo32(base, 0x48, lower_32_bits(ioffset));
230 nv_wo32(base, 0x4c, upper_32_bits(ioffset) | (ilength << 16));
231 nv_wo32(base, 0x54, 0x00000002);
232 nv_wo32(base, 0x84, 0x20400000);
233 nv_wo32(base, 0x94, 0x30000001);
234 nv_wo32(base, 0x9c, 0x00000100);
235 nv_wo32(base, 0xa4, 0x1f1f1f1f);
236 nv_wo32(base, 0xa8, 0x1f1f1f1f);
237 nv_wo32(base, 0xac, 0x0000001f);
238 nv_wo32(base, 0xb8, 0xf8000000);
239 nv_wo32(base, 0xf8, 0x10003080); /* 0x002310 */
240 nv_wo32(base, 0xfc, 0x10000010); /* 0x002350 */
246 nvc0_fifo_chan_init(struct nouveau_object *object)
248 struct nouveau_gpuobj *base = nv_gpuobj(object->parent);
249 struct nvc0_fifo_priv *priv = (void *)object->engine;
250 struct nvc0_fifo_chan *chan = (void *)object;
251 u32 chid = chan->base.chid;
254 ret = nouveau_fifo_channel_init(&chan->base);
258 nv_wr32(priv, 0x003000 + (chid * 8), 0xc0000000 | base->addr >> 12);
260 if (chan->state == STOPPED && (chan->state = RUNNING) == RUNNING) {
261 nv_wr32(priv, 0x003004 + (chid * 8), 0x001f0001);
262 nvc0_fifo_runlist_update(priv);
268 static void nvc0_fifo_intr_engine(struct nvc0_fifo_priv *priv);
271 nvc0_fifo_chan_fini(struct nouveau_object *object, bool suspend)
273 struct nvc0_fifo_priv *priv = (void *)object->engine;
274 struct nvc0_fifo_chan *chan = (void *)object;
275 u32 chid = chan->base.chid;
277 if (chan->state == RUNNING && (chan->state = STOPPED) == STOPPED) {
278 nv_mask(priv, 0x003004 + (chid * 8), 0x00000001, 0x00000000);
279 nvc0_fifo_runlist_update(priv);
282 nvc0_fifo_intr_engine(priv);
284 nv_wr32(priv, 0x003000 + (chid * 8), 0x00000000);
285 return nouveau_fifo_channel_fini(&chan->base, suspend);
288 static struct nouveau_ofuncs
290 .ctor = nvc0_fifo_chan_ctor,
291 .dtor = _nouveau_fifo_channel_dtor,
292 .init = nvc0_fifo_chan_init,
293 .fini = nvc0_fifo_chan_fini,
294 .rd32 = _nouveau_fifo_channel_rd32,
295 .wr32 = _nouveau_fifo_channel_wr32,
298 static struct nouveau_oclass
299 nvc0_fifo_sclass[] = {
300 { NVC0_CHANNEL_IND_CLASS, &nvc0_fifo_ofuncs },
304 /*******************************************************************************
305 * FIFO context - instmem heap and vm setup
306 ******************************************************************************/
309 nvc0_fifo_context_ctor(struct nouveau_object *parent,
310 struct nouveau_object *engine,
311 struct nouveau_oclass *oclass, void *data, u32 size,
312 struct nouveau_object **pobject)
314 struct nvc0_fifo_base *base;
317 ret = nouveau_fifo_context_create(parent, engine, oclass, NULL, 0x1000,
318 0x1000, NVOBJ_FLAG_ZERO_ALLOC |
319 NVOBJ_FLAG_HEAP, &base);
320 *pobject = nv_object(base);
324 ret = nouveau_gpuobj_new(nv_object(base), NULL, 0x10000, 0x1000, 0,
329 nv_wo32(base, 0x0200, lower_32_bits(base->pgd->addr));
330 nv_wo32(base, 0x0204, upper_32_bits(base->pgd->addr));
331 nv_wo32(base, 0x0208, 0xffffffff);
332 nv_wo32(base, 0x020c, 0x000000ff);
334 ret = nouveau_vm_ref(nouveau_client(parent)->vm, &base->vm, base->pgd);
342 nvc0_fifo_context_dtor(struct nouveau_object *object)
344 struct nvc0_fifo_base *base = (void *)object;
345 nouveau_vm_ref(NULL, &base->vm, base->pgd);
346 nouveau_gpuobj_ref(NULL, &base->pgd);
347 nouveau_fifo_context_destroy(&base->base);
350 static struct nouveau_oclass
352 .handle = NV_ENGCTX(FIFO, 0xc0),
353 .ofuncs = &(struct nouveau_ofuncs) {
354 .ctor = nvc0_fifo_context_ctor,
355 .dtor = nvc0_fifo_context_dtor,
356 .init = _nouveau_fifo_context_init,
357 .fini = _nouveau_fifo_context_fini,
358 .rd32 = _nouveau_fifo_context_rd32,
359 .wr32 = _nouveau_fifo_context_wr32,
363 /*******************************************************************************
365 ******************************************************************************/
368 nvc0_fifo_engidx(struct nvc0_fifo_priv *priv, u32 engn)
371 case NVDEV_ENGINE_GR : engn = 0; break;
372 case NVDEV_ENGINE_BSP : engn = 1; break;
373 case NVDEV_ENGINE_PPP : engn = 2; break;
374 case NVDEV_ENGINE_VP : engn = 3; break;
375 case NVDEV_ENGINE_COPY0: engn = 4; break;
376 case NVDEV_ENGINE_COPY1: engn = 5; break;
384 static inline struct nouveau_engine *
385 nvc0_fifo_engine(struct nvc0_fifo_priv *priv, u32 engn)
388 case 0: engn = NVDEV_ENGINE_GR; break;
389 case 1: engn = NVDEV_ENGINE_BSP; break;
390 case 2: engn = NVDEV_ENGINE_PPP; break;
391 case 3: engn = NVDEV_ENGINE_VP; break;
392 case 4: engn = NVDEV_ENGINE_COPY0; break;
393 case 5: engn = NVDEV_ENGINE_COPY1; break;
398 return nouveau_engine(priv, engn);
402 nvc0_fifo_recover_work(struct work_struct *work)
404 struct nvc0_fifo_priv *priv = container_of(work, typeof(*priv), fault);
405 struct nouveau_object *engine;
410 spin_lock_irqsave(&priv->base.lock, flags);
413 spin_unlock_irqrestore(&priv->base.lock, flags);
415 for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn))
416 engm |= 1 << nvc0_fifo_engidx(priv, engn);
417 nv_mask(priv, 0x002630, engm, engm);
419 for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn)) {
420 if ((engine = (void *)nouveau_engine(priv, engn))) {
421 nv_ofuncs(engine)->fini(engine, false);
422 WARN_ON(nv_ofuncs(engine)->init(engine));
426 nvc0_fifo_runlist_update(priv);
427 nv_wr32(priv, 0x00262c, engm);
428 nv_mask(priv, 0x002630, engm, 0x00000000);
432 nvc0_fifo_recover(struct nvc0_fifo_priv *priv, struct nouveau_engine *engine,
433 struct nvc0_fifo_chan *chan)
435 struct nouveau_object *engobj = nv_object(engine);
436 u32 chid = chan->base.chid;
439 nv_error(priv, "%s engine fault on channel %d, recovering...\n",
440 nv_subdev(engine)->name, chid);
442 nv_mask(priv, 0x003004 + (chid * 0x08), 0x00000001, 0x00000000);
443 chan->state = KILLED;
445 spin_lock_irqsave(&priv->base.lock, flags);
446 priv->mask |= 1ULL << nv_engidx(engobj);
447 spin_unlock_irqrestore(&priv->base.lock, flags);
448 schedule_work(&priv->fault);
452 nvc0_fifo_swmthd(struct nvc0_fifo_priv *priv, u32 chid, u32 mthd, u32 data)
454 struct nvc0_fifo_chan *chan = NULL;
455 struct nouveau_handle *bind;
459 spin_lock_irqsave(&priv->base.lock, flags);
460 if (likely(chid >= priv->base.min && chid <= priv->base.max))
461 chan = (void *)priv->base.channel[chid];
465 bind = nouveau_namedb_get_class(nv_namedb(chan), 0x906e);
467 if (!mthd || !nv_call(bind->object, mthd, data))
469 nouveau_namedb_put(bind);
473 spin_unlock_irqrestore(&priv->base.lock, flags);
477 static const struct nouveau_enum
478 nvc0_fifo_sched_reason[] = {
479 { 0x0a, "CTXSW_TIMEOUT" },
484 nvc0_fifo_intr_sched(struct nvc0_fifo_priv *priv)
486 u32 intr = nv_rd32(priv, 0x00254c);
487 u32 code = intr & 0x000000ff;
488 const struct nouveau_enum *en;
491 en = nouveau_enum_find(nvc0_fifo_sched_reason, code);
493 snprintf(enunk, sizeof(enunk), "UNK%02x", code);
495 nv_error(priv, "SCHED_ERROR [ %s ]\n", en ? en->name : enunk);
498 static const struct nouveau_enum
499 nvc0_fifo_fault_engine[] = {
500 { 0x00, "PGRAPH", NULL, NVDEV_ENGINE_GR },
501 { 0x03, "PEEPHOLE", NULL, NVDEV_ENGINE_IFB },
502 { 0x04, "BAR1", NULL, NVDEV_SUBDEV_BAR },
503 { 0x05, "BAR3", NULL, NVDEV_SUBDEV_INSTMEM },
504 { 0x07, "PFIFO", NULL, NVDEV_ENGINE_FIFO },
505 { 0x10, "PBSP", NULL, NVDEV_ENGINE_BSP },
506 { 0x11, "PPPP", NULL, NVDEV_ENGINE_PPP },
507 { 0x13, "PCOUNTER" },
508 { 0x14, "PVP", NULL, NVDEV_ENGINE_VP },
509 { 0x15, "PCOPY0", NULL, NVDEV_ENGINE_COPY0 },
510 { 0x16, "PCOPY1", NULL, NVDEV_ENGINE_COPY1 },
515 static const struct nouveau_enum
516 nvc0_fifo_fault_reason[] = {
517 { 0x00, "PT_NOT_PRESENT" },
518 { 0x01, "PT_TOO_SHORT" },
519 { 0x02, "PAGE_NOT_PRESENT" },
520 { 0x03, "VM_LIMIT_EXCEEDED" },
521 { 0x04, "NO_CHANNEL" },
522 { 0x05, "PAGE_SYSTEM_ONLY" },
523 { 0x06, "PAGE_READ_ONLY" },
524 { 0x0a, "COMPRESSED_SYSRAM" },
525 { 0x0c, "INVALID_STORAGE_TYPE" },
529 static const struct nouveau_enum
530 nvc0_fifo_fault_hubclient[] = {
533 { 0x04, "DISPATCH" },
536 { 0x07, "BAR_READ" },
537 { 0x08, "BAR_WRITE" },
541 { 0x11, "PCOUNTER" },
544 { 0x15, "CCACHE_POST" },
548 static const struct nouveau_enum
549 nvc0_fifo_fault_gpcclient[] = {
558 nvc0_fifo_intr_fault(struct nvc0_fifo_priv *priv, int unit)
560 u32 inst = nv_rd32(priv, 0x002800 + (unit * 0x10));
561 u32 valo = nv_rd32(priv, 0x002804 + (unit * 0x10));
562 u32 vahi = nv_rd32(priv, 0x002808 + (unit * 0x10));
563 u32 stat = nv_rd32(priv, 0x00280c + (unit * 0x10));
564 u32 gpc = (stat & 0x1f000000) >> 24;
565 u32 client = (stat & 0x00001f00) >> 8;
566 u32 write = (stat & 0x00000080);
567 u32 hub = (stat & 0x00000040);
568 u32 reason = (stat & 0x0000000f);
569 struct nouveau_object *engctx = NULL, *object;
570 struct nouveau_engine *engine = NULL;
571 const struct nouveau_enum *er, *eu, *ec;
577 er = nouveau_enum_find(nvc0_fifo_fault_reason, reason);
579 snprintf(erunk, sizeof(erunk), "UNK%02X", reason);
581 eu = nouveau_enum_find(nvc0_fifo_fault_engine, unit);
584 case NVDEV_SUBDEV_BAR:
585 nv_mask(priv, 0x001704, 0x00000000, 0x00000000);
587 case NVDEV_SUBDEV_INSTMEM:
588 nv_mask(priv, 0x001714, 0x00000000, 0x00000000);
590 case NVDEV_ENGINE_IFB:
591 nv_mask(priv, 0x001718, 0x00000000, 0x00000000);
594 engine = nouveau_engine(priv, eu->data2);
596 engctx = nouveau_engctx_get(engine, inst);
600 snprintf(euunk, sizeof(euunk), "UNK%02x", unit);
604 ec = nouveau_enum_find(nvc0_fifo_fault_hubclient, client);
606 ec = nouveau_enum_find(nvc0_fifo_fault_gpcclient, client);
607 snprintf(gpcid, sizeof(gpcid), "%d", gpc);
611 snprintf(ecunk, sizeof(ecunk), "UNK%02x", client);
613 nv_error(priv, "%s fault at 0x%010llx [%s] from %s/%s%s%s%s on "
614 "channel 0x%010llx [%s]\n", write ? "write" : "read",
615 (u64)vahi << 32 | valo, er ? er->name : erunk,
616 eu ? eu->name : euunk, hub ? "" : "GPC", gpcid, hub ? "" : "/",
617 ec ? ec->name : ecunk, (u64)inst << 12,
618 nouveau_client_name(engctx));
622 switch (nv_mclass(object)) {
623 case NVC0_CHANNEL_IND_CLASS:
624 nvc0_fifo_recover(priv, engine, (void *)object);
627 object = object->parent;
630 nouveau_engctx_put(engctx);
633 static const struct nouveau_bitfield
634 nvc0_fifo_pbdma_intr[] = {
635 /* { 0x00008000, "" } seen with null ib push */
636 { 0x00200000, "ILLEGAL_MTHD" },
637 { 0x00800000, "EMPTY_SUBC" },
642 nvc0_fifo_intr_pbdma(struct nvc0_fifo_priv *priv, int unit)
644 u32 stat = nv_rd32(priv, 0x040108 + (unit * 0x2000));
645 u32 addr = nv_rd32(priv, 0x0400c0 + (unit * 0x2000));
646 u32 data = nv_rd32(priv, 0x0400c4 + (unit * 0x2000));
647 u32 chid = nv_rd32(priv, 0x040120 + (unit * 0x2000)) & 0x7f;
648 u32 subc = (addr & 0x00070000) >> 16;
649 u32 mthd = (addr & 0x00003ffc);
652 if (stat & 0x00800000) {
653 if (!nvc0_fifo_swmthd(priv, chid, mthd, data))
658 nv_error(priv, "PBDMA%d:", unit);
659 nouveau_bitfield_print(nvc0_fifo_pbdma_intr, show);
662 "PBDMA%d: ch %d [%s] subc %d mthd 0x%04x data 0x%08x\n",
664 nouveau_client_name_for_fifo_chid(&priv->base, chid),
668 nv_wr32(priv, 0x0400c0 + (unit * 0x2000), 0x80600008);
669 nv_wr32(priv, 0x040108 + (unit * 0x2000), stat);
673 nvc0_fifo_intr_runlist(struct nvc0_fifo_priv *priv)
675 u32 intr = nv_rd32(priv, 0x002a00);
677 if (intr & 0x10000000) {
678 wake_up(&priv->runlist.wait);
679 nv_wr32(priv, 0x002a00, 0x10000000);
684 nv_error(priv, "RUNLIST 0x%08x\n", intr);
685 nv_wr32(priv, 0x002a00, intr);
690 nvc0_fifo_intr_engine_unit(struct nvc0_fifo_priv *priv, int engn)
692 u32 intr = nv_rd32(priv, 0x0025a8 + (engn * 0x04));
693 u32 inte = nv_rd32(priv, 0x002628);
696 for (unkn = 0; unkn < 8; unkn++) {
697 u32 ints = (intr >> (unkn * 0x04)) & inte;
699 nouveau_event_trigger(priv->base.uevent, 0);
703 nv_error(priv, "ENGINE %d %d %01x", engn, unkn, ints);
704 nv_mask(priv, 0x002628, ints, 0);
708 nv_wr32(priv, 0x0025a8 + (engn * 0x04), intr);
712 nvc0_fifo_intr_engine(struct nvc0_fifo_priv *priv)
714 u32 mask = nv_rd32(priv, 0x0025a4);
716 u32 unit = __ffs(mask);
717 nvc0_fifo_intr_engine_unit(priv, unit);
718 mask &= ~(1 << unit);
723 nvc0_fifo_intr(struct nouveau_subdev *subdev)
725 struct nvc0_fifo_priv *priv = (void *)subdev;
726 u32 mask = nv_rd32(priv, 0x002140);
727 u32 stat = nv_rd32(priv, 0x002100) & mask;
729 if (stat & 0x00000001) {
730 u32 intr = nv_rd32(priv, 0x00252c);
731 nv_warn(priv, "INTR 0x00000001: 0x%08x\n", intr);
732 nv_wr32(priv, 0x002100, 0x00000001);
736 if (stat & 0x00000100) {
737 nvc0_fifo_intr_sched(priv);
738 nv_wr32(priv, 0x002100, 0x00000100);
742 if (stat & 0x00010000) {
743 u32 intr = nv_rd32(priv, 0x00256c);
744 nv_warn(priv, "INTR 0x00010000: 0x%08x\n", intr);
745 nv_wr32(priv, 0x002100, 0x00010000);
749 if (stat & 0x01000000) {
750 u32 intr = nv_rd32(priv, 0x00258c);
751 nv_warn(priv, "INTR 0x01000000: 0x%08x\n", intr);
752 nv_wr32(priv, 0x002100, 0x01000000);
756 if (stat & 0x10000000) {
757 u32 mask = nv_rd32(priv, 0x00259c);
759 u32 unit = __ffs(mask);
760 nvc0_fifo_intr_fault(priv, unit);
761 nv_wr32(priv, 0x00259c, (1 << unit));
762 mask &= ~(1 << unit);
767 if (stat & 0x20000000) {
768 u32 mask = nv_rd32(priv, 0x0025a0);
770 u32 unit = __ffs(mask);
771 nvc0_fifo_intr_pbdma(priv, unit);
772 nv_wr32(priv, 0x0025a0, (1 << unit));
773 mask &= ~(1 << unit);
778 if (stat & 0x40000000) {
779 nvc0_fifo_intr_runlist(priv);
783 if (stat & 0x80000000) {
784 nvc0_fifo_intr_engine(priv);
789 nv_error(priv, "INTR 0x%08x\n", stat);
790 nv_mask(priv, 0x002140, stat, 0x00000000);
791 nv_wr32(priv, 0x002100, stat);
796 nvc0_fifo_uevent_enable(struct nouveau_event *event, int index)
798 struct nvc0_fifo_priv *priv = event->priv;
799 nv_mask(priv, 0x002140, 0x80000000, 0x80000000);
803 nvc0_fifo_uevent_disable(struct nouveau_event *event, int index)
805 struct nvc0_fifo_priv *priv = event->priv;
806 nv_mask(priv, 0x002140, 0x80000000, 0x00000000);
810 nvc0_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
811 struct nouveau_oclass *oclass, void *data, u32 size,
812 struct nouveau_object **pobject)
814 struct nvc0_fifo_priv *priv;
817 ret = nouveau_fifo_create(parent, engine, oclass, 0, 127, &priv);
818 *pobject = nv_object(priv);
822 INIT_WORK(&priv->fault, nvc0_fifo_recover_work);
824 ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 0x1000, 0,
825 &priv->runlist.mem[0]);
829 ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 0x1000, 0,
830 &priv->runlist.mem[1]);
834 init_waitqueue_head(&priv->runlist.wait);
836 ret = nouveau_gpuobj_new(nv_object(priv), NULL, 128 * 0x1000, 0x1000, 0,
841 ret = nouveau_gpuobj_map(priv->user.mem, NV_MEM_ACCESS_RW,
846 priv->base.uevent->enable = nvc0_fifo_uevent_enable;
847 priv->base.uevent->disable = nvc0_fifo_uevent_disable;
848 priv->base.uevent->priv = priv;
850 nv_subdev(priv)->unit = 0x00000100;
851 nv_subdev(priv)->intr = nvc0_fifo_intr;
852 nv_engine(priv)->cclass = &nvc0_fifo_cclass;
853 nv_engine(priv)->sclass = nvc0_fifo_sclass;
858 nvc0_fifo_dtor(struct nouveau_object *object)
860 struct nvc0_fifo_priv *priv = (void *)object;
862 nouveau_gpuobj_unmap(&priv->user.bar);
863 nouveau_gpuobj_ref(NULL, &priv->user.mem);
864 nouveau_gpuobj_ref(NULL, &priv->runlist.mem[0]);
865 nouveau_gpuobj_ref(NULL, &priv->runlist.mem[1]);
867 nouveau_fifo_destroy(&priv->base);
871 nvc0_fifo_init(struct nouveau_object *object)
873 struct nvc0_fifo_priv *priv = (void *)object;
876 ret = nouveau_fifo_init(&priv->base);
880 nv_wr32(priv, 0x000204, 0xffffffff);
881 nv_wr32(priv, 0x002204, 0xffffffff);
883 priv->spoon_nr = hweight32(nv_rd32(priv, 0x002204));
884 nv_debug(priv, "%d PBDMA unit(s)\n", priv->spoon_nr);
886 /* assign engines to PBDMAs */
887 if (priv->spoon_nr >= 3) {
888 nv_wr32(priv, 0x002208, ~(1 << 0)); /* PGRAPH */
889 nv_wr32(priv, 0x00220c, ~(1 << 1)); /* PVP */
890 nv_wr32(priv, 0x002210, ~(1 << 1)); /* PPP */
891 nv_wr32(priv, 0x002214, ~(1 << 1)); /* PBSP */
892 nv_wr32(priv, 0x002218, ~(1 << 2)); /* PCE0 */
893 nv_wr32(priv, 0x00221c, ~(1 << 1)); /* PCE1 */
897 for (i = 0; i < priv->spoon_nr; i++) {
898 nv_mask(priv, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000);
899 nv_wr32(priv, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */
900 nv_wr32(priv, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTREN */
903 nv_mask(priv, 0x002200, 0x00000001, 0x00000001);
904 nv_wr32(priv, 0x002254, 0x10000000 | priv->user.bar.offset >> 12);
906 nv_wr32(priv, 0x002100, 0xffffffff);
907 nv_wr32(priv, 0x002140, 0x7fffffff);
908 nv_wr32(priv, 0x002628, 0x00000001); /* ENGINE_INTR_EN */
912 struct nouveau_oclass *
913 nvc0_fifo_oclass = &(struct nouveau_oclass) {
914 .handle = NV_ENGINE(FIFO, 0xc0),
915 .ofuncs = &(struct nouveau_ofuncs) {
916 .ctor = nvc0_fifo_ctor,
917 .dtor = nvc0_fifo_dtor,
918 .init = nvc0_fifo_init,
919 .fini = _nouveau_fifo_fini,