drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <core/client.h>
  26 #include <core/handle.h>
  27 #include <core/namedb.h>
  28 #include <core/gpuobj.h>
  29 #include <core/engctx.h>
  30 #include <core/event.h>
  31 #include <core/class.h>
  32 #include <core/enum.h>
  33
  34 #include <subdev/timer.h>
  35 #include <subdev/bar.h>
  36 #include <subdev/fb.h>
  37 #include <subdev/vm.h>
  38
  39 #include <engine/dmaobj.h>
  40 #include <engine/fifo.h>
  41
  42 struct nvc0_fifo_priv {
  43         struct nouveau_fifo base;
  44
  45         struct work_struct fault;
  46         u64 mask;
  47
  48         struct {
  49                 struct nouveau_gpuobj *mem[2];
  50                 int active;
  51                 wait_queue_head_t wait;
  52         } runlist;
  53
  54         struct {
  55                 struct nouveau_gpuobj *mem;
  56                 struct nouveau_vma bar;
  57         } user;
  58         int spoon_nr;
  59 };
  60
  61 struct nvc0_fifo_base {
  62         struct nouveau_fifo_base base;
  63         struct nouveau_gpuobj *pgd;
  64         struct nouveau_vm *vm;
  65 };
  66
  67 struct nvc0_fifo_chan {
  68         struct nouveau_fifo_chan base;
  69         enum {
  70                 STOPPED,
  71                 RUNNING,
  72                 KILLED
  73         } state;
  74 };
  75
  76 /*******************************************************************************
  77  * FIFO channel objects
  78  ******************************************************************************/
  79
  80 static void
  81 nvc0_fifo_runlist_update(struct nvc0_fifo_priv *priv)
  82 {
  83         struct nouveau_bar *bar = nouveau_bar(priv);
  84         struct nouveau_gpuobj *cur;
  85         int i, p;
  86
  87         mutex_lock(&nv_subdev(priv)->mutex);
  88         cur = priv->runlist.mem[priv->runlist.active];
  89         priv->runlist.active = !priv->runlist.active;
  90
  91         for (i = 0, p = 0; i < 128; i++) {
  92                 struct nvc0_fifo_chan *chan = (void *)priv->base.channel[i];
  93                 if (chan && chan->state == RUNNING) {
  94                         nv_wo32(cur, p + 0, i);
  95                         nv_wo32(cur, p + 4, 0x00000004);
  96                         p += 8;
  97                 }
  98         }
  99         bar->flush(bar);
 100
 101         nv_wr32(priv, 0x002270, cur->addr >> 12);
 102         nv_wr32(priv, 0x002274, 0x01f00000 | (p >> 3));
 103
 104         if (wait_event_timeout(priv->runlist.wait,
 105                                !(nv_rd32(priv, 0x00227c) & 0x00100000),
 106                                msecs_to_jiffies(2000)) == 0)
 107                 nv_error(priv, "runlist update timeout\n");
 108         mutex_unlock(&nv_subdev(priv)->mutex);
 109 }
 110
 111 static int
 112 nvc0_fifo_context_attach(struct nouveau_object *parent,
 113                          struct nouveau_object *object)
 114 {
 115         struct nouveau_bar *bar = nouveau_bar(parent);
 116         struct nvc0_fifo_base *base = (void *)parent->parent;
 117         struct nouveau_engctx *ectx = (void *)object;
 118         u32 addr;
 119         int ret;
 120
 121         switch (nv_engidx(object->engine)) {
 122         case NVDEV_ENGINE_SW   : return 0;
 123         case NVDEV_ENGINE_GR   : addr = 0x0210; break;
 124         case NVDEV_ENGINE_COPY0: addr = 0x0230; break;
 125         case NVDEV_ENGINE_COPY1: addr = 0x0240; break;
 126         case NVDEV_ENGINE_BSP  : addr = 0x0270; break;
 127         case NVDEV_ENGINE_VP   : addr = 0x0250; break;
 128         case NVDEV_ENGINE_PPP  : addr = 0x0260; break;
 129         default:
 130                 return -EINVAL;
 131         }
 132
 133         if (!ectx->vma.node) {
 134                 ret = nouveau_gpuobj_map_vm(nv_gpuobj(ectx), base->vm,
 135                                             NV_MEM_ACCESS_RW, &ectx->vma);
 136                 if (ret)
 137                         return ret;
 138
 139                 nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12;
 140         }
 141
 142         nv_wo32(base, addr + 0x00, lower_32_bits(ectx->vma.offset) | 4);
 143         nv_wo32(base, addr + 0x04, upper_32_bits(ectx->vma.offset));
 144         bar->flush(bar);
 145         return 0;
 146 }
 147
 148 static int
 149 nvc0_fifo_context_detach(struct nouveau_object *parent, bool suspend,
 150                          struct nouveau_object *object)
 151 {
 152         struct nouveau_bar *bar = nouveau_bar(parent);
 153         struct nvc0_fifo_priv *priv = (void *)parent->engine;
 154         struct nvc0_fifo_base *base = (void *)parent->parent;
 155         struct nvc0_fifo_chan *chan = (void *)parent;
 156         u32 addr;
 157
 158         switch (nv_engidx(object->engine)) {
 159         case NVDEV_ENGINE_SW   : return 0;
 160         case NVDEV_ENGINE_GR   : addr = 0x0210; break;
 161         case NVDEV_ENGINE_COPY0: addr = 0x0230; break;
 162         case NVDEV_ENGINE_COPY1: addr = 0x0240; break;
 163         case NVDEV_ENGINE_BSP  : addr = 0x0270; break;
 164         case NVDEV_ENGINE_VP   : addr = 0x0250; break;
 165         case NVDEV_ENGINE_PPP  : addr = 0x0260; break;
 166         default:
 167                 return -EINVAL;
 168         }
 169
 170         nv_wr32(priv, 0x002634, chan->base.chid);
 171         if (!nv_wait(priv, 0x002634, 0xffffffff, chan->base.chid)) {
 172                 nv_error(priv, "channel %d [%s] kick timeout\n",
 173                          chan->base.chid, nouveau_client_name(chan));
 174                 if (suspend)
 175                         return -EBUSY;
 176         }
 177
 178         nv_wo32(base, addr + 0x00, 0x00000000);
 179         nv_wo32(base, addr + 0x04, 0x00000000);
 180         bar->flush(bar);
 181         return 0;
 182 }
 183
 184 static int
 185 nvc0_fifo_chan_ctor(struct nouveau_object *parent,
 186                     struct nouveau_object *engine,
 187                     struct nouveau_oclass *oclass, void *data, u32 size,
 188                     struct nouveau_object **pobject)
 189 {
 190         struct nouveau_bar *bar = nouveau_bar(parent);
 191         struct nvc0_fifo_priv *priv = (void *)engine;
 192         struct nvc0_fifo_base *base = (void *)parent;
 193         struct nvc0_fifo_chan *chan;
 194         struct nv50_channel_ind_class *args = data;
 195         u64 usermem, ioffset, ilength;
 196         int ret, i;
 197
 198         if (size < sizeof(*args))
 199                 return -EINVAL;
 200
 201         ret = nouveau_fifo_channel_create(parent, engine, oclass, 1,
 202                                           priv->user.bar.offset, 0x1000,
 203                                           args->pushbuf,
 204                                           (1ULL << NVDEV_ENGINE_SW) |
 205                                           (1ULL << NVDEV_ENGINE_GR) |
 206                                           (1ULL << NVDEV_ENGINE_COPY0) |
 207                                           (1ULL << NVDEV_ENGINE_COPY1) |
 208                                           (1ULL << NVDEV_ENGINE_BSP) |
 209                                           (1ULL << NVDEV_ENGINE_VP) |
 210                                           (1ULL << NVDEV_ENGINE_PPP), &chan);
 211         *pobject = nv_object(chan);
 212         if (ret)
 213                 return ret;
 214
 215         nv_parent(chan)->context_attach = nvc0_fifo_context_attach;
 216         nv_parent(chan)->context_detach = nvc0_fifo_context_detach;
 217
 218         usermem = chan->base.chid * 0x1000;
 219         ioffset = args->ioffset;
 220         ilength = order_base_2(args->ilength / 8);
 221
 222         for (i = 0; i < 0x1000; i += 4)
 223                 nv_wo32(priv->user.mem, usermem + i, 0x00000000);
 224
 225         nv_wo32(base, 0x08, lower_32_bits(priv->user.mem->addr + usermem));
 226         nv_wo32(base, 0x0c, upper_32_bits(priv->user.mem->addr + usermem));
 227         nv_wo32(base, 0x10, 0x0000face);
 228         nv_wo32(base, 0x30, 0xfffff902);
 229         nv_wo32(base, 0x48, lower_32_bits(ioffset));
 230         nv_wo32(base, 0x4c, upper_32_bits(ioffset) | (ilength << 16));
 231         nv_wo32(base, 0x54, 0x00000002);
 232         nv_wo32(base, 0x84, 0x20400000);
 233         nv_wo32(base, 0x94, 0x30000001);
 234         nv_wo32(base, 0x9c, 0x00000100);
 235         nv_wo32(base, 0xa4, 0x1f1f1f1f);
 236         nv_wo32(base, 0xa8, 0x1f1f1f1f);
 237         nv_wo32(base, 0xac, 0x0000001f);
 238         nv_wo32(base, 0xb8, 0xf8000000);
 239         nv_wo32(base, 0xf8, 0x10003080); /* 0x002310 */
 240         nv_wo32(base, 0xfc, 0x10000010); /* 0x002350 */
 241         bar->flush(bar);
 242         return 0;
 243 }
 244
 245 static int
 246 nvc0_fifo_chan_init(struct nouveau_object *object)
 247 {
 248         struct nouveau_gpuobj *base = nv_gpuobj(object->parent);
 249         struct nvc0_fifo_priv *priv = (void *)object->engine;
 250         struct nvc0_fifo_chan *chan = (void *)object;
 251         u32 chid = chan->base.chid;
 252         int ret;
 253
 254         ret = nouveau_fifo_channel_init(&chan->base);
 255         if (ret)
 256                 return ret;
 257
 258         nv_wr32(priv, 0x003000 + (chid * 8), 0xc0000000 | base->addr >> 12);
 259
 260         if (chan->state == STOPPED && (chan->state = RUNNING) == RUNNING) {
 261                 nv_wr32(priv, 0x003004 + (chid * 8), 0x001f0001);
 262                 nvc0_fifo_runlist_update(priv);
 263         }
 264
 265         return 0;
 266 }
 267
 268 static void nvc0_fifo_intr_engine(struct nvc0_fifo_priv *priv);
 269
 270 static int
 271 nvc0_fifo_chan_fini(struct nouveau_object *object, bool suspend)
 272 {
 273         struct nvc0_fifo_priv *priv = (void *)object->engine;
 274         struct nvc0_fifo_chan *chan = (void *)object;
 275         u32 chid = chan->base.chid;
 276
 277         if (chan->state == RUNNING && (chan->state = STOPPED) == STOPPED) {
 278                 nv_mask(priv, 0x003004 + (chid * 8), 0x00000001, 0x00000000);
 279                 nvc0_fifo_runlist_update(priv);
 280         }
 281
 282         nvc0_fifo_intr_engine(priv);
 283
 284         nv_wr32(priv, 0x003000 + (chid * 8), 0x00000000);
 285         return nouveau_fifo_channel_fini(&chan->base, suspend);
 286 }
 287
 288 static struct nouveau_ofuncs
 289 nvc0_fifo_ofuncs = {
 290         .ctor = nvc0_fifo_chan_ctor,
 291         .dtor = _nouveau_fifo_channel_dtor,
 292         .init = nvc0_fifo_chan_init,
 293         .fini = nvc0_fifo_chan_fini,
 294         .rd32 = _nouveau_fifo_channel_rd32,
 295         .wr32 = _nouveau_fifo_channel_wr32,
 296 };
 297
 298 static struct nouveau_oclass
 299 nvc0_fifo_sclass[] = {
 300         { NVC0_CHANNEL_IND_CLASS, &nvc0_fifo_ofuncs },
 301         {}
 302 };
 303
 304 /*******************************************************************************
 305  * FIFO context - instmem heap and vm setup
 306  ******************************************************************************/
 307
 308 static int
 309 nvc0_fifo_context_ctor(struct nouveau_object *parent,
 310                        struct nouveau_object *engine,
 311                        struct nouveau_oclass *oclass, void *data, u32 size,
 312                        struct nouveau_object **pobject)
 313 {
 314         struct nvc0_fifo_base *base;
 315         int ret;
 316
 317         ret = nouveau_fifo_context_create(parent, engine, oclass, NULL, 0x1000,
 318                                           0x1000, NVOBJ_FLAG_ZERO_ALLOC |
 319                                           NVOBJ_FLAG_HEAP, &base);
 320         *pobject = nv_object(base);
 321         if (ret)
 322                 return ret;
 323
 324         ret = nouveau_gpuobj_new(nv_object(base), NULL, 0x10000, 0x1000, 0,
 325                                 &base->pgd);
 326         if (ret)
 327                 return ret;
 328
 329         nv_wo32(base, 0x0200, lower_32_bits(base->pgd->addr));
 330         nv_wo32(base, 0x0204, upper_32_bits(base->pgd->addr));
 331         nv_wo32(base, 0x0208, 0xffffffff);
 332         nv_wo32(base, 0x020c, 0x000000ff);
 333
 334         ret = nouveau_vm_ref(nouveau_client(parent)->vm, &base->vm, base->pgd);
 335         if (ret)
 336                 return ret;
 337
 338         return 0;
 339 }
 340
 341 static void
 342 nvc0_fifo_context_dtor(struct nouveau_object *object)
 343 {
 344         struct nvc0_fifo_base *base = (void *)object;
 345         nouveau_vm_ref(NULL, &base->vm, base->pgd);
 346         nouveau_gpuobj_ref(NULL, &base->pgd);
 347         nouveau_fifo_context_destroy(&base->base);
 348 }
 349
 350 static struct nouveau_oclass
 351 nvc0_fifo_cclass = {
 352         .handle = NV_ENGCTX(FIFO, 0xc0),
 353         .ofuncs = &(struct nouveau_ofuncs) {
 354                 .ctor = nvc0_fifo_context_ctor,
 355                 .dtor = nvc0_fifo_context_dtor,
 356                 .init = _nouveau_fifo_context_init,
 357                 .fini = _nouveau_fifo_context_fini,
 358                 .rd32 = _nouveau_fifo_context_rd32,
 359                 .wr32 = _nouveau_fifo_context_wr32,
 360         },
 361 };
 362
 363 /*******************************************************************************
 364  * PFIFO engine
 365  ******************************************************************************/
 366
 367 static inline int
 368 nvc0_fifo_engidx(struct nvc0_fifo_priv *priv, u32 engn)
 369 {
 370         switch (engn) {
 371         case NVDEV_ENGINE_GR   : engn = 0; break;
 372         case NVDEV_ENGINE_BSP  : engn = 1; break;
 373         case NVDEV_ENGINE_PPP  : engn = 2; break;
 374         case NVDEV_ENGINE_VP   : engn = 3; break;
 375         case NVDEV_ENGINE_COPY0: engn = 4; break;
 376         case NVDEV_ENGINE_COPY1: engn = 5; break;
 377         default:
 378                 return -1;
 379         }
 380
 381         return engn;
 382 }
 383
 384 static inline struct nouveau_engine *
 385 nvc0_fifo_engine(struct nvc0_fifo_priv *priv, u32 engn)
 386 {
 387         switch (engn) {
 388         case 0: engn = NVDEV_ENGINE_GR; break;
 389         case 1: engn = NVDEV_ENGINE_BSP; break;
 390         case 2: engn = NVDEV_ENGINE_PPP; break;
 391         case 3: engn = NVDEV_ENGINE_VP; break;
 392         case 4: engn = NVDEV_ENGINE_COPY0; break;
 393         case 5: engn = NVDEV_ENGINE_COPY1; break;
 394         default:
 395                 return NULL;
 396         }
 397
 398         return nouveau_engine(priv, engn);
 399 }
 400
 401 static void
 402 nvc0_fifo_recover_work(struct work_struct *work)
 403 {
 404         struct nvc0_fifo_priv *priv = container_of(work, typeof(*priv), fault);
 405         struct nouveau_object *engine;
 406         unsigned long flags;
 407         u32 engn, engm = 0;
 408         u64 mask, todo;
 409
 410         spin_lock_irqsave(&priv->base.lock, flags);
 411         mask = priv->mask;
 412         priv->mask = 0ULL;
 413         spin_unlock_irqrestore(&priv->base.lock, flags);
 414
 415         for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn))
 416                 engm |= 1 << nvc0_fifo_engidx(priv, engn);
 417         nv_mask(priv, 0x002630, engm, engm);
 418
 419         for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn)) {
 420                 if ((engine = (void *)nouveau_engine(priv, engn))) {
 421                         nv_ofuncs(engine)->fini(engine, false);
 422                         WARN_ON(nv_ofuncs(engine)->init(engine));
 423                 }
 424         }
 425
 426         nvc0_fifo_runlist_update(priv);
 427         nv_wr32(priv, 0x00262c, engm);
 428         nv_mask(priv, 0x002630, engm, 0x00000000);
 429 }
 430
 431 static void
 432 nvc0_fifo_recover(struct nvc0_fifo_priv *priv, struct nouveau_engine *engine,
 433                   struct nvc0_fifo_chan *chan)
 434 {
 435         struct nouveau_object *engobj = nv_object(engine);
 436         u32 chid = chan->base.chid;
 437         unsigned long flags;
 438
 439         nv_error(priv, "%s engine fault on channel %d, recovering...\n",
 440                        nv_subdev(engine)->name, chid);
 441
 442         nv_mask(priv, 0x003004 + (chid * 0x08), 0x00000001, 0x00000000);
 443         chan->state = KILLED;
 444
 445         spin_lock_irqsave(&priv->base.lock, flags);
 446         priv->mask |= 1ULL << nv_engidx(engobj);
 447         spin_unlock_irqrestore(&priv->base.lock, flags);
 448         schedule_work(&priv->fault);
 449 }
 450
 451 static int
 452 nvc0_fifo_swmthd(struct nvc0_fifo_priv *priv, u32 chid, u32 mthd, u32 data)
 453 {
 454         struct nvc0_fifo_chan *chan = NULL;
 455         struct nouveau_handle *bind;
 456         unsigned long flags;
 457         int ret = -EINVAL;
 458
 459         spin_lock_irqsave(&priv->base.lock, flags);
 460         if (likely(chid >= priv->base.min && chid <= priv->base.max))
 461                 chan = (void *)priv->base.channel[chid];
 462         if (unlikely(!chan))
 463                 goto out;
 464
 465         bind = nouveau_namedb_get_class(nv_namedb(chan), 0x906e);
 466         if (likely(bind)) {
 467                 if (!mthd || !nv_call(bind->object, mthd, data))
 468                         ret = 0;
 469                 nouveau_namedb_put(bind);
 470         }
 471
 472 out:
 473         spin_unlock_irqrestore(&priv->base.lock, flags);
 474         return ret;
 475 }
 476
 477 static const struct nouveau_enum
 478 nvc0_fifo_sched_reason[] = {
 479         { 0x0a, "CTXSW_TIMEOUT" },
 480         {}
 481 };
 482
 483 static void
 484 nvc0_fifo_intr_sched(struct nvc0_fifo_priv *priv)
 485 {
 486         u32 intr = nv_rd32(priv, 0x00254c);
 487         u32 code = intr & 0x000000ff;
 488         const struct nouveau_enum *en;
 489         char enunk[6] = "";
 490
 491         en = nouveau_enum_find(nvc0_fifo_sched_reason, code);
 492         if (!en)
 493                 snprintf(enunk, sizeof(enunk), "UNK%02x", code);
 494
 495         nv_error(priv, "SCHED_ERROR [ %s ]\n", en ? en->name : enunk);
 496 }
 497
 498 static const struct nouveau_enum
 499 nvc0_fifo_fault_engine[] = {
 500         { 0x00, "PGRAPH", NULL, NVDEV_ENGINE_GR },
 501         { 0x03, "PEEPHOLE", NULL, NVDEV_ENGINE_IFB },
 502         { 0x04, "BAR1", NULL, NVDEV_SUBDEV_BAR },
 503         { 0x05, "BAR3", NULL, NVDEV_SUBDEV_INSTMEM },
 504         { 0x07, "PFIFO", NULL, NVDEV_ENGINE_FIFO },
 505         { 0x10, "PBSP", NULL, NVDEV_ENGINE_BSP },
 506         { 0x11, "PPPP", NULL, NVDEV_ENGINE_PPP },
 507         { 0x13, "PCOUNTER" },
 508         { 0x14, "PVP", NULL, NVDEV_ENGINE_VP },
 509         { 0x15, "PCOPY0", NULL, NVDEV_ENGINE_COPY0 },
 510         { 0x16, "PCOPY1", NULL, NVDEV_ENGINE_COPY1 },
 511         { 0x17, "PDAEMON" },
 512         {}
 513 };
 514
 515 static const struct nouveau_enum
 516 nvc0_fifo_fault_reason[] = {
 517         { 0x00, "PT_NOT_PRESENT" },
 518         { 0x01, "PT_TOO_SHORT" },
 519         { 0x02, "PAGE_NOT_PRESENT" },
 520         { 0x03, "VM_LIMIT_EXCEEDED" },
 521         { 0x04, "NO_CHANNEL" },
 522         { 0x05, "PAGE_SYSTEM_ONLY" },
 523         { 0x06, "PAGE_READ_ONLY" },
 524         { 0x0a, "COMPRESSED_SYSRAM" },
 525         { 0x0c, "INVALID_STORAGE_TYPE" },
 526         {}
 527 };
 528
 529 static const struct nouveau_enum
 530 nvc0_fifo_fault_hubclient[] = {
 531         { 0x01, "PCOPY0" },
 532         { 0x02, "PCOPY1" },
 533         { 0x04, "DISPATCH" },
 534         { 0x05, "CTXCTL" },
 535         { 0x06, "PFIFO" },
 536         { 0x07, "BAR_READ" },
 537         { 0x08, "BAR_WRITE" },
 538         { 0x0b, "PVP" },
 539         { 0x0c, "PPPP" },
 540         { 0x0d, "PBSP" },
 541         { 0x11, "PCOUNTER" },
 542         { 0x12, "PDAEMON" },
 543         { 0x14, "CCACHE" },
 544         { 0x15, "CCACHE_POST" },
 545         {}
 546 };
 547
 548 static const struct nouveau_enum
 549 nvc0_fifo_fault_gpcclient[] = {
 550         { 0x01, "TEX" },
 551         { 0x0c, "ESETUP" },
 552         { 0x0e, "CTXCTL" },
 553         { 0x0f, "PROP" },
 554         {}
 555 };
 556
 557 static void
 558 nvc0_fifo_intr_fault(struct nvc0_fifo_priv *priv, int unit)
 559 {
 560         u32 inst = nv_rd32(priv, 0x002800 + (unit * 0x10));
 561         u32 valo = nv_rd32(priv, 0x002804 + (unit * 0x10));
 562         u32 vahi = nv_rd32(priv, 0x002808 + (unit * 0x10));
 563         u32 stat = nv_rd32(priv, 0x00280c + (unit * 0x10));
 564         u32 gpc    = (stat & 0x1f000000) >> 24;
 565         u32 client = (stat & 0x00001f00) >> 8;
 566         u32 write  = (stat & 0x00000080);
 567         u32 hub    = (stat & 0x00000040);
 568         u32 reason = (stat & 0x0000000f);
 569         struct nouveau_object *engctx = NULL, *object;
 570         struct nouveau_engine *engine = NULL;
 571         const struct nouveau_enum *er, *eu, *ec;
 572         char erunk[6] = "";
 573         char euunk[6] = "";
 574         char ecunk[6] = "";
 575         char gpcid[3] = "";
 576
 577         er = nouveau_enum_find(nvc0_fifo_fault_reason, reason);
 578         if (!er)
 579                 snprintf(erunk, sizeof(erunk), "UNK%02X", reason);
 580
 581         eu = nouveau_enum_find(nvc0_fifo_fault_engine, unit);
 582         if (eu) {
 583                 switch (eu->data2) {
 584                 case NVDEV_SUBDEV_BAR:
 585                         nv_mask(priv, 0x001704, 0x00000000, 0x00000000);
 586                         break;
 587                 case NVDEV_SUBDEV_INSTMEM:
 588                         nv_mask(priv, 0x001714, 0x00000000, 0x00000000);
 589                         break;
 590                 case NVDEV_ENGINE_IFB:
 591                         nv_mask(priv, 0x001718, 0x00000000, 0x00000000);
 592                         break;
 593                 default:
 594                         engine = nouveau_engine(priv, eu->data2);
 595                         if (engine)
 596                                 engctx = nouveau_engctx_get(engine, inst);
 597                         break;
 598                 }
 599         } else {
 600                 snprintf(euunk, sizeof(euunk), "UNK%02x", unit);
 601         }
 602
 603         if (hub) {
 604                 ec = nouveau_enum_find(nvc0_fifo_fault_hubclient, client);
 605         } else {
 606                 ec = nouveau_enum_find(nvc0_fifo_fault_gpcclient, client);
 607                 snprintf(gpcid, sizeof(gpcid), "%d", gpc);
 608         }
 609
 610         if (!ec)
 611                 snprintf(ecunk, sizeof(ecunk), "UNK%02x", client);
 612
 613         nv_error(priv, "%s fault at 0x%010llx [%s] from %s/%s%s%s%s on "
 614                        "channel 0x%010llx [%s]\n", write ? "write" : "read",
 615                  (u64)vahi << 32 | valo, er ? er->name : erunk,
 616                  eu ? eu->name : euunk, hub ? "" : "GPC", gpcid, hub ? "" : "/",
 617                  ec ? ec->name : ecunk, (u64)inst << 12,
 618                  nouveau_client_name(engctx));
 619
 620         object = engctx;
 621         while (object) {
 622                 switch (nv_mclass(object)) {
 623                 case NVC0_CHANNEL_IND_CLASS:
 624                         nvc0_fifo_recover(priv, engine, (void *)object);
 625                         break;
 626                 }
 627                 object = object->parent;
 628         }
 629
 630         nouveau_engctx_put(engctx);
 631 }
 632
 633 static const struct nouveau_bitfield
 634 nvc0_fifo_pbdma_intr[] = {
 635 /*      { 0x00008000, "" }      seen with null ib push */
 636         { 0x00200000, "ILLEGAL_MTHD" },
 637         { 0x00800000, "EMPTY_SUBC" },
 638         {}
 639 };
 640
 641 static void
 642 nvc0_fifo_intr_pbdma(struct nvc0_fifo_priv *priv, int unit)
 643 {
 644         u32 stat = nv_rd32(priv, 0x040108 + (unit * 0x2000));
 645         u32 addr = nv_rd32(priv, 0x0400c0 + (unit * 0x2000));
 646         u32 data = nv_rd32(priv, 0x0400c4 + (unit * 0x2000));
 647         u32 chid = nv_rd32(priv, 0x040120 + (unit * 0x2000)) & 0x7f;
 648         u32 subc = (addr & 0x00070000) >> 16;
 649         u32 mthd = (addr & 0x00003ffc);
 650         u32 show = stat;
 651
 652         if (stat & 0x00800000) {
 653                 if (!nvc0_fifo_swmthd(priv, chid, mthd, data))
 654                         show &= ~0x00800000;
 655         }
 656
 657         if (show) {
 658                 nv_error(priv, "PBDMA%d:", unit);
 659                 nouveau_bitfield_print(nvc0_fifo_pbdma_intr, show);
 660                 pr_cont("\n");
 661                 nv_error(priv,
 662                          "PBDMA%d: ch %d [%s] subc %d mthd 0x%04x data 0x%08x\n",
 663                          unit, chid,
 664                          nouveau_client_name_for_fifo_chid(&priv->base, chid),
 665                          subc, mthd, data);
 666         }
 667
 668         nv_wr32(priv, 0x0400c0 + (unit * 0x2000), 0x80600008);
 669         nv_wr32(priv, 0x040108 + (unit * 0x2000), stat);
 670 }
 671
 672 static void
 673 nvc0_fifo_intr_runlist(struct nvc0_fifo_priv *priv)
 674 {
 675         u32 intr = nv_rd32(priv, 0x002a00);
 676
 677         if (intr & 0x10000000) {
 678                 wake_up(&priv->runlist.wait);
 679                 nv_wr32(priv, 0x002a00, 0x10000000);
 680                 intr &= ~0x10000000;
 681         }
 682
 683         if (intr) {
 684                 nv_error(priv, "RUNLIST 0x%08x\n", intr);
 685                 nv_wr32(priv, 0x002a00, intr);
 686         }
 687 }
 688
 689 static void
 690 nvc0_fifo_intr_engine_unit(struct nvc0_fifo_priv *priv, int engn)
 691 {
 692         u32 intr = nv_rd32(priv, 0x0025a8 + (engn * 0x04));
 693         u32 inte = nv_rd32(priv, 0x002628);
 694         u32 unkn;
 695
 696         for (unkn = 0; unkn < 8; unkn++) {
 697                 u32 ints = (intr >> (unkn * 0x04)) & inte;
 698                 if (ints & 0x1) {
 699                         nouveau_event_trigger(priv->base.uevent, 0);
 700                         ints &= ~1;
 701                 }
 702                 if (ints) {
 703                         nv_error(priv, "ENGINE %d %d %01x", engn, unkn, ints);
 704                         nv_mask(priv, 0x002628, ints, 0);
 705                 }
 706         }
 707
 708         nv_wr32(priv, 0x0025a8 + (engn * 0x04), intr);
 709 }
 710
 711 static void
 712 nvc0_fifo_intr_engine(struct nvc0_fifo_priv *priv)
 713 {
 714         u32 mask = nv_rd32(priv, 0x0025a4);
 715         while (mask) {
 716                 u32 unit = __ffs(mask);
 717                 nvc0_fifo_intr_engine_unit(priv, unit);
 718                 mask &= ~(1 << unit);
 719         }
 720 }
 721
 722 static void
 723 nvc0_fifo_intr(struct nouveau_subdev *subdev)
 724 {
 725         struct nvc0_fifo_priv *priv = (void *)subdev;
 726         u32 mask = nv_rd32(priv, 0x002140);
 727         u32 stat = nv_rd32(priv, 0x002100) & mask;
 728
 729         if (stat & 0x00000001) {
 730                 u32 intr = nv_rd32(priv, 0x00252c);
 731                 nv_warn(priv, "INTR 0x00000001: 0x%08x\n", intr);
 732                 nv_wr32(priv, 0x002100, 0x00000001);
 733                 stat &= ~0x00000001;
 734         }
 735
 736         if (stat & 0x00000100) {
 737                 nvc0_fifo_intr_sched(priv);
 738                 nv_wr32(priv, 0x002100, 0x00000100);
 739                 stat &= ~0x00000100;
 740         }
 741
 742         if (stat & 0x00010000) {
 743                 u32 intr = nv_rd32(priv, 0x00256c);
 744                 nv_warn(priv, "INTR 0x00010000: 0x%08x\n", intr);
 745                 nv_wr32(priv, 0x002100, 0x00010000);
 746                 stat &= ~0x00010000;
 747         }
 748
 749         if (stat & 0x01000000) {
 750                 u32 intr = nv_rd32(priv, 0x00258c);
 751                 nv_warn(priv, "INTR 0x01000000: 0x%08x\n", intr);
 752                 nv_wr32(priv, 0x002100, 0x01000000);
 753                 stat &= ~0x01000000;
 754         }
 755
 756         if (stat & 0x10000000) {
 757                 u32 mask = nv_rd32(priv, 0x00259c);
 758                 while (mask) {
 759                         u32 unit = __ffs(mask);
 760                         nvc0_fifo_intr_fault(priv, unit);
 761                         nv_wr32(priv, 0x00259c, (1 << unit));
 762                         mask &= ~(1 << unit);
 763                 }
 764                 stat &= ~0x10000000;
 765         }
 766
 767         if (stat & 0x20000000) {
 768                 u32 mask = nv_rd32(priv, 0x0025a0);
 769                 while (mask) {
 770                         u32 unit = __ffs(mask);
 771                         nvc0_fifo_intr_pbdma(priv, unit);
 772                         nv_wr32(priv, 0x0025a0, (1 << unit));
 773                         mask &= ~(1 << unit);
 774                 }
 775                 stat &= ~0x20000000;
 776         }
 777
 778         if (stat & 0x40000000) {
 779                 nvc0_fifo_intr_runlist(priv);
 780                 stat &= ~0x40000000;
 781         }
 782
 783         if (stat & 0x80000000) {
 784                 nvc0_fifo_intr_engine(priv);
 785                 stat &= ~0x80000000;
 786         }
 787
 788         if (stat) {
 789                 nv_error(priv, "INTR 0x%08x\n", stat);
 790                 nv_mask(priv, 0x002140, stat, 0x00000000);
 791                 nv_wr32(priv, 0x002100, stat);
 792         }
 793 }
 794
 795 static void
 796 nvc0_fifo_uevent_enable(struct nouveau_event *event, int index)
 797 {
 798         struct nvc0_fifo_priv *priv = event->priv;
 799         nv_mask(priv, 0x002140, 0x80000000, 0x80000000);
 800 }
 801
 802 static void
 803 nvc0_fifo_uevent_disable(struct nouveau_event *event, int index)
 804 {
 805         struct nvc0_fifo_priv *priv = event->priv;
 806         nv_mask(priv, 0x002140, 0x80000000, 0x00000000);
 807 }
 808
 809 static int
 810 nvc0_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 811                struct nouveau_oclass *oclass, void *data, u32 size,
 812                struct nouveau_object **pobject)
 813 {
 814         struct nvc0_fifo_priv *priv;
 815         int ret;
 816
 817         ret = nouveau_fifo_create(parent, engine, oclass, 0, 127, &priv);
 818         *pobject = nv_object(priv);
 819         if (ret)
 820                 return ret;
 821
 822         INIT_WORK(&priv->fault, nvc0_fifo_recover_work);
 823
 824         ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 0x1000, 0,
 825                                 &priv->runlist.mem[0]);
 826         if (ret)
 827                 return ret;
 828
 829         ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 0x1000, 0,
 830                                 &priv->runlist.mem[1]);
 831         if (ret)
 832                 return ret;
 833
 834         init_waitqueue_head(&priv->runlist.wait);
 835
 836         ret = nouveau_gpuobj_new(nv_object(priv), NULL, 128 * 0x1000, 0x1000, 0,
 837                                 &priv->user.mem);
 838         if (ret)
 839                 return ret;
 840
 841         ret = nouveau_gpuobj_map(priv->user.mem, NV_MEM_ACCESS_RW,
 842                                 &priv->user.bar);
 843         if (ret)
 844                 return ret;
 845
 846         priv->base.uevent->enable = nvc0_fifo_uevent_enable;
 847         priv->base.uevent->disable = nvc0_fifo_uevent_disable;
 848         priv->base.uevent->priv = priv;
 849
 850         nv_subdev(priv)->unit = 0x00000100;
 851         nv_subdev(priv)->intr = nvc0_fifo_intr;
 852         nv_engine(priv)->cclass = &nvc0_fifo_cclass;
 853         nv_engine(priv)->sclass = nvc0_fifo_sclass;
 854         return 0;
 855 }
 856
 857 static void
 858 nvc0_fifo_dtor(struct nouveau_object *object)
 859 {
 860         struct nvc0_fifo_priv *priv = (void *)object;
 861
 862         nouveau_gpuobj_unmap(&priv->user.bar);
 863         nouveau_gpuobj_ref(NULL, &priv->user.mem);
 864         nouveau_gpuobj_ref(NULL, &priv->runlist.mem[0]);
 865         nouveau_gpuobj_ref(NULL, &priv->runlist.mem[1]);
 866
 867         nouveau_fifo_destroy(&priv->base);
 868 }
 869
 870 static int
 871 nvc0_fifo_init(struct nouveau_object *object)
 872 {
 873         struct nvc0_fifo_priv *priv = (void *)object;
 874         int ret, i;
 875
 876         ret = nouveau_fifo_init(&priv->base);
 877         if (ret)
 878                 return ret;
 879
 880         nv_wr32(priv, 0x000204, 0xffffffff);
 881         nv_wr32(priv, 0x002204, 0xffffffff);
 882
 883         priv->spoon_nr = hweight32(nv_rd32(priv, 0x002204));
 884         nv_debug(priv, "%d PBDMA unit(s)\n", priv->spoon_nr);
 885
 886         /* assign engines to PBDMAs */
 887         if (priv->spoon_nr >= 3) {
 888                 nv_wr32(priv, 0x002208, ~(1 << 0)); /* PGRAPH */
 889                 nv_wr32(priv, 0x00220c, ~(1 << 1)); /* PVP */
 890                 nv_wr32(priv, 0x002210, ~(1 << 1)); /* PPP */
 891                 nv_wr32(priv, 0x002214, ~(1 << 1)); /* PBSP */
 892                 nv_wr32(priv, 0x002218, ~(1 << 2)); /* PCE0 */
 893                 nv_wr32(priv, 0x00221c, ~(1 << 1)); /* PCE1 */
 894         }
 895
 896         /* PBDMA[n] */
 897         for (i = 0; i < priv->spoon_nr; i++) {
 898                 nv_mask(priv, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000);
 899                 nv_wr32(priv, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */
 900                 nv_wr32(priv, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTREN */
 901         }
 902
 903         nv_mask(priv, 0x002200, 0x00000001, 0x00000001);
 904         nv_wr32(priv, 0x002254, 0x10000000 | priv->user.bar.offset >> 12);
 905
 906         nv_wr32(priv, 0x002100, 0xffffffff);
 907         nv_wr32(priv, 0x002140, 0x7fffffff);
 908         nv_wr32(priv, 0x002628, 0x00000001); /* ENGINE_INTR_EN */
 909         return 0;
 910 }
 911
 912 struct nouveau_oclass *
 913 nvc0_fifo_oclass = &(struct nouveau_oclass) {
 914         .handle = NV_ENGINE(FIFO, 0xc0),
 915         .ofuncs = &(struct nouveau_ofuncs) {
 916                 .ctor = nvc0_fifo_ctor,
 917                 .dtor = nvc0_fifo_dtor,
 918                 .init = nvc0_fifo_init,
 919                 .fini = _nouveau_fifo_fini,
 920         },
 921 };