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[karo-tx-linux.git] / drivers / gpu / drm / nouveau / core / engine / fifo / nve0.c
1 /*
2  * Copyright 2012 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Ben Skeggs
23  */
24
25 #include <core/client.h>
26 #include <core/handle.h>
27 #include <core/namedb.h>
28 #include <core/gpuobj.h>
29 #include <core/engctx.h>
30 #include <core/event.h>
31 #include <core/class.h>
32 #include <core/enum.h>
33
34 #include <subdev/timer.h>
35 #include <subdev/bar.h>
36 #include <subdev/fb.h>
37 #include <subdev/vm.h>
38
39 #include <engine/dmaobj.h>
40
41 #include "nve0.h"
42
43 #define _(a,b) { (a), ((1ULL << (a)) | (b)) }
44 static const struct {
45         u64 subdev;
46         u64 mask;
47 } fifo_engine[] = {
48         _(NVDEV_ENGINE_GR      , (1ULL << NVDEV_ENGINE_SW) |
49                                  (1ULL << NVDEV_ENGINE_COPY2)),
50         _(NVDEV_ENGINE_VP      , 0),
51         _(NVDEV_ENGINE_PPP     , 0),
52         _(NVDEV_ENGINE_BSP     , 0),
53         _(NVDEV_ENGINE_COPY0   , 0),
54         _(NVDEV_ENGINE_COPY1   , 0),
55         _(NVDEV_ENGINE_VENC    , 0),
56 };
57 #undef _
58 #define FIFO_ENGINE_NR ARRAY_SIZE(fifo_engine)
59
60 struct nve0_fifo_engn {
61         struct nouveau_gpuobj *runlist[2];
62         int cur_runlist;
63         wait_queue_head_t wait;
64 };
65
66 struct nve0_fifo_priv {
67         struct nouveau_fifo base;
68         struct nve0_fifo_engn engine[FIFO_ENGINE_NR];
69         struct {
70                 struct nouveau_gpuobj *mem;
71                 struct nouveau_vma bar;
72         } user;
73         int spoon_nr;
74 };
75
76 struct nve0_fifo_base {
77         struct nouveau_fifo_base base;
78         struct nouveau_gpuobj *pgd;
79         struct nouveau_vm *vm;
80 };
81
82 struct nve0_fifo_chan {
83         struct nouveau_fifo_chan base;
84         u32 engine;
85         enum {
86                 STOPPED,
87                 RUNNING,
88                 KILLED
89         } state;
90 };
91
92 /*******************************************************************************
93  * FIFO channel objects
94  ******************************************************************************/
95
96 static void
97 nve0_fifo_runlist_update(struct nve0_fifo_priv *priv, u32 engine)
98 {
99         struct nouveau_bar *bar = nouveau_bar(priv);
100         struct nve0_fifo_engn *engn = &priv->engine[engine];
101         struct nouveau_gpuobj *cur;
102         int i, p;
103
104         mutex_lock(&nv_subdev(priv)->mutex);
105         cur = engn->runlist[engn->cur_runlist];
106         engn->cur_runlist = !engn->cur_runlist;
107
108         for (i = 0, p = 0; i < priv->base.max; i++) {
109                 struct nve0_fifo_chan *chan = (void *)priv->base.channel[i];
110                 if (chan && chan->state == RUNNING && chan->engine == engine) {
111                         nv_wo32(cur, p + 0, i);
112                         nv_wo32(cur, p + 4, 0x00000000);
113                         p += 8;
114                 }
115         }
116         bar->flush(bar);
117
118         nv_wr32(priv, 0x002270, cur->addr >> 12);
119         nv_wr32(priv, 0x002274, (engine << 20) | (p >> 3));
120
121         if (wait_event_timeout(engn->wait, !(nv_rd32(priv, 0x002284 +
122                                (engine * 0x08)) & 0x00100000),
123                                 msecs_to_jiffies(2000)) == 0)
124                 nv_error(priv, "runlist %d update timeout\n", engine);
125         mutex_unlock(&nv_subdev(priv)->mutex);
126 }
127
128 static int
129 nve0_fifo_context_attach(struct nouveau_object *parent,
130                          struct nouveau_object *object)
131 {
132         struct nouveau_bar *bar = nouveau_bar(parent);
133         struct nve0_fifo_base *base = (void *)parent->parent;
134         struct nouveau_engctx *ectx = (void *)object;
135         u32 addr;
136         int ret;
137
138         switch (nv_engidx(object->engine)) {
139         case NVDEV_ENGINE_SW   :
140                 return 0;
141         case NVDEV_ENGINE_COPY0:
142         case NVDEV_ENGINE_COPY1:
143         case NVDEV_ENGINE_COPY2:
144                 nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12;
145                 return 0;
146         case NVDEV_ENGINE_GR   : addr = 0x0210; break;
147         case NVDEV_ENGINE_BSP  : addr = 0x0270; break;
148         case NVDEV_ENGINE_VP   : addr = 0x0250; break;
149         case NVDEV_ENGINE_PPP  : addr = 0x0260; break;
150         default:
151                 return -EINVAL;
152         }
153
154         if (!ectx->vma.node) {
155                 ret = nouveau_gpuobj_map_vm(nv_gpuobj(ectx), base->vm,
156                                             NV_MEM_ACCESS_RW, &ectx->vma);
157                 if (ret)
158                         return ret;
159
160                 nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12;
161         }
162
163         nv_wo32(base, addr + 0x00, lower_32_bits(ectx->vma.offset) | 4);
164         nv_wo32(base, addr + 0x04, upper_32_bits(ectx->vma.offset));
165         bar->flush(bar);
166         return 0;
167 }
168
169 static int
170 nve0_fifo_context_detach(struct nouveau_object *parent, bool suspend,
171                          struct nouveau_object *object)
172 {
173         struct nouveau_bar *bar = nouveau_bar(parent);
174         struct nve0_fifo_priv *priv = (void *)parent->engine;
175         struct nve0_fifo_base *base = (void *)parent->parent;
176         struct nve0_fifo_chan *chan = (void *)parent;
177         u32 addr;
178
179         switch (nv_engidx(object->engine)) {
180         case NVDEV_ENGINE_SW   : return 0;
181         case NVDEV_ENGINE_COPY0:
182         case NVDEV_ENGINE_COPY1:
183         case NVDEV_ENGINE_COPY2: addr = 0x0000; break;
184         case NVDEV_ENGINE_GR   : addr = 0x0210; break;
185         case NVDEV_ENGINE_BSP  : addr = 0x0270; break;
186         case NVDEV_ENGINE_VP   : addr = 0x0250; break;
187         case NVDEV_ENGINE_PPP  : addr = 0x0260; break;
188         default:
189                 return -EINVAL;
190         }
191
192         nv_wr32(priv, 0x002634, chan->base.chid);
193         if (!nv_wait(priv, 0x002634, 0xffffffff, chan->base.chid)) {
194                 nv_error(priv, "channel %d [%s] kick timeout\n",
195                          chan->base.chid, nouveau_client_name(chan));
196                 if (suspend)
197                         return -EBUSY;
198         }
199
200         if (addr) {
201                 nv_wo32(base, addr + 0x00, 0x00000000);
202                 nv_wo32(base, addr + 0x04, 0x00000000);
203                 bar->flush(bar);
204         }
205
206         return 0;
207 }
208
209 static int
210 nve0_fifo_chan_ctor(struct nouveau_object *parent,
211                     struct nouveau_object *engine,
212                     struct nouveau_oclass *oclass, void *data, u32 size,
213                     struct nouveau_object **pobject)
214 {
215         struct nouveau_bar *bar = nouveau_bar(parent);
216         struct nve0_fifo_priv *priv = (void *)engine;
217         struct nve0_fifo_base *base = (void *)parent;
218         struct nve0_fifo_chan *chan;
219         struct nve0_channel_ind_class *args = data;
220         u64 usermem, ioffset, ilength;
221         int ret, i;
222
223         if (size < sizeof(*args))
224                 return -EINVAL;
225
226         for (i = 0; i < FIFO_ENGINE_NR; i++) {
227                 if (args->engine & (1 << i)) {
228                         if (nouveau_engine(parent, fifo_engine[i].subdev)) {
229                                 args->engine = (1 << i);
230                                 break;
231                         }
232                 }
233         }
234
235         if (i == FIFO_ENGINE_NR) {
236                 nv_error(priv, "unsupported engines 0x%08x\n", args->engine);
237                 return -ENODEV;
238         }
239
240         ret = nouveau_fifo_channel_create(parent, engine, oclass, 1,
241                                           priv->user.bar.offset, 0x200,
242                                           args->pushbuf,
243                                           fifo_engine[i].mask, &chan);
244         *pobject = nv_object(chan);
245         if (ret)
246                 return ret;
247
248         nv_parent(chan)->context_attach = nve0_fifo_context_attach;
249         nv_parent(chan)->context_detach = nve0_fifo_context_detach;
250         chan->engine = i;
251
252         usermem = chan->base.chid * 0x200;
253         ioffset = args->ioffset;
254         ilength = order_base_2(args->ilength / 8);
255
256         for (i = 0; i < 0x200; i += 4)
257                 nv_wo32(priv->user.mem, usermem + i, 0x00000000);
258
259         nv_wo32(base, 0x08, lower_32_bits(priv->user.mem->addr + usermem));
260         nv_wo32(base, 0x0c, upper_32_bits(priv->user.mem->addr + usermem));
261         nv_wo32(base, 0x10, 0x0000face);
262         nv_wo32(base, 0x30, 0xfffff902);
263         nv_wo32(base, 0x48, lower_32_bits(ioffset));
264         nv_wo32(base, 0x4c, upper_32_bits(ioffset) | (ilength << 16));
265         nv_wo32(base, 0x84, 0x20400000);
266         nv_wo32(base, 0x94, 0x30000001);
267         nv_wo32(base, 0x9c, 0x00000100);
268         nv_wo32(base, 0xac, 0x0000001f);
269         nv_wo32(base, 0xe8, chan->base.chid);
270         nv_wo32(base, 0xb8, 0xf8000000);
271         nv_wo32(base, 0xf8, 0x10003080); /* 0x002310 */
272         nv_wo32(base, 0xfc, 0x10000010); /* 0x002350 */
273         bar->flush(bar);
274         return 0;
275 }
276
277 static int
278 nve0_fifo_chan_init(struct nouveau_object *object)
279 {
280         struct nouveau_gpuobj *base = nv_gpuobj(object->parent);
281         struct nve0_fifo_priv *priv = (void *)object->engine;
282         struct nve0_fifo_chan *chan = (void *)object;
283         u32 chid = chan->base.chid;
284         int ret;
285
286         ret = nouveau_fifo_channel_init(&chan->base);
287         if (ret)
288                 return ret;
289
290         nv_mask(priv, 0x800004 + (chid * 8), 0x000f0000, chan->engine << 16);
291         nv_wr32(priv, 0x800000 + (chid * 8), 0x80000000 | base->addr >> 12);
292
293         if (chan->state == STOPPED && (chan->state = RUNNING) == RUNNING) {
294                 nv_mask(priv, 0x800004 + (chid * 8), 0x00000400, 0x00000400);
295                 nve0_fifo_runlist_update(priv, chan->engine);
296                 nv_mask(priv, 0x800004 + (chid * 8), 0x00000400, 0x00000400);
297         }
298
299         return 0;
300 }
301
302 static int
303 nve0_fifo_chan_fini(struct nouveau_object *object, bool suspend)
304 {
305         struct nve0_fifo_priv *priv = (void *)object->engine;
306         struct nve0_fifo_chan *chan = (void *)object;
307         u32 chid = chan->base.chid;
308
309         if (chan->state == RUNNING && (chan->state = STOPPED) == STOPPED) {
310                 nv_mask(priv, 0x800004 + (chid * 8), 0x00000800, 0x00000800);
311                 nve0_fifo_runlist_update(priv, chan->engine);
312         }
313
314         nv_wr32(priv, 0x800000 + (chid * 8), 0x00000000);
315         return nouveau_fifo_channel_fini(&chan->base, suspend);
316 }
317
318 static struct nouveau_ofuncs
319 nve0_fifo_ofuncs = {
320         .ctor = nve0_fifo_chan_ctor,
321         .dtor = _nouveau_fifo_channel_dtor,
322         .init = nve0_fifo_chan_init,
323         .fini = nve0_fifo_chan_fini,
324         .rd32 = _nouveau_fifo_channel_rd32,
325         .wr32 = _nouveau_fifo_channel_wr32,
326 };
327
328 static struct nouveau_oclass
329 nve0_fifo_sclass[] = {
330         { NVE0_CHANNEL_IND_CLASS, &nve0_fifo_ofuncs },
331         {}
332 };
333
334 /*******************************************************************************
335  * FIFO context - instmem heap and vm setup
336  ******************************************************************************/
337
338 static int
339 nve0_fifo_context_ctor(struct nouveau_object *parent,
340                     struct nouveau_object *engine,
341                     struct nouveau_oclass *oclass, void *data, u32 size,
342                     struct nouveau_object **pobject)
343 {
344         struct nve0_fifo_base *base;
345         int ret;
346
347         ret = nouveau_fifo_context_create(parent, engine, oclass, NULL, 0x1000,
348                                           0x1000, NVOBJ_FLAG_ZERO_ALLOC, &base);
349         *pobject = nv_object(base);
350         if (ret)
351                 return ret;
352
353         ret = nouveau_gpuobj_new(nv_object(base), NULL, 0x10000, 0x1000, 0,
354                                 &base->pgd);
355         if (ret)
356                 return ret;
357
358         nv_wo32(base, 0x0200, lower_32_bits(base->pgd->addr));
359         nv_wo32(base, 0x0204, upper_32_bits(base->pgd->addr));
360         nv_wo32(base, 0x0208, 0xffffffff);
361         nv_wo32(base, 0x020c, 0x000000ff);
362
363         ret = nouveau_vm_ref(nouveau_client(parent)->vm, &base->vm, base->pgd);
364         if (ret)
365                 return ret;
366
367         return 0;
368 }
369
370 static void
371 nve0_fifo_context_dtor(struct nouveau_object *object)
372 {
373         struct nve0_fifo_base *base = (void *)object;
374         nouveau_vm_ref(NULL, &base->vm, base->pgd);
375         nouveau_gpuobj_ref(NULL, &base->pgd);
376         nouveau_fifo_context_destroy(&base->base);
377 }
378
379 static struct nouveau_oclass
380 nve0_fifo_cclass = {
381         .handle = NV_ENGCTX(FIFO, 0xe0),
382         .ofuncs = &(struct nouveau_ofuncs) {
383                 .ctor = nve0_fifo_context_ctor,
384                 .dtor = nve0_fifo_context_dtor,
385                 .init = _nouveau_fifo_context_init,
386                 .fini = _nouveau_fifo_context_fini,
387                 .rd32 = _nouveau_fifo_context_rd32,
388                 .wr32 = _nouveau_fifo_context_wr32,
389         },
390 };
391
392 /*******************************************************************************
393  * PFIFO engine
394  ******************************************************************************/
395
396 static int
397 nve0_fifo_swmthd(struct nve0_fifo_priv *priv, u32 chid, u32 mthd, u32 data)
398 {
399         struct nve0_fifo_chan *chan = NULL;
400         struct nouveau_handle *bind;
401         unsigned long flags;
402         int ret = -EINVAL;
403
404         spin_lock_irqsave(&priv->base.lock, flags);
405         if (likely(chid >= priv->base.min && chid <= priv->base.max))
406                 chan = (void *)priv->base.channel[chid];
407         if (unlikely(!chan))
408                 goto out;
409
410         bind = nouveau_namedb_get_class(nv_namedb(chan), 0x906e);
411         if (likely(bind)) {
412                 if (!mthd || !nv_call(bind->object, mthd, data))
413                         ret = 0;
414                 nouveau_namedb_put(bind);
415         }
416
417 out:
418         spin_unlock_irqrestore(&priv->base.lock, flags);
419         return ret;
420 }
421
422 static const struct nouveau_enum
423 nve0_fifo_sched_reason[] = {
424         { 0x0a, "CTXSW_TIMEOUT" },
425         {}
426 };
427
428 static void
429 nve0_fifo_intr_sched(struct nve0_fifo_priv *priv)
430 {
431         u32 intr = nv_rd32(priv, 0x00254c);
432         u32 code = intr & 0x000000ff;
433         const struct nouveau_enum *en;
434         char enunk[6] = "";
435
436         en = nouveau_enum_find(nve0_fifo_sched_reason, code);
437         if (!en)
438                 snprintf(enunk, sizeof(enunk), "UNK%02x", code);
439
440         nv_error(priv, "SCHED_ERROR [ %s ]\n", en ? en->name : enunk);
441 }
442
443 static void
444 nve0_fifo_intr_chsw(struct nve0_fifo_priv *priv)
445 {
446         u32 stat = nv_rd32(priv, 0x00256c);
447         nv_error(priv, "CHSW_ERROR 0x%08x\n", stat);
448         nv_wr32(priv, 0x00256c, stat);
449 }
450
451 static void
452 nve0_fifo_intr_dropped_fault(struct nve0_fifo_priv *priv)
453 {
454         u32 stat = nv_rd32(priv, 0x00259c);
455         nv_error(priv, "DROPPED_MMU_FAULT 0x%08x\n", stat);
456 }
457
458 static const struct nouveau_enum
459 nve0_fifo_fault_engine[] = {
460         { 0x00, "GR", NULL, NVDEV_ENGINE_GR },
461         { 0x03, "IFB", NULL, NVDEV_ENGINE_IFB },
462         { 0x04, "BAR1", NULL, NVDEV_SUBDEV_BAR },
463         { 0x05, "BAR3", NULL, NVDEV_SUBDEV_INSTMEM },
464         { 0x07, "PBDMA0", NULL, NVDEV_ENGINE_FIFO },
465         { 0x08, "PBDMA1", NULL, NVDEV_ENGINE_FIFO },
466         { 0x09, "PBDMA2", NULL, NVDEV_ENGINE_FIFO },
467         { 0x10, "MSVLD", NULL, NVDEV_ENGINE_BSP },
468         { 0x11, "MSPPP", NULL, NVDEV_ENGINE_PPP },
469         { 0x13, "PERF" },
470         { 0x14, "MSPDEC", NULL, NVDEV_ENGINE_VP },
471         { 0x15, "CE0", NULL, NVDEV_ENGINE_COPY0 },
472         { 0x16, "CE1", NULL, NVDEV_ENGINE_COPY1 },
473         { 0x17, "PMU" },
474         { 0x19, "MSENC", NULL, NVDEV_ENGINE_VENC },
475         { 0x1b, "CE2", NULL, NVDEV_ENGINE_COPY2 },
476         {}
477 };
478
479 static const struct nouveau_enum
480 nve0_fifo_fault_reason[] = {
481         { 0x00, "PDE" },
482         { 0x01, "PDE_SIZE" },
483         { 0x02, "PTE" },
484         { 0x03, "VA_LIMIT_VIOLATION" },
485         { 0x04, "UNBOUND_INST_BLOCK" },
486         { 0x05, "PRIV_VIOLATION" },
487         { 0x06, "RO_VIOLATION" },
488         { 0x07, "WO_VIOLATION" },
489         { 0x08, "PITCH_MASK_VIOLATION" },
490         { 0x09, "WORK_CREATION" },
491         { 0x0a, "UNSUPPORTED_APERTURE" },
492         { 0x0b, "COMPRESSION_FAILURE" },
493         { 0x0c, "UNSUPPORTED_KIND" },
494         { 0x0d, "REGION_VIOLATION" },
495         { 0x0e, "BOTH_PTES_VALID" },
496         { 0x0f, "INFO_TYPE_POISONED" },
497         {}
498 };
499
500 static const struct nouveau_enum
501 nve0_fifo_fault_hubclient[] = {
502         { 0x00, "VIP" },
503         { 0x01, "CE0" },
504         { 0x02, "CE1" },
505         { 0x03, "DNISO" },
506         { 0x04, "FE" },
507         { 0x05, "FECS" },
508         { 0x06, "HOST" },
509         { 0x07, "HOST_CPU" },
510         { 0x08, "HOST_CPU_NB" },
511         { 0x09, "ISO" },
512         { 0x0a, "MMU" },
513         { 0x0b, "MSPDEC" },
514         { 0x0c, "MSPPP" },
515         { 0x0d, "MSVLD" },
516         { 0x0e, "NISO" },
517         { 0x0f, "P2P" },
518         { 0x10, "PD" },
519         { 0x11, "PERF" },
520         { 0x12, "PMU" },
521         { 0x13, "RASTERTWOD" },
522         { 0x14, "SCC" },
523         { 0x15, "SCC_NB" },
524         { 0x16, "SEC" },
525         { 0x17, "SSYNC" },
526         { 0x18, "GR_COPY" },
527         { 0x19, "CE2" },
528         { 0x1a, "XV" },
529         { 0x1b, "MMU_NB" },
530         { 0x1c, "MSENC" },
531         { 0x1d, "DFALCON" },
532         { 0x1e, "SKED" },
533         { 0x1f, "AFALCON" },
534         {}
535 };
536
537 static const struct nouveau_enum
538 nve0_fifo_fault_gpcclient[] = {
539         { 0x00, "L1_0" }, { 0x01, "T1_0" }, { 0x02, "PE_0" },
540         { 0x03, "L1_1" }, { 0x04, "T1_1" }, { 0x05, "PE_1" },
541         { 0x06, "L1_2" }, { 0x07, "T1_2" }, { 0x08, "PE_2" },
542         { 0x09, "L1_3" }, { 0x0a, "T1_3" }, { 0x0b, "PE_3" },
543         { 0x0c, "RAST" },
544         { 0x0d, "GCC" },
545         { 0x0e, "GPCCS" },
546         { 0x0f, "PROP_0" },
547         { 0x10, "PROP_1" },
548         { 0x11, "PROP_2" },
549         { 0x12, "PROP_3" },
550         { 0x13, "L1_4" }, { 0x14, "T1_4" }, { 0x15, "PE_4" },
551         { 0x16, "L1_5" }, { 0x17, "T1_5" }, { 0x18, "PE_5" },
552         { 0x19, "L1_6" }, { 0x1a, "T1_6" }, { 0x1b, "PE_6" },
553         { 0x1c, "L1_7" }, { 0x1d, "T1_7" }, { 0x1e, "PE_7" },
554         { 0x1f, "GPM" },
555         { 0x20, "LTP_UTLB_0" },
556         { 0x21, "LTP_UTLB_1" },
557         { 0x22, "LTP_UTLB_2" },
558         { 0x23, "LTP_UTLB_3" },
559         { 0x24, "GPC_RGG_UTLB" },
560         {}
561 };
562
563 static void
564 nve0_fifo_intr_fault(struct nve0_fifo_priv *priv, int unit)
565 {
566         u32 inst = nv_rd32(priv, 0x002800 + (unit * 0x10));
567         u32 valo = nv_rd32(priv, 0x002804 + (unit * 0x10));
568         u32 vahi = nv_rd32(priv, 0x002808 + (unit * 0x10));
569         u32 stat = nv_rd32(priv, 0x00280c + (unit * 0x10));
570         u32 gpc    = (stat & 0x1f000000) >> 24;
571         u32 client = (stat & 0x00001f00) >> 8;
572         u32 write  = (stat & 0x00000080);
573         u32 hub    = (stat & 0x00000040);
574         u32 reason = (stat & 0x0000000f);
575         struct nouveau_object *engctx = NULL;
576         struct nouveau_engine *engine;
577         const struct nouveau_enum *er, *eu, *ec;
578         char erunk[6] = "";
579         char euunk[6] = "";
580         char ecunk[6] = "";
581         char gpcid[3] = "";
582
583         er = nouveau_enum_find(nve0_fifo_fault_reason, reason);
584         if (!er)
585                 snprintf(erunk, sizeof(erunk), "UNK%02X", reason);
586
587         eu = nouveau_enum_find(nve0_fifo_fault_engine, unit);
588         if (eu) {
589                 switch (eu->data2) {
590                 case NVDEV_SUBDEV_BAR:
591                         nv_mask(priv, 0x001704, 0x00000000, 0x00000000);
592                         break;
593                 case NVDEV_SUBDEV_INSTMEM:
594                         nv_mask(priv, 0x001714, 0x00000000, 0x00000000);
595                         break;
596                 case NVDEV_ENGINE_IFB:
597                         nv_mask(priv, 0x001718, 0x00000000, 0x00000000);
598                         break;
599                 default:
600                         engine = nouveau_engine(priv, eu->data2);
601                         if (engine)
602                                 engctx = nouveau_engctx_get(engine, inst);
603                         break;
604                 }
605         } else {
606                 snprintf(euunk, sizeof(euunk), "UNK%02x", unit);
607         }
608
609         if (hub) {
610                 ec = nouveau_enum_find(nve0_fifo_fault_hubclient, client);
611         } else {
612                 ec = nouveau_enum_find(nve0_fifo_fault_gpcclient, client);
613                 snprintf(gpcid, sizeof(gpcid), "%d", gpc);
614         }
615
616         if (!ec)
617                 snprintf(ecunk, sizeof(ecunk), "UNK%02x", client);
618
619         nv_error(priv, "%s fault at 0x%010llx [%s] from %s/%s%s%s%s on "
620                        "channel 0x%010llx [%s]\n", write ? "write" : "read",
621                  (u64)vahi << 32 | valo, er ? er->name : erunk,
622                  eu ? eu->name : euunk, hub ? "" : "GPC", gpcid, hub ? "" : "/",
623                  ec ? ec->name : ecunk, (u64)inst << 12,
624                  nouveau_client_name(engctx));
625
626         nouveau_engctx_put(engctx);
627 }
628
629 static const struct nouveau_bitfield nve0_fifo_pbdma_intr[] = {
630         { 0x00000001, "MEMREQ" },
631         { 0x00000002, "MEMACK_TIMEOUT" },
632         { 0x00000004, "MEMACK_EXTRA" },
633         { 0x00000008, "MEMDAT_TIMEOUT" },
634         { 0x00000010, "MEMDAT_EXTRA" },
635         { 0x00000020, "MEMFLUSH" },
636         { 0x00000040, "MEMOP" },
637         { 0x00000080, "LBCONNECT" },
638         { 0x00000100, "LBREQ" },
639         { 0x00000200, "LBACK_TIMEOUT" },
640         { 0x00000400, "LBACK_EXTRA" },
641         { 0x00000800, "LBDAT_TIMEOUT" },
642         { 0x00001000, "LBDAT_EXTRA" },
643         { 0x00002000, "GPFIFO" },
644         { 0x00004000, "GPPTR" },
645         { 0x00008000, "GPENTRY" },
646         { 0x00010000, "GPCRC" },
647         { 0x00020000, "PBPTR" },
648         { 0x00040000, "PBENTRY" },
649         { 0x00080000, "PBCRC" },
650         { 0x00100000, "XBARCONNECT" },
651         { 0x00200000, "METHOD" },
652         { 0x00400000, "METHODCRC" },
653         { 0x00800000, "DEVICE" },
654         { 0x02000000, "SEMAPHORE" },
655         { 0x04000000, "ACQUIRE" },
656         { 0x08000000, "PRI" },
657         { 0x20000000, "NO_CTXSW_SEG" },
658         { 0x40000000, "PBSEG" },
659         { 0x80000000, "SIGNATURE" },
660         {}
661 };
662
663 static void
664 nve0_fifo_intr_pbdma(struct nve0_fifo_priv *priv, int unit)
665 {
666         u32 stat = nv_rd32(priv, 0x040108 + (unit * 0x2000));
667         u32 addr = nv_rd32(priv, 0x0400c0 + (unit * 0x2000));
668         u32 data = nv_rd32(priv, 0x0400c4 + (unit * 0x2000));
669         u32 chid = nv_rd32(priv, 0x040120 + (unit * 0x2000)) & 0xfff;
670         u32 subc = (addr & 0x00070000) >> 16;
671         u32 mthd = (addr & 0x00003ffc);
672         u32 show = stat;
673
674         if (stat & 0x00800000) {
675                 if (!nve0_fifo_swmthd(priv, chid, mthd, data))
676                         show &= ~0x00800000;
677         }
678
679         if (show) {
680                 nv_error(priv, "PBDMA%d:", unit);
681                 nouveau_bitfield_print(nve0_fifo_pbdma_intr, show);
682                 pr_cont("\n");
683                 nv_error(priv,
684                          "PBDMA%d: ch %d [%s] subc %d mthd 0x%04x data 0x%08x\n",
685                          unit, chid,
686                          nouveau_client_name_for_fifo_chid(&priv->base, chid),
687                          subc, mthd, data);
688         }
689
690         nv_wr32(priv, 0x0400c0 + (unit * 0x2000), 0x80600008);
691         nv_wr32(priv, 0x040108 + (unit * 0x2000), stat);
692 }
693
694 static void
695 nve0_fifo_intr_runlist(struct nve0_fifo_priv *priv)
696 {
697         u32 mask = nv_rd32(priv, 0x002a00);
698         while (mask) {
699                 u32 engn = __ffs(mask);
700                 wake_up(&priv->engine[engn].wait);
701                 nv_wr32(priv, 0x002a00, 1 << engn);
702                 mask &= ~(1 << engn);
703         }
704 }
705
706 static void
707 nve0_fifo_intr_engine(struct nve0_fifo_priv *priv)
708 {
709         nouveau_event_trigger(priv->base.uevent, 0);
710 }
711
712 static void
713 nve0_fifo_intr(struct nouveau_subdev *subdev)
714 {
715         struct nve0_fifo_priv *priv = (void *)subdev;
716         u32 mask = nv_rd32(priv, 0x002140);
717         u32 stat = nv_rd32(priv, 0x002100) & mask;
718
719         if (stat & 0x00000001) {
720                 u32 stat = nv_rd32(priv, 0x00252c);
721                 nv_error(priv, "BIND_ERROR 0x%08x\n", stat);
722                 nv_wr32(priv, 0x002100, 0x00000001);
723                 stat &= ~0x00000001;
724         }
725
726         if (stat & 0x00000010) {
727                 nv_error(priv, "PIO_ERROR\n");
728                 nv_wr32(priv, 0x002100, 0x00000010);
729                 stat &= ~0x00000010;
730         }
731
732         if (stat & 0x00000100) {
733                 nve0_fifo_intr_sched(priv);
734                 nv_wr32(priv, 0x002100, 0x00000100);
735                 stat &= ~0x00000100;
736         }
737
738         if (stat & 0x00010000) {
739                 nve0_fifo_intr_chsw(priv);
740                 nv_wr32(priv, 0x002100, 0x00010000);
741                 stat &= ~0x00010000;
742         }
743
744         if (stat & 0x00800000) {
745                 nv_error(priv, "FB_FLUSH_TIMEOUT\n");
746                 nv_wr32(priv, 0x002100, 0x00800000);
747                 stat &= ~0x00800000;
748         }
749
750         if (stat & 0x01000000) {
751                 nv_error(priv, "LB_ERROR\n");
752                 nv_wr32(priv, 0x002100, 0x01000000);
753                 stat &= ~0x01000000;
754         }
755
756         if (stat & 0x08000000) {
757                 nve0_fifo_intr_dropped_fault(priv);
758                 nv_wr32(priv, 0x002100, 0x08000000);
759                 stat &= ~0x08000000;
760         }
761
762         if (stat & 0x10000000) {
763                 u32 mask = nv_rd32(priv, 0x00259c);
764                 while (mask) {
765                         u32 unit = __ffs(mask);
766                         nve0_fifo_intr_fault(priv, unit);
767                         nv_wr32(priv, 0x00259c, (1 << unit));
768                         mask &= ~(1 << unit);
769                 }
770                 stat &= ~0x10000000;
771         }
772
773         if (stat & 0x20000000) {
774                 u32 mask = nv_rd32(priv, 0x0025a0);
775                 while (mask) {
776                         u32 unit = __ffs(mask);
777                         nve0_fifo_intr_pbdma(priv, unit);
778                         nv_wr32(priv, 0x0025a0, (1 << unit));
779                         mask &= ~(1 << unit);
780                 }
781                 stat &= ~0x20000000;
782         }
783
784         if (stat & 0x40000000) {
785                 nve0_fifo_intr_runlist(priv);
786                 stat &= ~0x40000000;
787         }
788
789         if (stat & 0x80000000) {
790                 nve0_fifo_intr_engine(priv);
791                 nv_wr32(priv, 0x002100, 0x80000000);
792                 stat &= ~0x80000000;
793         }
794
795         if (stat) {
796                 nv_error(priv, "INTR 0x%08x\n", stat);
797                 nv_mask(priv, 0x002140, stat, 0x00000000);
798                 nv_wr32(priv, 0x002100, stat);
799         }
800 }
801
802 static void
803 nve0_fifo_uevent_enable(struct nouveau_event *event, int index)
804 {
805         struct nve0_fifo_priv *priv = event->priv;
806         nv_mask(priv, 0x002140, 0x80000000, 0x80000000);
807 }
808
809 static void
810 nve0_fifo_uevent_disable(struct nouveau_event *event, int index)
811 {
812         struct nve0_fifo_priv *priv = event->priv;
813         nv_mask(priv, 0x002140, 0x80000000, 0x00000000);
814 }
815
816 int
817 nve0_fifo_fini(struct nouveau_object *object, bool suspend)
818 {
819         struct nve0_fifo_priv *priv = (void *)object;
820         int ret;
821
822         ret = nouveau_fifo_fini(&priv->base, suspend);
823         if (ret)
824                 return ret;
825
826         /* allow mmu fault interrupts, even when we're not using fifo */
827         nv_mask(priv, 0x002140, 0x10000000, 0x10000000);
828         return 0;
829 }
830
831 int
832 nve0_fifo_init(struct nouveau_object *object)
833 {
834         struct nve0_fifo_priv *priv = (void *)object;
835         int ret, i;
836
837         ret = nouveau_fifo_init(&priv->base);
838         if (ret)
839                 return ret;
840
841         /* enable all available PBDMA units */
842         nv_wr32(priv, 0x000204, 0xffffffff);
843         priv->spoon_nr = hweight32(nv_rd32(priv, 0x000204));
844         nv_debug(priv, "%d PBDMA unit(s)\n", priv->spoon_nr);
845
846         /* PBDMA[n] */
847         for (i = 0; i < priv->spoon_nr; i++) {
848                 nv_mask(priv, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000);
849                 nv_wr32(priv, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */
850                 nv_wr32(priv, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTREN */
851         }
852
853         nv_wr32(priv, 0x002254, 0x10000000 | priv->user.bar.offset >> 12);
854
855         nv_wr32(priv, 0x002100, 0xffffffff);
856         nv_wr32(priv, 0x002140, 0x7fffffff);
857         return 0;
858 }
859
860 void
861 nve0_fifo_dtor(struct nouveau_object *object)
862 {
863         struct nve0_fifo_priv *priv = (void *)object;
864         int i;
865
866         nouveau_gpuobj_unmap(&priv->user.bar);
867         nouveau_gpuobj_ref(NULL, &priv->user.mem);
868
869         for (i = 0; i < FIFO_ENGINE_NR; i++) {
870                 nouveau_gpuobj_ref(NULL, &priv->engine[i].runlist[1]);
871                 nouveau_gpuobj_ref(NULL, &priv->engine[i].runlist[0]);
872         }
873
874         nouveau_fifo_destroy(&priv->base);
875 }
876
877 int
878 nve0_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
879                struct nouveau_oclass *oclass, void *data, u32 size,
880                struct nouveau_object **pobject)
881 {
882         struct nve0_fifo_impl *impl = (void *)oclass;
883         struct nve0_fifo_priv *priv;
884         int ret, i;
885
886         ret = nouveau_fifo_create(parent, engine, oclass, 0,
887                                   impl->channels - 1, &priv);
888         *pobject = nv_object(priv);
889         if (ret)
890                 return ret;
891
892         for (i = 0; i < FIFO_ENGINE_NR; i++) {
893                 ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x8000, 0x1000,
894                                          0, &priv->engine[i].runlist[0]);
895                 if (ret)
896                         return ret;
897
898                 ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x8000, 0x1000,
899                                          0, &priv->engine[i].runlist[1]);
900                 if (ret)
901                         return ret;
902
903                 init_waitqueue_head(&priv->engine[i].wait);
904         }
905
906         ret = nouveau_gpuobj_new(nv_object(priv), NULL, impl->channels * 0x200,
907                                 0x1000, NVOBJ_FLAG_ZERO_ALLOC, &priv->user.mem);
908         if (ret)
909                 return ret;
910
911         ret = nouveau_gpuobj_map(priv->user.mem, NV_MEM_ACCESS_RW,
912                                 &priv->user.bar);
913         if (ret)
914                 return ret;
915
916         priv->base.uevent->enable = nve0_fifo_uevent_enable;
917         priv->base.uevent->disable = nve0_fifo_uevent_disable;
918         priv->base.uevent->priv = priv;
919
920         nv_subdev(priv)->unit = 0x00000100;
921         nv_subdev(priv)->intr = nve0_fifo_intr;
922         nv_engine(priv)->cclass = &nve0_fifo_cclass;
923         nv_engine(priv)->sclass = nve0_fifo_sclass;
924         return 0;
925 }
926
927 struct nouveau_oclass *
928 nve0_fifo_oclass = &(struct nve0_fifo_impl) {
929         .base.handle = NV_ENGINE(FIFO, 0xe0),
930         .base.ofuncs = &(struct nouveau_ofuncs) {
931                 .ctor = nve0_fifo_ctor,
932                 .dtor = nve0_fifo_dtor,
933                 .init = nve0_fifo_init,
934                 .fini = nve0_fifo_fini,
935         },
936         .channels = 4096,
937 }.base;