1 #include <core/engine.h>
2 #include <core/device.h>
4 #include <subdev/bios.h>
5 #include <subdev/bios/bmp.h>
6 #include <subdev/bios/bit.h>
7 #include <subdev/bios/conn.h>
8 #include <subdev/bios/dcb.h>
9 #include <subdev/bios/dp.h>
10 #include <subdev/bios/gpio.h>
11 #include <subdev/bios/init.h>
12 #include <subdev/bios/ramcfg.h>
13 #include <subdev/devinit.h>
14 #include <subdev/i2c.h>
15 #include <subdev/vga.h>
16 #include <subdev/gpio.h>
18 #define bioslog(lvl, fmt, args...) do { \
19 nv_printk(init->bios, lvl, "0x%04x[%c]: "fmt, init->offset, \
20 init_exec(init) ? '0' + (init->nested - 1) : ' ', ##args); \
22 #define cont(fmt, args...) do { \
23 if (nv_subdev(init->bios)->debug >= NV_DBG_TRACE) \
24 printk(fmt, ##args); \
26 #define trace(fmt, args...) bioslog(TRACE, fmt, ##args)
27 #define warn(fmt, args...) bioslog(WARN, fmt, ##args)
28 #define error(fmt, args...) bioslog(ERROR, fmt, ##args)
30 /******************************************************************************
31 * init parser control flow helpers
32 *****************************************************************************/
35 init_exec(struct nvbios_init *init)
37 return (init->execute == 1) || ((init->execute & 5) == 5);
41 init_exec_set(struct nvbios_init *init, bool exec)
43 if (exec) init->execute &= 0xfd;
44 else init->execute |= 0x02;
48 init_exec_inv(struct nvbios_init *init)
50 init->execute ^= 0x02;
54 init_exec_force(struct nvbios_init *init, bool exec)
56 if (exec) init->execute |= 0x04;
57 else init->execute &= 0xfb;
60 /******************************************************************************
61 * init parser wrappers for normal register/i2c/whatever accessors
62 *****************************************************************************/
65 init_or(struct nvbios_init *init)
67 if (init_exec(init)) {
69 return ffs(init->outp->or) - 1;
70 error("script needs OR!!\n");
76 init_link(struct nvbios_init *init)
78 if (init_exec(init)) {
80 return !(init->outp->sorconf.link & 1);
81 error("script needs OR link\n");
87 init_crtc(struct nvbios_init *init)
89 if (init_exec(init)) {
92 error("script needs crtc\n");
98 init_conn(struct nvbios_init *init)
100 struct nouveau_bios *bios = init->bios;
104 if (init_exec(init)) {
106 conn = init->outp->connector;
107 conn = dcb_conn(bios, conn, &ver, &len);
109 return nv_ro08(bios, conn);
112 error("script needs connector type\n");
119 init_nvreg(struct nvbios_init *init, u32 reg)
121 struct nouveau_devinit *devinit = nouveau_devinit(init->bios);
123 /* C51 (at least) sometimes has the lower bits set which the VBIOS
124 * interprets to mean that access needs to go through certain IO
125 * ports instead. The NVIDIA binary driver has been seen to access
126 * these through the NV register address, so lets assume we can
131 /* GF8+ display scripts need register addresses mangled a bit to
132 * select a specific CRTC/OR
134 if (nv_device(init->bios)->card_type >= NV_50) {
135 if (reg & 0x80000000) {
136 reg += init_crtc(init) * 0x800;
140 if (reg & 0x40000000) {
141 reg += init_or(init) * 0x800;
143 if (reg & 0x20000000) {
144 reg += init_link(init) * 0x80;
150 if (reg & ~0x00fffffc)
151 warn("unknown bits in register 0x%08x\n", reg);
154 reg = devinit->mmio(devinit, reg);
159 init_rd32(struct nvbios_init *init, u32 reg)
161 reg = init_nvreg(init, reg);
162 if (reg != ~0 && init_exec(init))
163 return nv_rd32(init->subdev, reg);
168 init_wr32(struct nvbios_init *init, u32 reg, u32 val)
170 reg = init_nvreg(init, reg);
171 if (reg != ~0 && init_exec(init))
172 nv_wr32(init->subdev, reg, val);
176 init_mask(struct nvbios_init *init, u32 reg, u32 mask, u32 val)
178 reg = init_nvreg(init, reg);
179 if (reg != ~0 && init_exec(init)) {
180 u32 tmp = nv_rd32(init->subdev, reg);
181 nv_wr32(init->subdev, reg, (tmp & ~mask) | val);
188 init_rdport(struct nvbios_init *init, u16 port)
191 return nv_rdport(init->subdev, init->crtc, port);
196 init_wrport(struct nvbios_init *init, u16 port, u8 value)
199 nv_wrport(init->subdev, init->crtc, port, value);
203 init_rdvgai(struct nvbios_init *init, u16 port, u8 index)
205 struct nouveau_subdev *subdev = init->subdev;
206 if (init_exec(init)) {
207 int head = init->crtc < 0 ? 0 : init->crtc;
208 return nv_rdvgai(subdev, head, port, index);
214 init_wrvgai(struct nvbios_init *init, u16 port, u8 index, u8 value)
216 /* force head 0 for updates to cr44, it only exists on first head */
217 if (nv_device(init->subdev)->card_type < NV_50) {
218 if (port == 0x03d4 && index == 0x44)
222 if (init_exec(init)) {
223 int head = init->crtc < 0 ? 0 : init->crtc;
224 nv_wrvgai(init->subdev, head, port, index, value);
227 /* select head 1 if cr44 write selected it */
228 if (nv_device(init->subdev)->card_type < NV_50) {
229 if (port == 0x03d4 && index == 0x44 && value == 3)
234 static struct nouveau_i2c_port *
235 init_i2c(struct nvbios_init *init, int index)
237 struct nouveau_i2c *i2c = nouveau_i2c(init->bios);
240 index = NV_I2C_DEFAULT(0);
241 if (init->outp && init->outp->i2c_upper_default)
242 index = NV_I2C_DEFAULT(1);
247 error("script needs output for i2c\n");
251 if (index == -2 && init->outp->location) {
252 index = NV_I2C_TYPE_EXTAUX(init->outp->extdev);
253 return i2c->find_type(i2c, index);
256 index = init->outp->i2c_index;
259 return i2c->find(i2c, index);
263 init_rdi2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg)
265 struct nouveau_i2c_port *port = init_i2c(init, index);
266 if (port && init_exec(init))
267 return nv_rdi2cr(port, addr, reg);
272 init_wri2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg, u8 val)
274 struct nouveau_i2c_port *port = init_i2c(init, index);
275 if (port && init_exec(init))
276 return nv_wri2cr(port, addr, reg, val);
281 init_rdauxr(struct nvbios_init *init, u32 addr)
283 struct nouveau_i2c_port *port = init_i2c(init, -2);
286 if (port && init_exec(init)) {
287 int ret = nv_rdaux(port, addr, &data, 1);
297 init_wrauxr(struct nvbios_init *init, u32 addr, u8 data)
299 struct nouveau_i2c_port *port = init_i2c(init, -2);
300 if (port && init_exec(init))
301 return nv_wraux(port, addr, &data, 1);
306 init_prog_pll(struct nvbios_init *init, u32 id, u32 freq)
308 struct nouveau_devinit *devinit = nouveau_devinit(init->bios);
309 if (devinit->pll_set && init_exec(init)) {
310 int ret = devinit->pll_set(devinit, id, freq);
312 warn("failed to prog pll 0x%08x to %dkHz\n", id, freq);
316 /******************************************************************************
317 * parsing of bios structures that are required to execute init tables
318 *****************************************************************************/
321 init_table(struct nouveau_bios *bios, u16 *len)
323 struct bit_entry bit_I;
325 if (!bit_entry(bios, 'I', &bit_I)) {
330 if (bmp_version(bios) >= 0x0510) {
332 return bios->bmp_offset + 75;
339 init_table_(struct nvbios_init *init, u16 offset, const char *name)
341 struct nouveau_bios *bios = init->bios;
342 u16 len, data = init_table(bios, &len);
344 if (len >= offset + 2) {
345 data = nv_ro16(bios, data + offset);
349 warn("%s pointer invalid\n", name);
353 warn("init data too short for %s pointer", name);
357 warn("init data not found\n");
361 #define init_script_table(b) init_table_((b), 0x00, "script table")
362 #define init_macro_index_table(b) init_table_((b), 0x02, "macro index table")
363 #define init_macro_table(b) init_table_((b), 0x04, "macro table")
364 #define init_condition_table(b) init_table_((b), 0x06, "condition table")
365 #define init_io_condition_table(b) init_table_((b), 0x08, "io condition table")
366 #define init_io_flag_condition_table(b) init_table_((b), 0x0a, "io flag conditon table")
367 #define init_function_table(b) init_table_((b), 0x0c, "function table")
368 #define init_xlat_table(b) init_table_((b), 0x10, "xlat table");
371 init_script(struct nouveau_bios *bios, int index)
373 struct nvbios_init init = { .bios = bios };
374 u16 bmp_ver = bmp_version(bios), data;
376 if (bmp_ver && bmp_ver < 0x0510) {
377 if (index > 1 || bmp_ver < 0x0100)
380 data = bios->bmp_offset + (bmp_ver < 0x0200 ? 14 : 18);
381 return nv_ro16(bios, data + (index * 2));
384 data = init_script_table(&init);
386 return nv_ro16(bios, data + (index * 2));
392 init_unknown_script(struct nouveau_bios *bios)
394 u16 len, data = init_table(bios, &len);
395 if (data && len >= 16)
396 return nv_ro16(bios, data + 14);
401 init_ram_restrict_group_count(struct nvbios_init *init)
403 return nvbios_ramcfg_count(init->bios);
407 init_ram_restrict(struct nvbios_init *init)
409 /* This appears to be the behaviour of the VBIOS parser, and *is*
410 * important to cache the NV_PEXTDEV_BOOT0 on later chipsets to
411 * avoid fucking up the memory controller (somehow) by reading it
412 * on every INIT_RAM_RESTRICT_ZM_GROUP opcode.
414 * Preserving the non-caching behaviour on earlier chipsets just
415 * in case *not* re-reading the strap causes similar breakage.
417 if (!init->ramcfg || init->bios->version.major < 0x70)
418 init->ramcfg = 0x80000000 | nvbios_ramcfg_index(init->subdev);
419 return (init->ramcfg & 0x7fffffff);
423 init_xlat_(struct nvbios_init *init, u8 index, u8 offset)
425 struct nouveau_bios *bios = init->bios;
426 u16 table = init_xlat_table(init);
428 u16 data = nv_ro16(bios, table + (index * 2));
430 return nv_ro08(bios, data + offset);
431 warn("xlat table pointer %d invalid\n", index);
436 /******************************************************************************
437 * utility functions used by various init opcode handlers
438 *****************************************************************************/
441 init_condition_met(struct nvbios_init *init, u8 cond)
443 struct nouveau_bios *bios = init->bios;
444 u16 table = init_condition_table(init);
446 u32 reg = nv_ro32(bios, table + (cond * 12) + 0);
447 u32 msk = nv_ro32(bios, table + (cond * 12) + 4);
448 u32 val = nv_ro32(bios, table + (cond * 12) + 8);
449 trace("\t[0x%02x] (R[0x%06x] & 0x%08x) == 0x%08x\n",
450 cond, reg, msk, val);
451 return (init_rd32(init, reg) & msk) == val;
457 init_io_condition_met(struct nvbios_init *init, u8 cond)
459 struct nouveau_bios *bios = init->bios;
460 u16 table = init_io_condition_table(init);
462 u16 port = nv_ro16(bios, table + (cond * 5) + 0);
463 u8 index = nv_ro08(bios, table + (cond * 5) + 2);
464 u8 mask = nv_ro08(bios, table + (cond * 5) + 3);
465 u8 value = nv_ro08(bios, table + (cond * 5) + 4);
466 trace("\t[0x%02x] (0x%04x[0x%02x] & 0x%02x) == 0x%02x\n",
467 cond, port, index, mask, value);
468 return (init_rdvgai(init, port, index) & mask) == value;
474 init_io_flag_condition_met(struct nvbios_init *init, u8 cond)
476 struct nouveau_bios *bios = init->bios;
477 u16 table = init_io_flag_condition_table(init);
479 u16 port = nv_ro16(bios, table + (cond * 9) + 0);
480 u8 index = nv_ro08(bios, table + (cond * 9) + 2);
481 u8 mask = nv_ro08(bios, table + (cond * 9) + 3);
482 u8 shift = nv_ro08(bios, table + (cond * 9) + 4);
483 u16 data = nv_ro16(bios, table + (cond * 9) + 5);
484 u8 dmask = nv_ro08(bios, table + (cond * 9) + 7);
485 u8 value = nv_ro08(bios, table + (cond * 9) + 8);
486 u8 ioval = (init_rdvgai(init, port, index) & mask) >> shift;
487 return (nv_ro08(bios, data + ioval) & dmask) == value;
493 init_shift(u32 data, u8 shift)
496 return data >> shift;
497 return data << (0x100 - shift);
501 init_tmds_reg(struct nvbios_init *init, u8 tmds)
503 /* For mlv < 0x80, it is an index into a table of TMDS base addresses.
504 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by
505 * CR58 for CR57 = 0 to index a table of offsets to the basic
507 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by
508 * CR58 for CR57 = 0 to index a table of offsets to the basic
509 * 0x6808b0 address, and then flip the offset by 8.
512 const int pramdac_offset[13] = {
513 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 };
514 const u32 pramdac_table[4] = {
515 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 };
519 u32 dacoffset = pramdac_offset[init->outp->or];
522 return 0x6808b0 + dacoffset;
526 error("tmds opcodes need dcb\n");
528 if (tmds < ARRAY_SIZE(pramdac_table))
529 return pramdac_table[tmds];
531 error("tmds selector 0x%02x unknown\n", tmds);
537 /******************************************************************************
538 * init opcode handlers
539 *****************************************************************************/
542 * init_reserved - stub for various unknown/unused single-byte opcodes
546 init_reserved(struct nvbios_init *init)
548 u8 opcode = nv_ro08(init->bios, init->offset);
560 trace("RESERVED 0x%02x\t", opcode);
561 for (i = 1; i < length; i++)
562 cont(" 0x%02x", nv_ro08(init->bios, init->offset + i));
564 init->offset += length;
568 * INIT_DONE - opcode 0x71
572 init_done(struct nvbios_init *init)
575 init->offset = 0x0000;
579 * INIT_IO_RESTRICT_PROG - opcode 0x32
583 init_io_restrict_prog(struct nvbios_init *init)
585 struct nouveau_bios *bios = init->bios;
586 u16 port = nv_ro16(bios, init->offset + 1);
587 u8 index = nv_ro08(bios, init->offset + 3);
588 u8 mask = nv_ro08(bios, init->offset + 4);
589 u8 shift = nv_ro08(bios, init->offset + 5);
590 u8 count = nv_ro08(bios, init->offset + 6);
591 u32 reg = nv_ro32(bios, init->offset + 7);
594 trace("IO_RESTRICT_PROG\tR[0x%06x] = "
595 "((0x%04x[0x%02x] & 0x%02x) >> %d) [{\n",
596 reg, port, index, mask, shift);
599 conf = (init_rdvgai(init, port, index) & mask) >> shift;
600 for (i = 0; i < count; i++) {
601 u32 data = nv_ro32(bios, init->offset);
604 trace("\t0x%08x *\n", data);
605 init_wr32(init, reg, data);
607 trace("\t0x%08x\n", data);
616 * INIT_REPEAT - opcode 0x33
620 init_repeat(struct nvbios_init *init)
622 struct nouveau_bios *bios = init->bios;
623 u8 count = nv_ro08(bios, init->offset + 1);
624 u16 repeat = init->repeat;
626 trace("REPEAT\t0x%02x\n", count);
629 init->repeat = init->offset;
630 init->repend = init->offset;
632 init->offset = init->repeat;
635 trace("REPEAT\t0x%02x\n", count);
637 init->offset = init->repend;
638 init->repeat = repeat;
642 * INIT_IO_RESTRICT_PLL - opcode 0x34
646 init_io_restrict_pll(struct nvbios_init *init)
648 struct nouveau_bios *bios = init->bios;
649 u16 port = nv_ro16(bios, init->offset + 1);
650 u8 index = nv_ro08(bios, init->offset + 3);
651 u8 mask = nv_ro08(bios, init->offset + 4);
652 u8 shift = nv_ro08(bios, init->offset + 5);
653 s8 iofc = nv_ro08(bios, init->offset + 6);
654 u8 count = nv_ro08(bios, init->offset + 7);
655 u32 reg = nv_ro32(bios, init->offset + 8);
658 trace("IO_RESTRICT_PLL\tR[0x%06x] =PLL= "
659 "((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) IOFCOND 0x%02x [{\n",
660 reg, port, index, mask, shift, iofc);
663 conf = (init_rdvgai(init, port, index) & mask) >> shift;
664 for (i = 0; i < count; i++) {
665 u32 freq = nv_ro16(bios, init->offset) * 10;
668 trace("\t%dkHz *\n", freq);
669 if (iofc > 0 && init_io_flag_condition_met(init, iofc))
671 init_prog_pll(init, reg, freq);
673 trace("\t%dkHz\n", freq);
682 * INIT_END_REPEAT - opcode 0x36
686 init_end_repeat(struct nvbios_init *init)
688 trace("END_REPEAT\n");
692 init->repend = init->offset;
698 * INIT_COPY - opcode 0x37
702 init_copy(struct nvbios_init *init)
704 struct nouveau_bios *bios = init->bios;
705 u32 reg = nv_ro32(bios, init->offset + 1);
706 u8 shift = nv_ro08(bios, init->offset + 5);
707 u8 smask = nv_ro08(bios, init->offset + 6);
708 u16 port = nv_ro16(bios, init->offset + 7);
709 u8 index = nv_ro08(bios, init->offset + 9);
710 u8 mask = nv_ro08(bios, init->offset + 10);
713 trace("COPY\t0x%04x[0x%02x] &= 0x%02x |= "
714 "((R[0x%06x] %s 0x%02x) & 0x%02x)\n",
715 port, index, mask, reg, (shift & 0x80) ? "<<" : ">>",
716 (shift & 0x80) ? (0x100 - shift) : shift, smask);
719 data = init_rdvgai(init, port, index) & mask;
720 data |= init_shift(init_rd32(init, reg), shift) & smask;
721 init_wrvgai(init, port, index, data);
725 * INIT_NOT - opcode 0x38
729 init_not(struct nvbios_init *init)
737 * INIT_IO_FLAG_CONDITION - opcode 0x39
741 init_io_flag_condition(struct nvbios_init *init)
743 struct nouveau_bios *bios = init->bios;
744 u8 cond = nv_ro08(bios, init->offset + 1);
746 trace("IO_FLAG_CONDITION\t0x%02x\n", cond);
749 if (!init_io_flag_condition_met(init, cond))
750 init_exec_set(init, false);
754 * INIT_DP_CONDITION - opcode 0x3a
758 init_dp_condition(struct nvbios_init *init)
760 struct nouveau_bios *bios = init->bios;
761 struct nvbios_dpout info;
762 u8 cond = nv_ro08(bios, init->offset + 1);
763 u8 unkn = nv_ro08(bios, init->offset + 2);
764 u8 ver, hdr, cnt, len;
767 trace("DP_CONDITION\t0x%02x 0x%02x\n", cond, unkn);
772 if (init_conn(init) != DCB_CONNECTOR_eDP)
773 init_exec_set(init, false);
778 (data = nvbios_dpout_match(bios, DCB_OUTPUT_DP,
779 (init->outp->or << 0) |
780 (init->outp->sorconf.link << 6),
781 &ver, &hdr, &cnt, &len, &info)))
783 if (!(info.flags & cond))
784 init_exec_set(init, false);
789 warn("script needs dp output table data\n");
792 if (!(init_rdauxr(init, 0x0d) & 1))
793 init_exec_set(init, false);
796 warn("unknown dp condition 0x%02x\n", cond);
802 * INIT_IO_MASK_OR - opcode 0x3b
806 init_io_mask_or(struct nvbios_init *init)
808 struct nouveau_bios *bios = init->bios;
809 u8 index = nv_ro08(bios, init->offset + 1);
810 u8 or = init_or(init);
813 trace("IO_MASK_OR\t0x03d4[0x%02x] &= ~(1 << 0x%02x)\n", index, or);
816 data = init_rdvgai(init, 0x03d4, index);
817 init_wrvgai(init, 0x03d4, index, data &= ~(1 << or));
821 * INIT_IO_OR - opcode 0x3c
825 init_io_or(struct nvbios_init *init)
827 struct nouveau_bios *bios = init->bios;
828 u8 index = nv_ro08(bios, init->offset + 1);
829 u8 or = init_or(init);
832 trace("IO_OR\t0x03d4[0x%02x] |= (1 << 0x%02x)\n", index, or);
835 data = init_rdvgai(init, 0x03d4, index);
836 init_wrvgai(init, 0x03d4, index, data | (1 << or));
840 * INIT_INDEX_ADDRESS_LATCHED - opcode 0x49
844 init_idx_addr_latched(struct nvbios_init *init)
846 struct nouveau_bios *bios = init->bios;
847 u32 creg = nv_ro32(bios, init->offset + 1);
848 u32 dreg = nv_ro32(bios, init->offset + 5);
849 u32 mask = nv_ro32(bios, init->offset + 9);
850 u32 data = nv_ro32(bios, init->offset + 13);
851 u8 count = nv_ro08(bios, init->offset + 17);
853 trace("INDEX_ADDRESS_LATCHED\tR[0x%06x] : R[0x%06x]\n", creg, dreg);
854 trace("\tCTRL &= 0x%08x |= 0x%08x\n", mask, data);
858 u8 iaddr = nv_ro08(bios, init->offset + 0);
859 u8 idata = nv_ro08(bios, init->offset + 1);
861 trace("\t[0x%02x] = 0x%02x\n", iaddr, idata);
864 init_wr32(init, dreg, idata);
865 init_mask(init, creg, ~mask, data | iaddr);
870 * INIT_IO_RESTRICT_PLL2 - opcode 0x4a
874 init_io_restrict_pll2(struct nvbios_init *init)
876 struct nouveau_bios *bios = init->bios;
877 u16 port = nv_ro16(bios, init->offset + 1);
878 u8 index = nv_ro08(bios, init->offset + 3);
879 u8 mask = nv_ro08(bios, init->offset + 4);
880 u8 shift = nv_ro08(bios, init->offset + 5);
881 u8 count = nv_ro08(bios, init->offset + 6);
882 u32 reg = nv_ro32(bios, init->offset + 7);
885 trace("IO_RESTRICT_PLL2\t"
886 "R[0x%06x] =PLL= ((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) [{\n",
887 reg, port, index, mask, shift);
890 conf = (init_rdvgai(init, port, index) & mask) >> shift;
891 for (i = 0; i < count; i++) {
892 u32 freq = nv_ro32(bios, init->offset);
894 trace("\t%dkHz *\n", freq);
895 init_prog_pll(init, reg, freq);
897 trace("\t%dkHz\n", freq);
905 * INIT_PLL2 - opcode 0x4b
909 init_pll2(struct nvbios_init *init)
911 struct nouveau_bios *bios = init->bios;
912 u32 reg = nv_ro32(bios, init->offset + 1);
913 u32 freq = nv_ro32(bios, init->offset + 5);
915 trace("PLL2\tR[0x%06x] =PLL= %dkHz\n", reg, freq);
918 init_prog_pll(init, reg, freq);
922 * INIT_I2C_BYTE - opcode 0x4c
926 init_i2c_byte(struct nvbios_init *init)
928 struct nouveau_bios *bios = init->bios;
929 u8 index = nv_ro08(bios, init->offset + 1);
930 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
931 u8 count = nv_ro08(bios, init->offset + 3);
933 trace("I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr);
937 u8 reg = nv_ro08(bios, init->offset + 0);
938 u8 mask = nv_ro08(bios, init->offset + 1);
939 u8 data = nv_ro08(bios, init->offset + 2);
942 trace("\t[0x%02x] &= 0x%02x |= 0x%02x\n", reg, mask, data);
945 val = init_rdi2cr(init, index, addr, reg);
948 init_wri2cr(init, index, addr, reg, (val & mask) | data);
953 * INIT_ZM_I2C_BYTE - opcode 0x4d
957 init_zm_i2c_byte(struct nvbios_init *init)
959 struct nouveau_bios *bios = init->bios;
960 u8 index = nv_ro08(bios, init->offset + 1);
961 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
962 u8 count = nv_ro08(bios, init->offset + 3);
964 trace("ZM_I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr);
968 u8 reg = nv_ro08(bios, init->offset + 0);
969 u8 data = nv_ro08(bios, init->offset + 1);
971 trace("\t[0x%02x] = 0x%02x\n", reg, data);
974 init_wri2cr(init, index, addr, reg, data);
980 * INIT_ZM_I2C - opcode 0x4e
984 init_zm_i2c(struct nvbios_init *init)
986 struct nouveau_bios *bios = init->bios;
987 u8 index = nv_ro08(bios, init->offset + 1);
988 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
989 u8 count = nv_ro08(bios, init->offset + 3);
992 trace("ZM_I2C\tI2C[0x%02x][0x%02x]\n", index, addr);
995 for (i = 0; i < count; i++) {
996 data[i] = nv_ro08(bios, init->offset);
997 trace("\t0x%02x\n", data[i]);
1001 if (init_exec(init)) {
1002 struct nouveau_i2c_port *port = init_i2c(init, index);
1003 struct i2c_msg msg = {
1004 .addr = addr, .flags = 0, .len = count, .buf = data,
1008 if (port && (ret = i2c_transfer(&port->adapter, &msg, 1)) != 1)
1009 warn("i2c wr failed, %d\n", ret);
1014 * INIT_TMDS - opcode 0x4f
1018 init_tmds(struct nvbios_init *init)
1020 struct nouveau_bios *bios = init->bios;
1021 u8 tmds = nv_ro08(bios, init->offset + 1);
1022 u8 addr = nv_ro08(bios, init->offset + 2);
1023 u8 mask = nv_ro08(bios, init->offset + 3);
1024 u8 data = nv_ro08(bios, init->offset + 4);
1025 u32 reg = init_tmds_reg(init, tmds);
1027 trace("TMDS\tT[0x%02x][0x%02x] &= 0x%02x |= 0x%02x\n",
1028 tmds, addr, mask, data);
1034 init_wr32(init, reg + 0, addr | 0x00010000);
1035 init_wr32(init, reg + 4, data | (init_rd32(init, reg + 4) & mask));
1036 init_wr32(init, reg + 0, addr);
1040 * INIT_ZM_TMDS_GROUP - opcode 0x50
1044 init_zm_tmds_group(struct nvbios_init *init)
1046 struct nouveau_bios *bios = init->bios;
1047 u8 tmds = nv_ro08(bios, init->offset + 1);
1048 u8 count = nv_ro08(bios, init->offset + 2);
1049 u32 reg = init_tmds_reg(init, tmds);
1051 trace("TMDS_ZM_GROUP\tT[0x%02x]\n", tmds);
1055 u8 addr = nv_ro08(bios, init->offset + 0);
1056 u8 data = nv_ro08(bios, init->offset + 1);
1058 trace("\t[0x%02x] = 0x%02x\n", addr, data);
1061 init_wr32(init, reg + 4, data);
1062 init_wr32(init, reg + 0, addr);
1067 * INIT_CR_INDEX_ADDRESS_LATCHED - opcode 0x51
1071 init_cr_idx_adr_latch(struct nvbios_init *init)
1073 struct nouveau_bios *bios = init->bios;
1074 u8 addr0 = nv_ro08(bios, init->offset + 1);
1075 u8 addr1 = nv_ro08(bios, init->offset + 2);
1076 u8 base = nv_ro08(bios, init->offset + 3);
1077 u8 count = nv_ro08(bios, init->offset + 4);
1080 trace("CR_INDEX_ADDR C[%02x] C[%02x]\n", addr0, addr1);
1083 save0 = init_rdvgai(init, 0x03d4, addr0);
1085 u8 data = nv_ro08(bios, init->offset);
1087 trace("\t\t[0x%02x] = 0x%02x\n", base, data);
1090 init_wrvgai(init, 0x03d4, addr0, base++);
1091 init_wrvgai(init, 0x03d4, addr1, data);
1093 init_wrvgai(init, 0x03d4, addr0, save0);
1097 * INIT_CR - opcode 0x52
1101 init_cr(struct nvbios_init *init)
1103 struct nouveau_bios *bios = init->bios;
1104 u8 addr = nv_ro08(bios, init->offset + 1);
1105 u8 mask = nv_ro08(bios, init->offset + 2);
1106 u8 data = nv_ro08(bios, init->offset + 3);
1109 trace("CR\t\tC[0x%02x] &= 0x%02x |= 0x%02x\n", addr, mask, data);
1112 val = init_rdvgai(init, 0x03d4, addr) & mask;
1113 init_wrvgai(init, 0x03d4, addr, val | data);
1117 * INIT_ZM_CR - opcode 0x53
1121 init_zm_cr(struct nvbios_init *init)
1123 struct nouveau_bios *bios = init->bios;
1124 u8 addr = nv_ro08(bios, init->offset + 1);
1125 u8 data = nv_ro08(bios, init->offset + 2);
1127 trace("ZM_CR\tC[0x%02x] = 0x%02x\n", addr, data);
1130 init_wrvgai(init, 0x03d4, addr, data);
1134 * INIT_ZM_CR_GROUP - opcode 0x54
1138 init_zm_cr_group(struct nvbios_init *init)
1140 struct nouveau_bios *bios = init->bios;
1141 u8 count = nv_ro08(bios, init->offset + 1);
1143 trace("ZM_CR_GROUP\n");
1147 u8 addr = nv_ro08(bios, init->offset + 0);
1148 u8 data = nv_ro08(bios, init->offset + 1);
1150 trace("\t\tC[0x%02x] = 0x%02x\n", addr, data);
1153 init_wrvgai(init, 0x03d4, addr, data);
1158 * INIT_CONDITION_TIME - opcode 0x56
1162 init_condition_time(struct nvbios_init *init)
1164 struct nouveau_bios *bios = init->bios;
1165 u8 cond = nv_ro08(bios, init->offset + 1);
1166 u8 retry = nv_ro08(bios, init->offset + 2);
1167 u8 wait = min((u16)retry * 50, 100);
1169 trace("CONDITION_TIME\t0x%02x 0x%02x\n", cond, retry);
1172 if (!init_exec(init))
1176 if (init_condition_met(init, cond))
1181 init_exec_set(init, false);
1185 * INIT_LTIME - opcode 0x57
1189 init_ltime(struct nvbios_init *init)
1191 struct nouveau_bios *bios = init->bios;
1192 u16 msec = nv_ro16(bios, init->offset + 1);
1194 trace("LTIME\t0x%04x\n", msec);
1197 if (init_exec(init))
1202 * INIT_ZM_REG_SEQUENCE - opcode 0x58
1206 init_zm_reg_sequence(struct nvbios_init *init)
1208 struct nouveau_bios *bios = init->bios;
1209 u32 base = nv_ro32(bios, init->offset + 1);
1210 u8 count = nv_ro08(bios, init->offset + 5);
1212 trace("ZM_REG_SEQUENCE\t0x%02x\n", count);
1216 u32 data = nv_ro32(bios, init->offset);
1218 trace("\t\tR[0x%06x] = 0x%08x\n", base, data);
1221 init_wr32(init, base, data);
1227 * INIT_SUB_DIRECT - opcode 0x5b
1231 init_sub_direct(struct nvbios_init *init)
1233 struct nouveau_bios *bios = init->bios;
1234 u16 addr = nv_ro16(bios, init->offset + 1);
1237 trace("SUB_DIRECT\t0x%04x\n", addr);
1239 if (init_exec(init)) {
1240 save = init->offset;
1241 init->offset = addr;
1242 if (nvbios_exec(init)) {
1243 error("error parsing sub-table\n");
1246 init->offset = save;
1253 * INIT_JUMP - opcode 0x5c
1257 init_jump(struct nvbios_init *init)
1259 struct nouveau_bios *bios = init->bios;
1260 u16 offset = nv_ro16(bios, init->offset + 1);
1262 trace("JUMP\t0x%04x\n", offset);
1264 if (init_exec(init))
1265 init->offset = offset;
1271 * INIT_I2C_IF - opcode 0x5e
1275 init_i2c_if(struct nvbios_init *init)
1277 struct nouveau_bios *bios = init->bios;
1278 u8 index = nv_ro08(bios, init->offset + 1);
1279 u8 addr = nv_ro08(bios, init->offset + 2);
1280 u8 reg = nv_ro08(bios, init->offset + 3);
1281 u8 mask = nv_ro08(bios, init->offset + 4);
1282 u8 data = nv_ro08(bios, init->offset + 5);
1285 trace("I2C_IF\tI2C[0x%02x][0x%02x][0x%02x] & 0x%02x == 0x%02x\n",
1286 index, addr, reg, mask, data);
1288 init_exec_force(init, true);
1290 value = init_rdi2cr(init, index, addr, reg);
1291 if ((value & mask) != data)
1292 init_exec_set(init, false);
1294 init_exec_force(init, false);
1298 * INIT_COPY_NV_REG - opcode 0x5f
1302 init_copy_nv_reg(struct nvbios_init *init)
1304 struct nouveau_bios *bios = init->bios;
1305 u32 sreg = nv_ro32(bios, init->offset + 1);
1306 u8 shift = nv_ro08(bios, init->offset + 5);
1307 u32 smask = nv_ro32(bios, init->offset + 6);
1308 u32 sxor = nv_ro32(bios, init->offset + 10);
1309 u32 dreg = nv_ro32(bios, init->offset + 14);
1310 u32 dmask = nv_ro32(bios, init->offset + 18);
1313 trace("COPY_NV_REG\tR[0x%06x] &= 0x%08x |= "
1314 "((R[0x%06x] %s 0x%02x) & 0x%08x ^ 0x%08x)\n",
1315 dreg, dmask, sreg, (shift & 0x80) ? "<<" : ">>",
1316 (shift & 0x80) ? (0x100 - shift) : shift, smask, sxor);
1319 data = init_shift(init_rd32(init, sreg), shift);
1320 init_mask(init, dreg, ~dmask, (data & smask) ^ sxor);
1324 * INIT_ZM_INDEX_IO - opcode 0x62
1328 init_zm_index_io(struct nvbios_init *init)
1330 struct nouveau_bios *bios = init->bios;
1331 u16 port = nv_ro16(bios, init->offset + 1);
1332 u8 index = nv_ro08(bios, init->offset + 3);
1333 u8 data = nv_ro08(bios, init->offset + 4);
1335 trace("ZM_INDEX_IO\tI[0x%04x][0x%02x] = 0x%02x\n", port, index, data);
1338 init_wrvgai(init, port, index, data);
1342 * INIT_COMPUTE_MEM - opcode 0x63
1346 init_compute_mem(struct nvbios_init *init)
1348 struct nouveau_devinit *devinit = nouveau_devinit(init->bios);
1350 trace("COMPUTE_MEM\n");
1353 init_exec_force(init, true);
1354 if (init_exec(init) && devinit->meminit)
1355 devinit->meminit(devinit);
1356 init_exec_force(init, false);
1360 * INIT_RESET - opcode 0x65
1364 init_reset(struct nvbios_init *init)
1366 struct nouveau_bios *bios = init->bios;
1367 u32 reg = nv_ro32(bios, init->offset + 1);
1368 u32 data1 = nv_ro32(bios, init->offset + 5);
1369 u32 data2 = nv_ro32(bios, init->offset + 9);
1372 trace("RESET\tR[0x%08x] = 0x%08x, 0x%08x", reg, data1, data2);
1374 init_exec_force(init, true);
1376 savepci19 = init_mask(init, 0x00184c, 0x00000f00, 0x00000000);
1377 init_wr32(init, reg, data1);
1379 init_wr32(init, reg, data2);
1380 init_wr32(init, 0x00184c, savepci19);
1381 init_mask(init, 0x001850, 0x00000001, 0x00000000);
1383 init_exec_force(init, false);
1387 * INIT_CONFIGURE_MEM - opcode 0x66
1391 init_configure_mem_clk(struct nvbios_init *init)
1393 u16 mdata = bmp_mem_init_table(init->bios);
1395 mdata += (init_rdvgai(init, 0x03d4, 0x3c) >> 4) * 66;
1400 init_configure_mem(struct nvbios_init *init)
1402 struct nouveau_bios *bios = init->bios;
1406 trace("CONFIGURE_MEM\n");
1409 if (bios->version.major > 2) {
1413 init_exec_force(init, true);
1415 mdata = init_configure_mem_clk(init);
1416 sdata = bmp_sdr_seq_table(bios);
1417 if (nv_ro08(bios, mdata) & 0x01)
1418 sdata = bmp_ddr_seq_table(bios);
1419 mdata += 6; /* skip to data */
1421 data = init_rdvgai(init, 0x03c4, 0x01);
1422 init_wrvgai(init, 0x03c4, 0x01, data | 0x20);
1424 for (; (addr = nv_ro32(bios, sdata)) != 0xffffffff; sdata += 4) {
1426 case 0x10021c: /* CKE_NORMAL */
1427 case 0x1002d0: /* CMD_REFRESH */
1428 case 0x1002d4: /* CMD_PRECHARGE */
1432 data = nv_ro32(bios, mdata);
1434 if (data == 0xffffffff)
1439 init_wr32(init, addr, data);
1442 init_exec_force(init, false);
1446 * INIT_CONFIGURE_CLK - opcode 0x67
1450 init_configure_clk(struct nvbios_init *init)
1452 struct nouveau_bios *bios = init->bios;
1455 trace("CONFIGURE_CLK\n");
1458 if (bios->version.major > 2) {
1462 init_exec_force(init, true);
1464 mdata = init_configure_mem_clk(init);
1467 clock = nv_ro16(bios, mdata + 4) * 10;
1468 init_prog_pll(init, 0x680500, clock);
1471 clock = nv_ro16(bios, mdata + 2) * 10;
1472 if (nv_ro08(bios, mdata) & 0x01)
1474 init_prog_pll(init, 0x680504, clock);
1476 init_exec_force(init, false);
1480 * INIT_CONFIGURE_PREINIT - opcode 0x68
1484 init_configure_preinit(struct nvbios_init *init)
1486 struct nouveau_bios *bios = init->bios;
1489 trace("CONFIGURE_PREINIT\n");
1492 if (bios->version.major > 2) {
1496 init_exec_force(init, true);
1498 strap = init_rd32(init, 0x101000);
1499 strap = ((strap << 2) & 0xf0) | ((strap & 0x40) >> 6);
1500 init_wrvgai(init, 0x03d4, 0x3c, strap);
1502 init_exec_force(init, false);
1506 * INIT_IO - opcode 0x69
1510 init_io(struct nvbios_init *init)
1512 struct nouveau_bios *bios = init->bios;
1513 u16 port = nv_ro16(bios, init->offset + 1);
1514 u8 mask = nv_ro16(bios, init->offset + 3);
1515 u8 data = nv_ro16(bios, init->offset + 4);
1518 trace("IO\t\tI[0x%04x] &= 0x%02x |= 0x%02x\n", port, mask, data);
1521 /* ummm.. yes.. should really figure out wtf this is and why it's
1522 * needed some day.. it's almost certainly wrong, but, it also
1523 * somehow makes things work...
1525 if (nv_device(init->bios)->card_type >= NV_50 &&
1526 port == 0x03c3 && data == 0x01) {
1527 init_mask(init, 0x614100, 0xf0800000, 0x00800000);
1528 init_mask(init, 0x00e18c, 0x00020000, 0x00020000);
1529 init_mask(init, 0x614900, 0xf0800000, 0x00800000);
1530 init_mask(init, 0x000200, 0x40000000, 0x00000000);
1532 init_mask(init, 0x00e18c, 0x00020000, 0x00000000);
1533 init_mask(init, 0x000200, 0x40000000, 0x40000000);
1534 init_wr32(init, 0x614100, 0x00800018);
1535 init_wr32(init, 0x614900, 0x00800018);
1537 init_wr32(init, 0x614100, 0x10000018);
1538 init_wr32(init, 0x614900, 0x10000018);
1541 value = init_rdport(init, port) & mask;
1542 init_wrport(init, port, data | value);
1546 * INIT_SUB - opcode 0x6b
1550 init_sub(struct nvbios_init *init)
1552 struct nouveau_bios *bios = init->bios;
1553 u8 index = nv_ro08(bios, init->offset + 1);
1556 trace("SUB\t0x%02x\n", index);
1558 addr = init_script(bios, index);
1559 if (addr && init_exec(init)) {
1560 save = init->offset;
1561 init->offset = addr;
1562 if (nvbios_exec(init)) {
1563 error("error parsing sub-table\n");
1566 init->offset = save;
1573 * INIT_RAM_CONDITION - opcode 0x6d
1577 init_ram_condition(struct nvbios_init *init)
1579 struct nouveau_bios *bios = init->bios;
1580 u8 mask = nv_ro08(bios, init->offset + 1);
1581 u8 value = nv_ro08(bios, init->offset + 2);
1583 trace("RAM_CONDITION\t"
1584 "(R[0x100000] & 0x%02x) == 0x%02x\n", mask, value);
1587 if ((init_rd32(init, 0x100000) & mask) != value)
1588 init_exec_set(init, false);
1592 * INIT_NV_REG - opcode 0x6e
1596 init_nv_reg(struct nvbios_init *init)
1598 struct nouveau_bios *bios = init->bios;
1599 u32 reg = nv_ro32(bios, init->offset + 1);
1600 u32 mask = nv_ro32(bios, init->offset + 5);
1601 u32 data = nv_ro32(bios, init->offset + 9);
1603 trace("NV_REG\tR[0x%06x] &= 0x%08x |= 0x%08x\n", reg, mask, data);
1606 init_mask(init, reg, ~mask, data);
1610 * INIT_MACRO - opcode 0x6f
1614 init_macro(struct nvbios_init *init)
1616 struct nouveau_bios *bios = init->bios;
1617 u8 macro = nv_ro08(bios, init->offset + 1);
1620 trace("MACRO\t0x%02x\n", macro);
1622 table = init_macro_table(init);
1624 u32 addr = nv_ro32(bios, table + (macro * 8) + 0);
1625 u32 data = nv_ro32(bios, table + (macro * 8) + 4);
1626 trace("\t\tR[0x%06x] = 0x%08x\n", addr, data);
1627 init_wr32(init, addr, data);
1634 * INIT_RESUME - opcode 0x72
1638 init_resume(struct nvbios_init *init)
1642 init_exec_set(init, true);
1646 * INIT_TIME - opcode 0x74
1650 init_time(struct nvbios_init *init)
1652 struct nouveau_bios *bios = init->bios;
1653 u16 usec = nv_ro16(bios, init->offset + 1);
1655 trace("TIME\t0x%04x\n", usec);
1658 if (init_exec(init)) {
1662 mdelay((usec + 900) / 1000);
1667 * INIT_CONDITION - opcode 0x75
1671 init_condition(struct nvbios_init *init)
1673 struct nouveau_bios *bios = init->bios;
1674 u8 cond = nv_ro08(bios, init->offset + 1);
1676 trace("CONDITION\t0x%02x\n", cond);
1679 if (!init_condition_met(init, cond))
1680 init_exec_set(init, false);
1684 * INIT_IO_CONDITION - opcode 0x76
1688 init_io_condition(struct nvbios_init *init)
1690 struct nouveau_bios *bios = init->bios;
1691 u8 cond = nv_ro08(bios, init->offset + 1);
1693 trace("IO_CONDITION\t0x%02x\n", cond);
1696 if (!init_io_condition_met(init, cond))
1697 init_exec_set(init, false);
1701 * INIT_INDEX_IO - opcode 0x78
1705 init_index_io(struct nvbios_init *init)
1707 struct nouveau_bios *bios = init->bios;
1708 u16 port = nv_ro16(bios, init->offset + 1);
1709 u8 index = nv_ro16(bios, init->offset + 3);
1710 u8 mask = nv_ro08(bios, init->offset + 4);
1711 u8 data = nv_ro08(bios, init->offset + 5);
1714 trace("INDEX_IO\tI[0x%04x][0x%02x] &= 0x%02x |= 0x%02x\n",
1715 port, index, mask, data);
1718 value = init_rdvgai(init, port, index) & mask;
1719 init_wrvgai(init, port, index, data | value);
1723 * INIT_PLL - opcode 0x79
1727 init_pll(struct nvbios_init *init)
1729 struct nouveau_bios *bios = init->bios;
1730 u32 reg = nv_ro32(bios, init->offset + 1);
1731 u32 freq = nv_ro16(bios, init->offset + 5) * 10;
1733 trace("PLL\tR[0x%06x] =PLL= %dkHz\n", reg, freq);
1736 init_prog_pll(init, reg, freq);
1740 * INIT_ZM_REG - opcode 0x7a
1744 init_zm_reg(struct nvbios_init *init)
1746 struct nouveau_bios *bios = init->bios;
1747 u32 addr = nv_ro32(bios, init->offset + 1);
1748 u32 data = nv_ro32(bios, init->offset + 5);
1750 trace("ZM_REG\tR[0x%06x] = 0x%08x\n", addr, data);
1753 if (addr == 0x000200)
1756 init_wr32(init, addr, data);
1760 * INIT_RAM_RESTRICT_PLL - opcde 0x87
1764 init_ram_restrict_pll(struct nvbios_init *init)
1766 struct nouveau_bios *bios = init->bios;
1767 u8 type = nv_ro08(bios, init->offset + 1);
1768 u8 count = init_ram_restrict_group_count(init);
1769 u8 strap = init_ram_restrict(init);
1772 trace("RAM_RESTRICT_PLL\t0x%02x\n", type);
1775 for (cconf = 0; cconf < count; cconf++) {
1776 u32 freq = nv_ro32(bios, init->offset);
1778 if (cconf == strap) {
1779 trace("%dkHz *\n", freq);
1780 init_prog_pll(init, type, freq);
1782 trace("%dkHz\n", freq);
1790 * INIT_GPIO - opcode 0x8e
1794 init_gpio(struct nvbios_init *init)
1796 struct nouveau_gpio *gpio = nouveau_gpio(init->bios);
1801 if (init_exec(init) && gpio && gpio->reset)
1802 gpio->reset(gpio, DCB_GPIO_UNUSED);
1806 * INIT_RAM_RESTRICT_ZM_GROUP - opcode 0x8f
1810 init_ram_restrict_zm_reg_group(struct nvbios_init *init)
1812 struct nouveau_bios *bios = init->bios;
1813 u32 addr = nv_ro32(bios, init->offset + 1);
1814 u8 incr = nv_ro08(bios, init->offset + 5);
1815 u8 num = nv_ro08(bios, init->offset + 6);
1816 u8 count = init_ram_restrict_group_count(init);
1817 u8 index = init_ram_restrict(init);
1820 trace("RAM_RESTRICT_ZM_REG_GROUP\t"
1821 "R[0x%08x] 0x%02x 0x%02x\n", addr, incr, num);
1824 for (i = 0; i < num; i++) {
1825 trace("\tR[0x%06x] = {\n", addr);
1826 for (j = 0; j < count; j++) {
1827 u32 data = nv_ro32(bios, init->offset);
1830 trace("\t\t0x%08x *\n", data);
1831 init_wr32(init, addr, data);
1833 trace("\t\t0x%08x\n", data);
1844 * INIT_COPY_ZM_REG - opcode 0x90
1848 init_copy_zm_reg(struct nvbios_init *init)
1850 struct nouveau_bios *bios = init->bios;
1851 u32 sreg = nv_ro32(bios, init->offset + 1);
1852 u32 dreg = nv_ro32(bios, init->offset + 5);
1854 trace("COPY_ZM_REG\tR[0x%06x] = R[0x%06x]\n", dreg, sreg);
1857 init_wr32(init, dreg, init_rd32(init, sreg));
1861 * INIT_ZM_REG_GROUP - opcode 0x91
1865 init_zm_reg_group(struct nvbios_init *init)
1867 struct nouveau_bios *bios = init->bios;
1868 u32 addr = nv_ro32(bios, init->offset + 1);
1869 u8 count = nv_ro08(bios, init->offset + 5);
1871 trace("ZM_REG_GROUP\tR[0x%06x] =\n", addr);
1875 u32 data = nv_ro32(bios, init->offset);
1876 trace("\t0x%08x\n", data);
1877 init_wr32(init, addr, data);
1883 * INIT_XLAT - opcode 0x96
1887 init_xlat(struct nvbios_init *init)
1889 struct nouveau_bios *bios = init->bios;
1890 u32 saddr = nv_ro32(bios, init->offset + 1);
1891 u8 sshift = nv_ro08(bios, init->offset + 5);
1892 u8 smask = nv_ro08(bios, init->offset + 6);
1893 u8 index = nv_ro08(bios, init->offset + 7);
1894 u32 daddr = nv_ro32(bios, init->offset + 8);
1895 u32 dmask = nv_ro32(bios, init->offset + 12);
1896 u8 shift = nv_ro08(bios, init->offset + 16);
1899 trace("INIT_XLAT\tR[0x%06x] &= 0x%08x |= "
1900 "(X%02x((R[0x%06x] %s 0x%02x) & 0x%02x) << 0x%02x)\n",
1901 daddr, dmask, index, saddr, (sshift & 0x80) ? "<<" : ">>",
1902 (sshift & 0x80) ? (0x100 - sshift) : sshift, smask, shift);
1905 data = init_shift(init_rd32(init, saddr), sshift) & smask;
1906 data = init_xlat_(init, index, data) << shift;
1907 init_mask(init, daddr, ~dmask, data);
1911 * INIT_ZM_MASK_ADD - opcode 0x97
1915 init_zm_mask_add(struct nvbios_init *init)
1917 struct nouveau_bios *bios = init->bios;
1918 u32 addr = nv_ro32(bios, init->offset + 1);
1919 u32 mask = nv_ro32(bios, init->offset + 5);
1920 u32 add = nv_ro32(bios, init->offset + 9);
1923 trace("ZM_MASK_ADD\tR[0x%06x] &= 0x%08x += 0x%08x\n", addr, mask, add);
1926 data = init_rd32(init, addr);
1927 data = (data & mask) | ((data + add) & ~mask);
1928 init_wr32(init, addr, data);
1932 * INIT_AUXCH - opcode 0x98
1936 init_auxch(struct nvbios_init *init)
1938 struct nouveau_bios *bios = init->bios;
1939 u32 addr = nv_ro32(bios, init->offset + 1);
1940 u8 count = nv_ro08(bios, init->offset + 5);
1942 trace("AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count);
1946 u8 mask = nv_ro08(bios, init->offset + 0);
1947 u8 data = nv_ro08(bios, init->offset + 1);
1948 trace("\tAUX[0x%08x] &= 0x%02x |= 0x%02x\n", addr, mask, data);
1949 mask = init_rdauxr(init, addr) & mask;
1950 init_wrauxr(init, addr, mask | data);
1956 * INIT_AUXCH - opcode 0x99
1960 init_zm_auxch(struct nvbios_init *init)
1962 struct nouveau_bios *bios = init->bios;
1963 u32 addr = nv_ro32(bios, init->offset + 1);
1964 u8 count = nv_ro08(bios, init->offset + 5);
1966 trace("ZM_AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count);
1970 u8 data = nv_ro08(bios, init->offset + 0);
1971 trace("\tAUX[0x%08x] = 0x%02x\n", addr, data);
1972 init_wrauxr(init, addr, data);
1978 * INIT_I2C_LONG_IF - opcode 0x9a
1982 init_i2c_long_if(struct nvbios_init *init)
1984 struct nouveau_bios *bios = init->bios;
1985 u8 index = nv_ro08(bios, init->offset + 1);
1986 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
1987 u8 reglo = nv_ro08(bios, init->offset + 3);
1988 u8 reghi = nv_ro08(bios, init->offset + 4);
1989 u8 mask = nv_ro08(bios, init->offset + 5);
1990 u8 data = nv_ro08(bios, init->offset + 6);
1991 struct nouveau_i2c_port *port;
1993 trace("I2C_LONG_IF\t"
1994 "I2C[0x%02x][0x%02x][0x%02x%02x] & 0x%02x == 0x%02x\n",
1995 index, addr, reglo, reghi, mask, data);
1998 port = init_i2c(init, index);
2000 u8 i[2] = { reghi, reglo };
2002 struct i2c_msg msg[] = {
2003 { .addr = addr, .flags = 0, .len = 2, .buf = i },
2004 { .addr = addr, .flags = I2C_M_RD, .len = 1, .buf = o }
2008 ret = i2c_transfer(&port->adapter, msg, 2);
2009 if (ret == 2 && ((o[0] & mask) == data))
2013 init_exec_set(init, false);
2017 * INIT_GPIO_NE - opcode 0xa9
2021 init_gpio_ne(struct nvbios_init *init)
2023 struct nouveau_bios *bios = init->bios;
2024 struct nouveau_gpio *gpio = nouveau_gpio(bios);
2025 struct dcb_gpio_func func;
2026 u8 count = nv_ro08(bios, init->offset + 1);
2027 u8 idx = 0, ver, len;
2033 for (i = init->offset; i < init->offset + count; i++)
2034 cont("0x%02x ", nv_ro08(bios, i));
2037 while ((data = dcb_gpio_parse(bios, 0, idx++, &ver, &len, &func))) {
2038 if (func.func != DCB_GPIO_UNUSED) {
2039 for (i = init->offset; i < init->offset + count; i++) {
2040 if (func.func == nv_ro08(bios, i))
2044 trace("\tFUNC[0x%02x]", func.func);
2045 if (i == (init->offset + count)) {
2047 if (init_exec(init) && gpio && gpio->reset)
2048 gpio->reset(gpio, func.func);
2054 init->offset += count;
2057 static struct nvbios_init_opcode {
2058 void (*exec)(struct nvbios_init *);
2060 [0x32] = { init_io_restrict_prog },
2061 [0x33] = { init_repeat },
2062 [0x34] = { init_io_restrict_pll },
2063 [0x36] = { init_end_repeat },
2064 [0x37] = { init_copy },
2065 [0x38] = { init_not },
2066 [0x39] = { init_io_flag_condition },
2067 [0x3a] = { init_dp_condition },
2068 [0x3b] = { init_io_mask_or },
2069 [0x3c] = { init_io_or },
2070 [0x49] = { init_idx_addr_latched },
2071 [0x4a] = { init_io_restrict_pll2 },
2072 [0x4b] = { init_pll2 },
2073 [0x4c] = { init_i2c_byte },
2074 [0x4d] = { init_zm_i2c_byte },
2075 [0x4e] = { init_zm_i2c },
2076 [0x4f] = { init_tmds },
2077 [0x50] = { init_zm_tmds_group },
2078 [0x51] = { init_cr_idx_adr_latch },
2079 [0x52] = { init_cr },
2080 [0x53] = { init_zm_cr },
2081 [0x54] = { init_zm_cr_group },
2082 [0x56] = { init_condition_time },
2083 [0x57] = { init_ltime },
2084 [0x58] = { init_zm_reg_sequence },
2085 [0x5b] = { init_sub_direct },
2086 [0x5c] = { init_jump },
2087 [0x5e] = { init_i2c_if },
2088 [0x5f] = { init_copy_nv_reg },
2089 [0x62] = { init_zm_index_io },
2090 [0x63] = { init_compute_mem },
2091 [0x65] = { init_reset },
2092 [0x66] = { init_configure_mem },
2093 [0x67] = { init_configure_clk },
2094 [0x68] = { init_configure_preinit },
2095 [0x69] = { init_io },
2096 [0x6b] = { init_sub },
2097 [0x6d] = { init_ram_condition },
2098 [0x6e] = { init_nv_reg },
2099 [0x6f] = { init_macro },
2100 [0x71] = { init_done },
2101 [0x72] = { init_resume },
2102 [0x74] = { init_time },
2103 [0x75] = { init_condition },
2104 [0x76] = { init_io_condition },
2105 [0x78] = { init_index_io },
2106 [0x79] = { init_pll },
2107 [0x7a] = { init_zm_reg },
2108 [0x87] = { init_ram_restrict_pll },
2109 [0x8c] = { init_reserved },
2110 [0x8d] = { init_reserved },
2111 [0x8e] = { init_gpio },
2112 [0x8f] = { init_ram_restrict_zm_reg_group },
2113 [0x90] = { init_copy_zm_reg },
2114 [0x91] = { init_zm_reg_group },
2115 [0x92] = { init_reserved },
2116 [0x96] = { init_xlat },
2117 [0x97] = { init_zm_mask_add },
2118 [0x98] = { init_auxch },
2119 [0x99] = { init_zm_auxch },
2120 [0x9a] = { init_i2c_long_if },
2121 [0xa9] = { init_gpio_ne },
2122 [0xaa] = { init_reserved },
2125 #define init_opcode_nr (sizeof(init_opcode) / sizeof(init_opcode[0]))
2128 nvbios_exec(struct nvbios_init *init)
2131 while (init->offset) {
2132 u8 opcode = nv_ro08(init->bios, init->offset);
2133 if (opcode >= init_opcode_nr || !init_opcode[opcode].exec) {
2134 error("unknown opcode 0x%02x\n", opcode);
2138 init_opcode[opcode].exec(init);
2145 nvbios_init(struct nouveau_subdev *subdev, bool execute)
2147 struct nouveau_bios *bios = nouveau_bios(subdev);
2153 nv_info(bios, "running init tables\n");
2154 while (!ret && (data = (init_script(bios, ++i)))) {
2155 struct nvbios_init init = {
2161 .execute = execute ? 1 : 0,
2164 ret = nvbios_exec(&init);
2167 /* the vbios parser will run this right after the normal init
2168 * tables, whereas the binary driver appears to run it later.
2170 if (!ret && (data = init_unknown_script(bios))) {
2171 struct nvbios_init init = {
2177 .execute = execute ? 1 : 0,
2180 ret = nvbios_exec(&init);