2 * Copyright 2013 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <subdev/bios.h>
26 #include <subdev/bios/bit.h>
27 #include <subdev/bios/pll.h>
28 #include <subdev/bios/perf.h>
29 #include <subdev/bios/timing.h>
30 #include <subdev/clock/pll.h>
31 #include <subdev/fb.h>
33 #include <core/option.h>
42 struct hwsq_reg r_0x002504;
43 struct hwsq_reg r_0x004008;
44 struct hwsq_reg r_0x00400c;
45 struct hwsq_reg r_0x00c040;
46 struct hwsq_reg r_0x100210;
47 struct hwsq_reg r_0x1002d0;
48 struct hwsq_reg r_0x1002d4;
49 struct hwsq_reg r_0x1002dc;
50 struct hwsq_reg r_0x100da0[8];
51 struct hwsq_reg r_0x100e20;
52 struct hwsq_reg r_0x100e24;
53 struct hwsq_reg r_0x611200;
54 struct hwsq_reg r_timing[9];
55 struct hwsq_reg r_mr[4];
59 struct nouveau_ram base;
60 struct nv50_ramseq hwsq;
66 nv50_ram_calc(struct nouveau_fb *pfb, u32 freq)
68 struct nouveau_bios *bios = nouveau_bios(pfb);
69 struct nv50_ram *ram = (void *)pfb->ram;
70 struct nv50_ramseq *hwsq = &ram->hwsq;
71 struct nvbios_perfE perfE;
72 struct nvbios_pll mpll;
77 u8 ver, hdr, cnt, strap;
78 int N1, M1, N2, M2, P;
81 /* lookup closest matching performance table entry for frequency */
84 ramcfg.data = nvbios_perfEp(bios, i++, &ver, &hdr, &cnt,
85 &ramcfg.size, &perfE);
86 if (!ramcfg.data || (ver < 0x25 || ver >= 0x40) ||
88 nv_error(pfb, "invalid/missing perftab entry\n");
91 } while (perfE.memory < freq);
93 /* locate specific data set for the attached memory */
94 strap = nvbios_ramcfg_index(bios);
96 nv_error(pfb, "invalid ramcfg strap\n");
100 ramcfg.data += hdr + (strap * ramcfg.size);
102 /* lookup memory timings, if bios says they're present */
103 strap = nv_ro08(bios, ramcfg.data + 0x01);
105 timing.data = nvbios_timing_entry(bios, strap, &ver, &hdr);
106 if (!timing.data || ver != 0x10 || hdr < 0x12) {
107 nv_error(pfb, "invalid/missing timing entry "
108 "%02x %04x %02x %02x\n",
109 strap, timing.data, ver, hdr);
116 ret = ram_init(hwsq, nv_subdev(pfb));
120 ram_wait(hwsq, 0x01, 0x00); /* wait for !vblank */
121 ram_wait(hwsq, 0x01, 0x01); /* wait for vblank */
122 ram_wr32(hwsq, 0x611200, 0x00003300);
123 ram_wr32(hwsq, 0x002504, 0x00000001); /* block fifo */
124 ram_nsec(hwsq, 8000);
125 ram_setf(hwsq, 0x10, 0x00); /* disable fb */
126 ram_wait(hwsq, 0x00, 0x01); /* wait for fb disabled */
128 ram_wr32(hwsq, 0x1002d4, 0x00000001); /* precharge */
129 ram_wr32(hwsq, 0x1002d0, 0x00000001); /* refresh */
130 ram_wr32(hwsq, 0x1002d0, 0x00000001); /* refresh */
131 ram_wr32(hwsq, 0x100210, 0x00000000); /* disable auto-refresh */
132 ram_wr32(hwsq, 0x1002dc, 0x00000001); /* enable self-refresh */
134 ret = nvbios_pll_parse(bios, 0x004008, &mpll);
135 mpll.vco2.max_freq = 0;
137 ret = nv04_pll_calc(nv_subdev(pfb), &mpll, freq,
138 &N1, &M1, &N2, &M2, &P);
146 ram_mask(hwsq, 0x00c040, 0xc000c000, 0x0000c000);
147 ram_mask(hwsq, 0x004008, 0x00000200, 0x00000200);
148 ram_mask(hwsq, 0x00400c, 0x0000ffff, (N1 << 8) | M1);
149 ram_mask(hwsq, 0x004008, 0x81ff0000, 0x80000000 | (mpll.bias_p << 19) |
150 (P << 22) | (P << 16));
152 for (i = 0; i < 8; i++)
153 ram_mask(hwsq, 0x100da0[i], 0x00000000, 0x00000000); /*XXX*/
155 ram_nsec(hwsq, 96000); /*XXX*/
156 ram_mask(hwsq, 0x004008, 0x00002200, 0x00002000);
158 ram_wr32(hwsq, 0x1002dc, 0x00000000); /* disable self-refresh */
159 ram_wr32(hwsq, 0x100210, 0x80000000); /* enable auto-refresh */
161 ram_nsec(hwsq, 12000);
163 switch (ram->base.type) {
164 case NV_MEM_TYPE_DDR2:
165 ram_nuke(hwsq, mr[0]); /* force update */
166 ram_mask(hwsq, mr[0], 0x000, 0x000);
168 case NV_MEM_TYPE_GDDR3:
169 ram_mask(hwsq, mr[2], 0x000, 0x000);
170 ram_nuke(hwsq, mr[0]); /* force update */
171 ram_mask(hwsq, mr[0], 0x000, 0x000);
177 ram_mask(hwsq, timing[3], 0x00000000, 0x00000000); /*XXX*/
178 ram_mask(hwsq, timing[1], 0x00000000, 0x00000000); /*XXX*/
179 ram_mask(hwsq, timing[6], 0x00000000, 0x00000000); /*XXX*/
180 ram_mask(hwsq, timing[7], 0x00000000, 0x00000000); /*XXX*/
181 ram_mask(hwsq, timing[8], 0x00000000, 0x00000000); /*XXX*/
182 ram_mask(hwsq, timing[0], 0x00000000, 0x00000000); /*XXX*/
183 ram_mask(hwsq, timing[2], 0x00000000, 0x00000000); /*XXX*/
184 ram_mask(hwsq, timing[4], 0x00000000, 0x00000000); /*XXX*/
185 ram_mask(hwsq, timing[5], 0x00000000, 0x00000000); /*XXX*/
187 ram_mask(hwsq, timing[0], 0x00000000, 0x00000000); /*XXX*/
190 ram_nuke(hwsq, 0x100e24);
191 ram_mask(hwsq, 0x100e24, 0x00000000, 0x00000000);
192 ram_nuke(hwsq, 0x100e20);
193 ram_mask(hwsq, 0x100e20, 0x00000000, 0x00000000);
196 ram_mask(hwsq, mr[0], 0x100, 0x100);
197 ram_mask(hwsq, mr[0], 0x100, 0x000);
199 ram_setf(hwsq, 0x10, 0x01); /* enable fb */
200 ram_wait(hwsq, 0x00, 0x00); /* wait for fb enabled */
201 ram_wr32(hwsq, 0x611200, 0x00003330);
202 ram_wr32(hwsq, 0x002504, 0x00000000); /* un-block fifo */
207 nv50_ram_prog(struct nouveau_fb *pfb)
209 struct nouveau_device *device = nv_device(pfb);
210 struct nv50_ram *ram = (void *)pfb->ram;
211 struct nv50_ramseq *hwsq = &ram->hwsq;
213 ram_exec(hwsq, nouveau_boolopt(device->cfgopt, "NvMemExec", false));
218 nv50_ram_tidy(struct nouveau_fb *pfb)
220 struct nv50_ram *ram = (void *)pfb->ram;
221 struct nv50_ramseq *hwsq = &ram->hwsq;
222 ram_exec(hwsq, false);
226 __nv50_ram_put(struct nouveau_fb *pfb, struct nouveau_mem *mem)
228 struct nouveau_mm_node *this;
230 while (!list_empty(&mem->regions)) {
231 this = list_first_entry(&mem->regions, typeof(*this), rl_entry);
233 list_del(&this->rl_entry);
234 nouveau_mm_free(&pfb->vram, &this);
237 nouveau_mm_free(&pfb->tags, &mem->tag);
241 nv50_ram_put(struct nouveau_fb *pfb, struct nouveau_mem **pmem)
243 struct nouveau_mem *mem = *pmem;
246 if (unlikely(mem == NULL))
249 mutex_lock(&pfb->base.mutex);
250 __nv50_ram_put(pfb, mem);
251 mutex_unlock(&pfb->base.mutex);
257 nv50_ram_get(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin,
258 u32 memtype, struct nouveau_mem **pmem)
260 struct nouveau_mm *heap = &pfb->vram;
261 struct nouveau_mm *tags = &pfb->tags;
262 struct nouveau_mm_node *r;
263 struct nouveau_mem *mem;
264 int comp = (memtype & 0x300) >> 8;
265 int type = (memtype & 0x07f);
266 int back = (memtype & 0x800);
270 min = ncmin ? (ncmin >> 12) : max;
273 mem = kzalloc(sizeof(*mem), GFP_KERNEL);
277 mutex_lock(&pfb->base.mutex);
280 int n = (max >> 4) * comp;
282 ret = nouveau_mm_head(tags, 1, n, n, 1, &mem->tag);
287 if (unlikely(!mem->tag))
291 INIT_LIST_HEAD(&mem->regions);
292 mem->memtype = (comp << 7) | type;
295 type = nv50_fb_memtype[type];
298 ret = nouveau_mm_tail(heap, type, max, min, align, &r);
300 ret = nouveau_mm_head(heap, type, max, min, align, &r);
302 mutex_unlock(&pfb->base.mutex);
303 pfb->ram->put(pfb, &mem);
307 list_add_tail(&r->rl_entry, &mem->regions);
310 mutex_unlock(&pfb->base.mutex);
312 r = list_first_entry(&mem->regions, struct nouveau_mm_node, rl_entry);
313 mem->offset = (u64)r->offset << 12;
319 nv50_fb_vram_rblock(struct nouveau_fb *pfb, struct nouveau_ram *ram)
321 int i, parts, colbits, rowbitsa, rowbitsb, banks;
322 u64 rowsize, predicted;
323 u32 r0, r4, rt, ru, rblock_size;
325 r0 = nv_rd32(pfb, 0x100200);
326 r4 = nv_rd32(pfb, 0x100204);
327 rt = nv_rd32(pfb, 0x100250);
328 ru = nv_rd32(pfb, 0x001540);
329 nv_debug(pfb, "memcfg 0x%08x 0x%08x 0x%08x 0x%08x\n", r0, r4, rt, ru);
331 for (i = 0, parts = 0; i < 8; i++) {
332 if (ru & (0x00010000 << i))
336 colbits = (r4 & 0x0000f000) >> 12;
337 rowbitsa = ((r4 & 0x000f0000) >> 16) + 8;
338 rowbitsb = ((r4 & 0x00f00000) >> 20) + 8;
339 banks = 1 << (((r4 & 0x03000000) >> 24) + 2);
341 rowsize = parts * banks * (1 << colbits) * 8;
342 predicted = rowsize << rowbitsa;
344 predicted += rowsize << rowbitsb;
346 if (predicted != ram->size) {
347 nv_warn(pfb, "memory controller reports %d MiB VRAM\n",
348 (u32)(ram->size >> 20));
351 rblock_size = rowsize;
355 nv_debug(pfb, "rblock %d bytes\n", rblock_size);
360 nv50_ram_create_(struct nouveau_object *parent, struct nouveau_object *engine,
361 struct nouveau_oclass *oclass, int length, void **pobject)
363 const u32 rsvd_head = ( 256 * 1024) >> 12; /* vga memory */
364 const u32 rsvd_tail = (1024 * 1024) >> 12; /* vbios etc */
365 struct nouveau_bios *bios = nouveau_bios(parent);
366 struct nouveau_fb *pfb = nouveau_fb(parent);
367 struct nouveau_ram *ram;
370 ret = nouveau_ram_create_(parent, engine, oclass, length, pobject);
375 ram->size = nv_rd32(pfb, 0x10020c);
376 ram->size = (ram->size & 0xffffff00) | ((ram->size & 0x000000ff) << 32);
378 switch (nv_rd32(pfb, 0x100714) & 0x00000007) {
379 case 0: ram->type = NV_MEM_TYPE_DDR1; break;
381 if (nouveau_fb_bios_memtype(bios) == NV_MEM_TYPE_DDR3)
382 ram->type = NV_MEM_TYPE_DDR3;
384 ram->type = NV_MEM_TYPE_DDR2;
386 case 2: ram->type = NV_MEM_TYPE_GDDR3; break;
387 case 3: ram->type = NV_MEM_TYPE_GDDR4; break;
388 case 4: ram->type = NV_MEM_TYPE_GDDR5; break;
393 ret = nouveau_mm_init(&pfb->vram, rsvd_head, (ram->size >> 12) -
394 (rsvd_head + rsvd_tail),
395 nv50_fb_vram_rblock(pfb, ram) >> 12);
399 ram->ranks = (nv_rd32(pfb, 0x100200) & 0x4) ? 2 : 1;
400 ram->tags = nv_rd32(pfb, 0x100320);
401 ram->get = nv50_ram_get;
402 ram->put = nv50_ram_put;
407 nv50_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
408 struct nouveau_oclass *oclass, void *data, u32 datasize,
409 struct nouveau_object **pobject)
411 struct nv50_ram *ram;
414 ret = nv50_ram_create(parent, engine, oclass, &ram);
415 *pobject = nv_object(ram);
419 switch (ram->base.type) {
420 case NV_MEM_TYPE_DDR2:
421 case NV_MEM_TYPE_GDDR3:
422 ram->base.calc = nv50_ram_calc;
423 ram->base.prog = nv50_ram_prog;
424 ram->base.tidy = nv50_ram_tidy;
427 nv_warn(ram, "reclocking of this ram type unsupported\n");
431 ram->hwsq.r_0x002504 = hwsq_reg(0x002504);
432 ram->hwsq.r_0x00c040 = hwsq_reg(0x00c040);
433 ram->hwsq.r_0x004008 = hwsq_reg(0x004008);
434 ram->hwsq.r_0x00400c = hwsq_reg(0x00400c);
435 ram->hwsq.r_0x100210 = hwsq_reg(0x100210);
436 ram->hwsq.r_0x1002d0 = hwsq_reg(0x1002d0);
437 ram->hwsq.r_0x1002d4 = hwsq_reg(0x1002d4);
438 ram->hwsq.r_0x1002dc = hwsq_reg(0x1002dc);
439 for (i = 0; i < 8; i++)
440 ram->hwsq.r_0x100da0[i] = hwsq_reg(0x100da0 + (i * 0x04));
441 ram->hwsq.r_0x100e20 = hwsq_reg(0x100e20);
442 ram->hwsq.r_0x100e24 = hwsq_reg(0x100e24);
443 ram->hwsq.r_0x611200 = hwsq_reg(0x611200);
445 for (i = 0; i < 9; i++)
446 ram->hwsq.r_timing[i] = hwsq_reg(0x100220 + (i * 0x04));
448 if (ram->base.ranks > 1) {
449 ram->hwsq.r_mr[0] = hwsq_reg2(0x1002c0, 0x1002c8);
450 ram->hwsq.r_mr[1] = hwsq_reg2(0x1002c4, 0x1002cc);
451 ram->hwsq.r_mr[2] = hwsq_reg2(0x1002e0, 0x1002e8);
452 ram->hwsq.r_mr[3] = hwsq_reg2(0x1002e4, 0x1002ec);
454 ram->hwsq.r_mr[0] = hwsq_reg(0x1002c0);
455 ram->hwsq.r_mr[1] = hwsq_reg(0x1002c4);
456 ram->hwsq.r_mr[2] = hwsq_reg(0x1002e0);
457 ram->hwsq.r_mr[3] = hwsq_reg(0x1002e4);
463 struct nouveau_oclass
465 .ofuncs = &(struct nouveau_ofuncs) {
466 .ctor = nv50_ram_ctor,
467 .dtor = _nouveau_ram_dtor,
468 .init = _nouveau_ram_init,
469 .fini = _nouveau_ram_fini,