2 * Copyright 2013 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <subdev/bios.h>
26 #include <subdev/bios/bit.h>
27 #include <subdev/bios/pll.h>
28 #include <subdev/bios/rammap.h>
29 #include <subdev/bios/timing.h>
31 #include <subdev/clock/nva3.h>
32 #include <subdev/clock/pll.h>
34 #include <core/option.h>
42 struct ramfuc_reg r_0x004000;
43 struct ramfuc_reg r_0x004004;
44 struct ramfuc_reg r_0x004018;
45 struct ramfuc_reg r_0x004128;
46 struct ramfuc_reg r_0x004168;
47 struct ramfuc_reg r_0x100200;
48 struct ramfuc_reg r_0x100210;
49 struct ramfuc_reg r_0x100220[9];
50 struct ramfuc_reg r_0x1002d0;
51 struct ramfuc_reg r_0x1002d4;
52 struct ramfuc_reg r_0x1002dc;
53 struct ramfuc_reg r_0x10053c;
54 struct ramfuc_reg r_0x1005a0;
55 struct ramfuc_reg r_0x1005a4;
56 struct ramfuc_reg r_0x100714;
57 struct ramfuc_reg r_0x100718;
58 struct ramfuc_reg r_0x10071c;
59 struct ramfuc_reg r_0x100760;
60 struct ramfuc_reg r_0x1007a0;
61 struct ramfuc_reg r_0x1007e0;
62 struct ramfuc_reg r_0x10f804;
63 struct ramfuc_reg r_0x1110e0;
64 struct ramfuc_reg r_0x111100;
65 struct ramfuc_reg r_0x111104;
66 struct ramfuc_reg r_0x611200;
67 struct ramfuc_reg r_mr[4];
71 struct nouveau_ram base;
72 struct nva3_ramfuc fuc;
76 nva3_ram_calc(struct nouveau_fb *pfb, u32 freq)
78 struct nouveau_bios *bios = nouveau_bios(pfb);
79 struct nva3_ram *ram = (void *)pfb->ram;
80 struct nva3_ramfuc *fuc = &ram->fuc;
81 struct nva3_clock_info mclk;
87 } rammap, ramcfg, timing;
88 u32 r004018, r100760, ctrl;
89 u32 unk714, unk718, unk71c;
92 /* lookup memory config data relevant to the target frequency */
93 rammap.data = nvbios_rammap_match(bios, freq / 1000, &ver, &rammap.size,
95 if (!rammap.data || ver != 0x10 || rammap.size < 0x0e) {
96 nv_error(pfb, "invalid/missing rammap entry\n");
100 /* locate specific data set for the attached memory */
101 strap = nvbios_ramcfg_index(bios);
103 nv_error(pfb, "invalid ramcfg strap\n");
107 ramcfg.data = rammap.data + rammap.size + (strap * ramcfg.size);
108 if (!ramcfg.data || ver != 0x10 || ramcfg.size < 0x0e) {
109 nv_error(pfb, "invalid/missing ramcfg entry\n");
113 /* lookup memory timings, if bios says they're present */
114 strap = nv_ro08(bios, ramcfg.data + 0x01);
116 timing.data = nvbios_timing_entry(bios, strap, &ver,
118 if (!timing.data || ver != 0x10 || timing.size < 0x19) {
119 nv_error(pfb, "invalid/missing timing entry\n");
126 ret = nva3_clock_info(nouveau_clock(pfb), 0x12, 0x4000, freq, &mclk);
128 nv_error(pfb, "failed mclk calculation\n");
132 ret = ram_init(fuc, pfb);
136 /* XXX: where the fuck does 750MHz come from? */
137 if (freq <= 750000) {
138 r004018 = 0x10000000;
139 r100760 = 0x22222222;
141 r004018 = 0x00000000;
142 r100760 = 0x00000000;
145 ctrl = ram_rd32(fuc, 0x004000);
146 if (ctrl & 0x00000008) {
148 ram_mask(fuc, 0x004128, 0x00000101, 0x00000101);
149 ram_wr32(fuc, 0x004004, mclk.pll);
150 ram_wr32(fuc, 0x004000, (ctrl |= 0x00000001));
151 ram_wr32(fuc, 0x004000, (ctrl &= 0xffffffef));
152 ram_wait(fuc, 0x004000, 0x00020000, 0x00020000, 64000);
153 ram_wr32(fuc, 0x004000, (ctrl |= 0x00000010));
154 ram_wr32(fuc, 0x004018, 0x00005000 | r004018);
155 ram_wr32(fuc, 0x004000, (ctrl |= 0x00000004));
158 u32 ssel = 0x00000101;
162 ssel |= 0x00080000; /* 324MHz, shouldn't matter... */
163 ram_mask(fuc, 0x004168, 0x003f3141, ctrl);
166 if ( (nv_ro08(bios, ramcfg.data + 0x02) & 0x10)) {
167 ram_mask(fuc, 0x111104, 0x00000600, 0x00000000);
169 ram_mask(fuc, 0x111100, 0x40000000, 0x40000000);
170 ram_mask(fuc, 0x111104, 0x00000180, 0x00000000);
173 if (!(nv_ro08(bios, rammap.data + 0x04) & 0x02))
174 ram_mask(fuc, 0x100200, 0x00000800, 0x00000000);
175 ram_wr32(fuc, 0x611200, 0x00003300);
176 if (!(nv_ro08(bios, ramcfg.data + 0x02) & 0x10))
177 ram_wr32(fuc, 0x111100, 0x4c020000); /*XXX*/
179 ram_wr32(fuc, 0x1002d4, 0x00000001);
180 ram_wr32(fuc, 0x1002d0, 0x00000001);
181 ram_wr32(fuc, 0x1002d0, 0x00000001);
182 ram_wr32(fuc, 0x100210, 0x00000000);
183 ram_wr32(fuc, 0x1002dc, 0x00000001);
186 ctrl = ram_rd32(fuc, 0x004000);
187 if (!(ctrl & 0x00000008) && mclk.pll) {
188 ram_wr32(fuc, 0x004000, (ctrl |= 0x00000008));
189 ram_mask(fuc, 0x1110e0, 0x00088000, 0x00088000);
190 ram_wr32(fuc, 0x004018, 0x00001000);
191 ram_wr32(fuc, 0x004000, (ctrl &= ~0x00000001));
192 ram_wr32(fuc, 0x004004, mclk.pll);
193 ram_wr32(fuc, 0x004000, (ctrl |= 0x00000001));
195 ram_wr32(fuc, 0x004018, 0x00005000 | r004018);
199 ram_mask(fuc, 0x004168, 0x003f3040, mclk.clk);
200 ram_wr32(fuc, 0x004000, (ctrl |= 0x00000008));
201 ram_mask(fuc, 0x1110e0, 0x00088000, 0x00088000);
202 ram_wr32(fuc, 0x004018, 0x0000d000 | r004018);
205 if ( (nv_ro08(bios, rammap.data + 0x04) & 0x08)) {
206 u32 unk5a0 = (nv_ro16(bios, ramcfg.data + 0x05) << 8) |
207 nv_ro08(bios, ramcfg.data + 0x05);
208 u32 unk5a4 = (nv_ro16(bios, ramcfg.data + 0x07));
209 u32 unk804 = (nv_ro08(bios, ramcfg.data + 0x09) & 0xf0) << 16 |
210 (nv_ro08(bios, ramcfg.data + 0x03) & 0x0f) << 16 |
211 (nv_ro08(bios, ramcfg.data + 0x09) & 0x0f) |
213 ram_wr32(fuc, 0x1005a0, unk5a0);
214 ram_wr32(fuc, 0x1005a4, unk5a4);
215 ram_wr32(fuc, 0x10f804, unk804);
216 ram_mask(fuc, 0x10053c, 0x00001000, 0x00000000);
218 ram_mask(fuc, 0x10053c, 0x00001000, 0x00001000);
219 ram_mask(fuc, 0x10f804, 0x80000000, 0x00000000);
220 ram_mask(fuc, 0x100760, 0x22222222, r100760);
221 ram_mask(fuc, 0x1007a0, 0x22222222, r100760);
222 ram_mask(fuc, 0x1007e0, 0x22222222, r100760);
226 ram_mask(fuc, 0x1110e0, 0x00088000, 0x00011000);
227 ram_wr32(fuc, 0x004000, (ctrl &= ~0x00000008));
231 ram_wr32(fuc, 0x1002dc, 0x00000000);
232 ram_wr32(fuc, 0x1002d4, 0x00000001);
233 ram_wr32(fuc, 0x100210, 0x80000000);
237 ram_mask(fuc, mr[2], 0x00000000, 0x00000000);
239 ram_nuke(fuc, mr[0]);
240 ram_mask(fuc, mr[0], 0x00000000, 0x00000000);
243 ram_mask(fuc, 0x100220[3], 0x00000000, 0x00000000);
244 ram_mask(fuc, 0x100220[1], 0x00000000, 0x00000000);
245 ram_mask(fuc, 0x100220[6], 0x00000000, 0x00000000);
246 ram_mask(fuc, 0x100220[7], 0x00000000, 0x00000000);
247 ram_mask(fuc, 0x100220[2], 0x00000000, 0x00000000);
248 ram_mask(fuc, 0x100220[4], 0x00000000, 0x00000000);
249 ram_mask(fuc, 0x100220[5], 0x00000000, 0x00000000);
250 ram_mask(fuc, 0x100220[0], 0x00000000, 0x00000000);
251 ram_mask(fuc, 0x100220[8], 0x00000000, 0x00000000);
253 data = (nv_ro08(bios, ramcfg.data + 0x02) & 0x08) ? 0x00000000 : 0x00001000;
254 ram_mask(fuc, 0x100200, 0x00001000, data);
256 unk714 = ram_rd32(fuc, 0x100714) & ~0xf0000010;
257 unk718 = ram_rd32(fuc, 0x100718) & ~0x00000100;
258 unk71c = ram_rd32(fuc, 0x10071c) & ~0x00000100;
259 if ( (nv_ro08(bios, ramcfg.data + 0x02) & 0x20))
260 unk714 |= 0xf0000000;
261 if (!(nv_ro08(bios, ramcfg.data + 0x02) & 0x04))
262 unk714 |= 0x00000010;
263 ram_wr32(fuc, 0x100714, unk714);
265 if (nv_ro08(bios, ramcfg.data + 0x02) & 0x01)
266 unk71c |= 0x00000100;
267 ram_wr32(fuc, 0x10071c, unk71c);
269 if (nv_ro08(bios, ramcfg.data + 0x02) & 0x02)
270 unk718 |= 0x00000100;
271 ram_wr32(fuc, 0x100718, unk718);
273 if (nv_ro08(bios, ramcfg.data + 0x02) & 0x10)
274 ram_wr32(fuc, 0x111100, 0x48000000); /*XXX*/
276 ram_mask(fuc, mr[0], 0x100, 0x100);
278 ram_mask(fuc, mr[0], 0x100, 0x000);
282 ram_nsec(fuc, 12000);
284 ram_wr32(fuc, 0x611200, 0x00003330);
285 if ( (nv_ro08(bios, rammap.data + 0x04) & 0x02))
286 ram_mask(fuc, 0x100200, 0x00000800, 0x00000800);
287 if ( (nv_ro08(bios, ramcfg.data + 0x02) & 0x10)) {
288 ram_mask(fuc, 0x111104, 0x00000180, 0x00000180);
289 ram_mask(fuc, 0x111100, 0x40000000, 0x00000000);
291 ram_mask(fuc, 0x111104, 0x00000600, 0x00000600);
295 ram_mask(fuc, 0x004168, 0x00000001, 0x00000000);
296 ram_mask(fuc, 0x004168, 0x00000100, 0x00000000);
298 ram_mask(fuc, 0x004000, 0x00000001, 0x00000000);
299 ram_mask(fuc, 0x004128, 0x00000001, 0x00000000);
300 ram_mask(fuc, 0x004128, 0x00000100, 0x00000000);
307 nva3_ram_prog(struct nouveau_fb *pfb)
309 struct nouveau_device *device = nv_device(pfb);
310 struct nva3_ram *ram = (void *)pfb->ram;
311 struct nva3_ramfuc *fuc = &ram->fuc;
312 ram_exec(fuc, nouveau_boolopt(device->cfgopt, "NvMemExec", false));
317 nva3_ram_tidy(struct nouveau_fb *pfb)
319 struct nva3_ram *ram = (void *)pfb->ram;
320 struct nva3_ramfuc *fuc = &ram->fuc;
321 ram_exec(fuc, false);
325 nva3_ram_init(struct nouveau_object *object)
327 struct nouveau_fb *pfb = (void *)object->parent;
328 struct nva3_ram *ram = (void *)object;
331 ret = nouveau_ram_init(&ram->base);
335 /* prepare for ddr link training, and load training patterns */
336 switch (ram->base.type) {
337 case NV_MEM_TYPE_DDR3: {
338 static const u32 pattern[16] = {
339 0xaaaaaaaa, 0xcccccccc, 0xdddddddd, 0xeeeeeeee,
340 0x00000000, 0x11111111, 0x44444444, 0xdddddddd,
341 0x33333333, 0x55555555, 0x77777777, 0x66666666,
342 0x99999999, 0x88888888, 0xeeeeeeee, 0xbbbbbbbb,
345 nv_wr32(pfb, 0x100538, 0x10001ff6); /*XXX*/
346 nv_wr32(pfb, 0x1005a8, 0x0000ffff);
347 nv_mask(pfb, 0x10f800, 0x00000001, 0x00000001);
348 for (i = 0; i < 0x30; i++) {
349 nv_wr32(pfb, 0x10f8c0, (i << 8) | i);
350 nv_wr32(pfb, 0x10f8e0, (i << 8) | i);
351 nv_wr32(pfb, 0x10f900, pattern[i % 16]);
352 nv_wr32(pfb, 0x10f920, pattern[i % 16]);
364 nva3_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
365 struct nouveau_oclass *oclass, void *data, u32 datasize,
366 struct nouveau_object **pobject)
368 struct nva3_ram *ram;
371 ret = nv50_ram_create(parent, engine, oclass, &ram);
372 *pobject = nv_object(ram);
376 switch (ram->base.type) {
377 case NV_MEM_TYPE_DDR3:
378 ram->base.calc = nva3_ram_calc;
379 ram->base.prog = nva3_ram_prog;
380 ram->base.tidy = nva3_ram_tidy;
383 nv_warn(ram, "reclocking of this ram type unsupported\n");
387 ram->fuc.r_0x004000 = ramfuc_reg(0x004000);
388 ram->fuc.r_0x004004 = ramfuc_reg(0x004004);
389 ram->fuc.r_0x004018 = ramfuc_reg(0x004018);
390 ram->fuc.r_0x004128 = ramfuc_reg(0x004128);
391 ram->fuc.r_0x004168 = ramfuc_reg(0x004168);
392 ram->fuc.r_0x100200 = ramfuc_reg(0x100200);
393 ram->fuc.r_0x100210 = ramfuc_reg(0x100210);
394 for (i = 0; i < 9; i++)
395 ram->fuc.r_0x100220[i] = ramfuc_reg(0x100220 + (i * 4));
396 ram->fuc.r_0x1002d0 = ramfuc_reg(0x1002d0);
397 ram->fuc.r_0x1002d4 = ramfuc_reg(0x1002d4);
398 ram->fuc.r_0x1002dc = ramfuc_reg(0x1002dc);
399 ram->fuc.r_0x10053c = ramfuc_reg(0x10053c);
400 ram->fuc.r_0x1005a0 = ramfuc_reg(0x1005a0);
401 ram->fuc.r_0x1005a4 = ramfuc_reg(0x1005a4);
402 ram->fuc.r_0x100714 = ramfuc_reg(0x100714);
403 ram->fuc.r_0x100718 = ramfuc_reg(0x100718);
404 ram->fuc.r_0x10071c = ramfuc_reg(0x10071c);
405 ram->fuc.r_0x100760 = ramfuc_reg(0x100760);
406 ram->fuc.r_0x1007a0 = ramfuc_reg(0x1007a0);
407 ram->fuc.r_0x1007e0 = ramfuc_reg(0x1007e0);
408 ram->fuc.r_0x10f804 = ramfuc_reg(0x10f804);
409 ram->fuc.r_0x1110e0 = ramfuc_reg(0x1110e0);
410 ram->fuc.r_0x111100 = ramfuc_reg(0x111100);
411 ram->fuc.r_0x111104 = ramfuc_reg(0x111104);
412 ram->fuc.r_0x611200 = ramfuc_reg(0x611200);
414 if (ram->base.ranks > 1) {
415 ram->fuc.r_mr[0] = ramfuc_reg2(0x1002c0, 0x1002c8);
416 ram->fuc.r_mr[1] = ramfuc_reg2(0x1002c4, 0x1002cc);
417 ram->fuc.r_mr[2] = ramfuc_reg2(0x1002e0, 0x1002e8);
418 ram->fuc.r_mr[3] = ramfuc_reg2(0x1002e4, 0x1002ec);
420 ram->fuc.r_mr[0] = ramfuc_reg(0x1002c0);
421 ram->fuc.r_mr[1] = ramfuc_reg(0x1002c4);
422 ram->fuc.r_mr[2] = ramfuc_reg(0x1002e0);
423 ram->fuc.r_mr[3] = ramfuc_reg(0x1002e4);
429 struct nouveau_oclass
431 .ofuncs = &(struct nouveau_ofuncs) {
432 .ctor = nva3_ram_ctor,
433 .dtor = _nouveau_ram_dtor,
434 .init = nva3_ram_init,
435 .fini = _nouveau_ram_fini,