2 * Copyright 2013 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <subdev/gpio.h>
27 #include <subdev/bios.h>
28 #include <subdev/bios/pll.h>
29 #include <subdev/bios/init.h>
30 #include <subdev/bios/rammap.h>
31 #include <subdev/bios/timing.h>
33 #include <subdev/clock.h>
34 #include <subdev/clock/pll.h>
36 #include <subdev/timer.h>
38 #include <core/option.h>
44 /* binary driver only executes this path if the condition (a) is true
45 * for any configuration (combination of rammap+ramcfg+timing) that
46 * can be reached on a given card. for now, we will execute the branch
47 * unconditionally in the hope that a "false everywhere" in the bios
48 * tables doesn't actually mean "don't touch this".
55 struct nvbios_pll refpll;
56 struct nvbios_pll mempll;
58 struct ramfuc_reg r_gpioMV;
60 struct ramfuc_reg r_gpio2E;
62 struct ramfuc_reg r_gpiotrig;
64 struct ramfuc_reg r_0x132020;
65 struct ramfuc_reg r_0x132028;
66 struct ramfuc_reg r_0x132024;
67 struct ramfuc_reg r_0x132030;
68 struct ramfuc_reg r_0x132034;
69 struct ramfuc_reg r_0x132000;
70 struct ramfuc_reg r_0x132004;
71 struct ramfuc_reg r_0x132040;
73 struct ramfuc_reg r_0x10f248;
74 struct ramfuc_reg r_0x10f290;
75 struct ramfuc_reg r_0x10f294;
76 struct ramfuc_reg r_0x10f298;
77 struct ramfuc_reg r_0x10f29c;
78 struct ramfuc_reg r_0x10f2a0;
79 struct ramfuc_reg r_0x10f2a4;
80 struct ramfuc_reg r_0x10f2a8;
81 struct ramfuc_reg r_0x10f2ac;
82 struct ramfuc_reg r_0x10f2cc;
83 struct ramfuc_reg r_0x10f2e8;
84 struct ramfuc_reg r_0x10f250;
85 struct ramfuc_reg r_0x10f24c;
86 struct ramfuc_reg r_0x10fec4;
87 struct ramfuc_reg r_0x10fec8;
88 struct ramfuc_reg r_0x10f604;
89 struct ramfuc_reg r_0x10f614;
90 struct ramfuc_reg r_0x10f610;
91 struct ramfuc_reg r_0x100770;
92 struct ramfuc_reg r_0x100778;
93 struct ramfuc_reg r_0x10f224;
95 struct ramfuc_reg r_0x10f870;
96 struct ramfuc_reg r_0x10f698;
97 struct ramfuc_reg r_0x10f694;
98 struct ramfuc_reg r_0x10f6b8;
99 struct ramfuc_reg r_0x10f808;
100 struct ramfuc_reg r_0x10f670;
101 struct ramfuc_reg r_0x10f60c;
102 struct ramfuc_reg r_0x10f830;
103 struct ramfuc_reg r_0x1373ec;
104 struct ramfuc_reg r_0x10f800;
105 struct ramfuc_reg r_0x10f82c;
107 struct ramfuc_reg r_0x10f978;
108 struct ramfuc_reg r_0x10f910;
109 struct ramfuc_reg r_0x10f914;
111 struct ramfuc_reg r_mr[16]; /* MR0 - MR8, MR15 */
113 struct ramfuc_reg r_0x62c000;
115 struct ramfuc_reg r_0x10f200;
117 struct ramfuc_reg r_0x10f210;
118 struct ramfuc_reg r_0x10f310;
119 struct ramfuc_reg r_0x10f314;
120 struct ramfuc_reg r_0x10f318;
121 struct ramfuc_reg r_0x10f090;
122 struct ramfuc_reg r_0x10f69c;
123 struct ramfuc_reg r_0x10f824;
124 struct ramfuc_reg r_0x1373f0;
125 struct ramfuc_reg r_0x1373f4;
126 struct ramfuc_reg r_0x137320;
127 struct ramfuc_reg r_0x10f65c;
128 struct ramfuc_reg r_0x10f6bc;
129 struct ramfuc_reg r_0x100710;
130 struct ramfuc_reg r_0x100750;
134 struct nouveau_ram base;
135 struct nve0_ramfuc fuc;
147 /*******************************************************************************
149 ******************************************************************************/
151 nve0_ram_train(struct nve0_ramfuc *fuc, u32 mask, u32 data)
153 struct nve0_ram *ram = container_of(fuc, typeof(*ram), fuc);
154 u32 addr = 0x110974, i;
156 ram_mask(fuc, 0x10f910, mask, data);
157 ram_mask(fuc, 0x10f914, mask, data);
159 for (i = 0; (data & 0x80000000) && i < ram->parts; addr += 0x1000, i++) {
160 if (ram->pmask & (1 << i))
162 ram_wait(fuc, addr, 0x0000000f, 0x00000000, 500000);
167 r1373f4_init(struct nve0_ramfuc *fuc)
169 struct nve0_ram *ram = container_of(fuc, typeof(*ram), fuc);
170 const u32 mcoef = ((--ram->P2 << 28) | (ram->N2 << 8) | ram->M2);
171 const u32 rcoef = (( ram->P1 << 16) | (ram->N1 << 8) | ram->M1);
172 const u32 runk0 = ram->fN1 << 16;
173 const u32 runk1 = ram->fN1;
175 if (ram->from == 2) {
176 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00001100);
177 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00000010);
179 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00010010);
182 ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000000);
183 ram_mask(fuc, 0x1373f4, 0x00000010, 0x00000000);
185 /* (re)program refpll, if required */
186 if ((ram_rd32(fuc, 0x132024) & 0xffffffff) != rcoef ||
187 (ram_rd32(fuc, 0x132034) & 0x0000ffff) != runk1) {
188 ram_mask(fuc, 0x132000, 0x00000001, 0x00000000);
189 ram_mask(fuc, 0x132020, 0x00000001, 0x00000000);
190 ram_wr32(fuc, 0x137320, 0x00000000);
191 ram_mask(fuc, 0x132030, 0xffff0000, runk0);
192 ram_mask(fuc, 0x132034, 0x0000ffff, runk1);
193 ram_wr32(fuc, 0x132024, rcoef);
194 ram_mask(fuc, 0x132028, 0x00080000, 0x00080000);
195 ram_mask(fuc, 0x132020, 0x00000001, 0x00000001);
196 ram_wait(fuc, 0x137390, 0x00020000, 0x00020000, 64000);
197 ram_mask(fuc, 0x132028, 0x00080000, 0x00000000);
200 /* (re)program mempll, if required */
201 if (ram->mode == 2) {
202 ram_mask(fuc, 0x1373f4, 0x00010000, 0x00000000);
203 ram_mask(fuc, 0x132000, 0x00000001, 0x00000000);
204 ram_mask(fuc, 0x132004, 0x103fffff, mcoef);
205 ram_mask(fuc, 0x132000, 0x00000001, 0x00000001);
206 ram_wait(fuc, 0x137390, 0x00000002, 0x00000002, 64000);
207 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00001100);
209 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00010100);
212 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00000010);
216 r1373f4_fini(struct nve0_ramfuc *fuc)
218 struct nve0_ram *ram = container_of(fuc, typeof(*ram), fuc);
219 struct nouveau_ram_data *next = ram->base.next;
220 u8 v0 = next->bios.ramcfg_11_03_c0;
221 u8 v1 = next->bios.ramcfg_11_03_30;
224 tmp = ram_rd32(fuc, 0x1373ec) & ~0x00030000;
225 ram_wr32(fuc, 0x1373ec, tmp | (v1 << 16));
226 ram_mask(fuc, 0x1373f0, (~ram->mode & 3), 0x00000000);
227 if (ram->mode == 2) {
228 ram_mask(fuc, 0x1373f4, 0x00000003, 0x000000002);
229 ram_mask(fuc, 0x1373f4, 0x00001100, 0x000000000);
231 ram_mask(fuc, 0x1373f4, 0x00000003, 0x000000001);
232 ram_mask(fuc, 0x1373f4, 0x00010000, 0x000000000);
234 ram_mask(fuc, 0x10f800, 0x00000030, (v0 ^ v1) << 4);
238 nve0_ram_nuts(struct nve0_ram *ram, struct ramfuc_reg *reg,
239 u32 _mask, u32 _data, u32 _copy)
241 struct nve0_fb_priv *priv = (void *)nouveau_fb(ram);
242 struct ramfuc *fuc = &ram->fuc.base;
243 u32 addr = 0x110000 + (reg->addr[0] & 0xfff);
244 u32 mask = _mask | _copy;
245 u32 data = (_data & _mask) | (reg->data & _copy);
248 for (i = 0; i < 16; i++, addr += 0x1000) {
249 if (ram->pnuts & (1 << i)) {
250 u32 prev = nv_rd32(priv, addr);
251 u32 next = (prev & ~mask) | data;
252 nouveau_memx_wr32(fuc->memx, addr, next);
256 #define ram_nuts(s,r,m,d,c) \
257 nve0_ram_nuts((s), &(s)->fuc.r_##r, (m), (d), (c))
260 nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
262 struct nve0_ram *ram = (void *)pfb->ram;
263 struct nve0_ramfuc *fuc = &ram->fuc;
264 struct nouveau_ram_data *next = ram->base.next;
265 int vc = !(next->bios.ramcfg_11_02_08);
266 int mv = !(next->bios.ramcfg_11_02_04);
269 ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000);
270 ram_wr32(fuc, 0x62c000, 0x0f0f0000);
272 /* MR1: turn termination on early, for some reason.. */
273 if ((ram->base.mr[1] & 0x03c) != 0x030) {
274 ram_mask(fuc, mr[1], 0x03c, ram->base.mr[1] & 0x03c);
275 ram_nuts(ram, mr[1], 0x03c, ram->base.mr1_nuts & 0x03c, 0x000);
278 if (vc == 1 && ram_have(fuc, gpio2E)) {
279 u32 temp = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[1]);
280 if (temp != ram_rd32(fuc, gpio2E)) {
281 ram_wr32(fuc, gpiotrig, 1);
282 ram_nsec(fuc, 20000);
286 ram_mask(fuc, 0x10f200, 0x00000800, 0x00000000);
288 nve0_ram_train(fuc, 0x01020000, 0x000c0000);
290 ram_wr32(fuc, 0x10f210, 0x00000000); /* REFRESH_AUTO = 0 */
292 ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */
295 ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000);
296 ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */
297 ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000);
298 ram_wr32(fuc, 0x10f090, 0x00000061);
299 ram_wr32(fuc, 0x10f090, 0xc000007f);
302 ram_wr32(fuc, 0x10f698, 0x00000000);
303 ram_wr32(fuc, 0x10f69c, 0x00000000);
305 /*XXX: there does appear to be some kind of condition here, simply
306 * modifying these bits in the vbios from the default pl0
307 * entries shows no change. however, the data does appear to
308 * be correct and may be required for the transition back
312 if (ram_rd32(fuc, 0x10f978) & 0x00800000)
317 switch (next->bios.ramcfg_11_03_c0) {
318 case 3: data &= ~0x00000040; break;
319 case 2: data &= ~0x00000100; break;
320 case 1: data &= ~0x80000000; break;
321 case 0: data &= ~0x00000400; break;
324 switch (next->bios.ramcfg_11_03_30) {
325 case 3: data &= ~0x00000020; break;
326 case 2: data &= ~0x00000080; break;
327 case 1: data &= ~0x00080000; break;
328 case 0: data &= ~0x00000200; break;
332 if (next->bios.ramcfg_11_02_80)
334 if (next->bios.ramcfg_11_02_40)
336 if (next->bios.ramcfg_11_07_10)
338 if (next->bios.ramcfg_11_07_08)
342 if (ram_rd32(fuc, 0x10f978) & 0x00800000)
345 ram_mask(fuc, 0x10f824, mask, data);
347 ram_mask(fuc, 0x132040, 0x00010000, 0x00000000);
349 if (ram->from == 2 && ram->mode != 2) {
350 ram_mask(fuc, 0x10f808, 0x00080000, 0x00000000);
351 ram_mask(fuc, 0x10f200, 0x18008000, 0x00008000);
352 ram_mask(fuc, 0x10f800, 0x00000000, 0x00000004);
353 ram_mask(fuc, 0x10f830, 0x00008000, 0x01040010);
354 ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000);
356 ram_mask(fuc, 0x1373f0, 0x00000002, 0x00000001);
358 ram_mask(fuc, 0x10f830, 0x00c00000, 0x00240001);
360 if (ram->from != 2 && ram->mode != 2) {
365 if (ram_have(fuc, gpioMV)) {
366 u32 temp = ram_mask(fuc, gpioMV, 0x3000, fuc->r_funcMV[mv]);
367 if (temp != ram_rd32(fuc, gpioMV)) {
368 ram_wr32(fuc, gpiotrig, 1);
369 ram_nsec(fuc, 64000);
373 if ( (next->bios.ramcfg_11_02_40) ||
374 (next->bios.ramcfg_11_07_10)) {
375 ram_mask(fuc, 0x132040, 0x00010000, 0x00010000);
376 ram_nsec(fuc, 20000);
379 if (ram->from != 2 && ram->mode == 2) {
380 if (0 /*XXX: Titan */)
381 ram_mask(fuc, 0x10f200, 0x18000000, 0x18000000);
382 ram_mask(fuc, 0x10f800, 0x00000004, 0x00000000);
383 ram_mask(fuc, 0x1373f0, 0x00000000, 0x00000002);
384 ram_mask(fuc, 0x10f830, 0x00800001, 0x00408010);
387 ram_mask(fuc, 0x10f808, 0x00000000, 0x00080000);
388 ram_mask(fuc, 0x10f200, 0x00808000, 0x00800000);
390 if (ram->from == 2 && ram->mode == 2) {
391 ram_mask(fuc, 0x10f800, 0x00000004, 0x00000000);
396 if (ram->mode != 2) /*XXX*/ {
397 if (next->bios.ramcfg_11_07_40)
398 ram_mask(fuc, 0x10f670, 0x80000000, 0x80000000);
401 ram_wr32(fuc, 0x10f65c, 0x00000011 * next->bios.rammap_11_11_0c);
402 ram_wr32(fuc, 0x10f6b8, 0x01010101 * next->bios.ramcfg_11_09);
403 ram_wr32(fuc, 0x10f6bc, 0x01010101 * next->bios.ramcfg_11_09);
405 if (!next->bios.ramcfg_11_07_08 && !next->bios.ramcfg_11_07_04) {
406 ram_wr32(fuc, 0x10f698, 0x01010101 * next->bios.ramcfg_11_04);
407 ram_wr32(fuc, 0x10f69c, 0x01010101 * next->bios.ramcfg_11_04);
409 if (!next->bios.ramcfg_11_07_08) {
410 ram_wr32(fuc, 0x10f698, 0x00000000);
411 ram_wr32(fuc, 0x10f69c, 0x00000000);
414 if (ram->mode != 2) {
415 u32 data = 0x01000100 * next->bios.ramcfg_11_04;
416 ram_nuke(fuc, 0x10f694);
417 ram_mask(fuc, 0x10f694, 0xff00ff00, data);
420 if (ram->mode == 2 && (next->bios.ramcfg_11_08_10))
424 ram_mask(fuc, 0x10f60c, 0x00000080, data);
428 if (!(next->bios.ramcfg_11_02_80))
430 if (!(next->bios.ramcfg_11_02_40))
432 if (!(next->bios.ramcfg_11_07_10))
434 if (!(next->bios.ramcfg_11_07_08))
438 ram_mask(fuc, 0x10f824, mask, data);
440 if (next->bios.ramcfg_11_01_08)
444 ram_mask(fuc, 0x10f200, 0x00001000, data);
446 if (ram_rd32(fuc, 0x10f670) & 0x80000000) {
447 ram_nsec(fuc, 10000);
448 ram_mask(fuc, 0x10f670, 0x80000000, 0x00000000);
451 if (next->bios.ramcfg_11_08_01)
455 ram_mask(fuc, 0x10f82c, 0x00100000, data);
458 if (next->bios.ramcfg_11_08_08)
460 if (next->bios.ramcfg_11_08_04)
462 if (next->bios.ramcfg_11_08_02)
464 ram_mask(fuc, 0x10f830, 0x00007000, data);
467 ram_mask(fuc, 0x10f248, 0xffffffff, next->bios.timing[10]);
468 ram_mask(fuc, 0x10f290, 0xffffffff, next->bios.timing[0]);
469 ram_mask(fuc, 0x10f294, 0xffffffff, next->bios.timing[1]);
470 ram_mask(fuc, 0x10f298, 0xffffffff, next->bios.timing[2]);
471 ram_mask(fuc, 0x10f29c, 0xffffffff, next->bios.timing[3]);
472 ram_mask(fuc, 0x10f2a0, 0xffffffff, next->bios.timing[4]);
473 ram_mask(fuc, 0x10f2a4, 0xffffffff, next->bios.timing[5]);
474 ram_mask(fuc, 0x10f2a8, 0xffffffff, next->bios.timing[6]);
475 ram_mask(fuc, 0x10f2ac, 0xffffffff, next->bios.timing[7]);
476 ram_mask(fuc, 0x10f2cc, 0xffffffff, next->bios.timing[8]);
477 ram_mask(fuc, 0x10f2e8, 0xffffffff, next->bios.timing[9]);
479 data = mask = 0x00000000;
480 if (NOTE00(ramcfg_08_20)) {
481 if (next->bios.ramcfg_11_08_20)
485 ram_mask(fuc, 0x10f200, mask, data);
487 data = mask = 0x00000000;
488 if (NOTE00(ramcfg_02_03 != 0)) {
489 data |= (next->bios.ramcfg_11_02_03) << 8;
492 if (NOTE00(ramcfg_01_10)) {
493 if (next->bios.ramcfg_11_01_10)
497 ram_mask(fuc, 0x10f604, mask, data);
499 data = mask = 0x00000000;
500 if (NOTE00(timing_30_07 != 0)) {
501 data |= (next->bios.timing_20_30_07) << 28;
504 if (NOTE00(ramcfg_01_01)) {
505 if (next->bios.ramcfg_11_01_01)
509 ram_mask(fuc, 0x10f614, mask, data);
511 data = mask = 0x00000000;
512 if (NOTE00(timing_30_07 != 0)) {
513 data |= (next->bios.timing_20_30_07) << 28;
516 if (NOTE00(ramcfg_01_02)) {
517 if (next->bios.ramcfg_11_01_02)
521 ram_mask(fuc, 0x10f610, mask, data);
525 if (!(next->bios.ramcfg_11_01_04))
527 if (!(next->bios.ramcfg_11_07_80))
529 /*XXX: see note above about there probably being some condition
530 * for the 10f824 stuff that uses ramcfg 3...
532 if ( (next->bios.ramcfg_11_03_f0)) {
533 if (next->bios.rammap_11_08_0c) {
534 if (!(next->bios.ramcfg_11_07_80))
545 ram_mask(fuc, 0x10f808, mask, data);
547 ram_wr32(fuc, 0x10f870, 0x11111111 * next->bios.ramcfg_11_03_0f);
549 data = mask = 0x00000000;
550 if (NOTE00(ramcfg_02_03 != 0)) {
551 data |= next->bios.ramcfg_11_02_03;
554 if (NOTE00(ramcfg_01_10)) {
555 if (next->bios.ramcfg_11_01_10)
560 if ((ram_mask(fuc, 0x100770, mask, data) & mask & 4) != (data & 4)) {
561 ram_mask(fuc, 0x100750, 0x00000008, 0x00000008);
562 ram_wr32(fuc, 0x100710, 0x00000000);
563 ram_wait(fuc, 0x100710, 0x80000000, 0x80000000, 200000);
566 data = (next->bios.timing_20_30_07) << 8;
567 if (next->bios.ramcfg_11_01_01)
569 ram_mask(fuc, 0x100778, 0x00000700, data);
571 ram_mask(fuc, 0x10f250, 0x000003f0, next->bios.timing_20_2c_003f << 4);
572 ram_mask(fuc, 0x10f24c, 0x7f000000, next->bios.timing_20_2c_1fc0 << 24);
573 ram_mask(fuc, 0x10f224, 0x001f0000, next->bios.timing_20_30_f8 << 16);
575 ram_mask(fuc, 0x10fec4, 0x041e0f07, next->bios.timing_20_31_0800 << 26 |
576 next->bios.timing_20_31_0780 << 17 |
577 next->bios.timing_20_31_0078 << 8 |
578 next->bios.timing_20_31_0007);
579 ram_mask(fuc, 0x10fec8, 0x00000027, next->bios.timing_20_31_8000 << 5 |
580 next->bios.timing_20_31_7000);
582 ram_wr32(fuc, 0x10f090, 0x4000007e);
584 ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */
585 ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */
586 ram_wr32(fuc, 0x10f210, 0x80000000); /* REFRESH_AUTO = 1 */
588 if ((next->bios.ramcfg_11_08_10) && (ram->mode == 2) /*XXX*/) {
589 u32 temp = ram_mask(fuc, 0x10f294, 0xff000000, 0x24000000);
590 nve0_ram_train(fuc, 0xbc0e0000, 0xa4010000); /*XXX*/
592 ram_wr32(fuc, 0x10f294, temp);
595 ram_mask(fuc, mr[3], 0xfff, ram->base.mr[3]);
596 ram_wr32(fuc, mr[0], ram->base.mr[0]);
597 ram_mask(fuc, mr[8], 0xfff, ram->base.mr[8]);
599 ram_mask(fuc, mr[1], 0xfff, ram->base.mr[1]);
600 ram_mask(fuc, mr[5], 0xfff, ram->base.mr[5] & ~0x004); /* LP3 later */
601 ram_mask(fuc, mr[6], 0xfff, ram->base.mr[6]);
602 ram_mask(fuc, mr[7], 0xfff, ram->base.mr[7]);
604 if (vc == 0 && ram_have(fuc, gpio2E)) {
605 u32 temp = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[0]);
606 if (temp != ram_rd32(fuc, gpio2E)) {
607 ram_wr32(fuc, gpiotrig, 1);
608 ram_nsec(fuc, 20000);
612 ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000);
613 ram_wr32(fuc, 0x10f318, 0x00000001); /* NOP? */
614 ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000);
616 ram_nuts(ram, 0x10f200, 0x18808800, 0x00000000, 0x18808800);
618 data = ram_rd32(fuc, 0x10f978);
621 if (!(next->bios.ramcfg_11_07_08)) {
622 if (!(next->bios.ramcfg_11_07_04))
629 ram_wr32(fuc, 0x10f978, data);
631 if (ram->mode == 1) {
632 data = ram_rd32(fuc, 0x10f830) | 0x00000001;
633 ram_wr32(fuc, 0x10f830, data);
636 if (!(next->bios.ramcfg_11_07_08)) {
638 if ( (next->bios.ramcfg_11_07_04))
640 if (!(next->bios.rammap_11_08_10))
645 nve0_ram_train(fuc, 0xbc0f0000, data);
646 if (1) /* XXX: not always? */
649 if (ram->mode == 2) { /*XXX*/
650 ram_mask(fuc, 0x10f800, 0x00000004, 0x00000004);
654 if (ram_mask(fuc, mr[5], 0x004, ram->base.mr[5]) != ram->base.mr[5])
657 if (ram->mode != 2) {
658 ram_mask(fuc, 0x10f830, 0x01000000, 0x01000000);
659 ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000);
662 if (next->bios.ramcfg_11_07_02)
663 nve0_ram_train(fuc, 0x80020000, 0x01000000);
665 ram_wr32(fuc, 0x62c000, 0x0f0f0f00);
667 if (next->bios.rammap_11_08_01)
671 ram_mask(fuc, 0x10f200, 0x00000800, data);
672 ram_nuts(ram, 0x10f200, 0x18808800, data, 0x18808800);
676 /*******************************************************************************
678 ******************************************************************************/
681 nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq)
683 struct nve0_ram *ram = (void *)pfb->ram;
684 struct nve0_ramfuc *fuc = &ram->fuc;
685 const u32 rcoef = (( ram->P1 << 16) | (ram->N1 << 8) | ram->M1);
686 const u32 runk0 = ram->fN1 << 16;
687 const u32 runk1 = ram->fN1;
688 struct nouveau_ram_data *next = ram->base.next;
689 int vc = !(next->bios.ramcfg_11_02_08);
690 int mv = !(next->bios.ramcfg_11_02_04);
693 ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000);
694 ram_wr32(fuc, 0x62c000, 0x0f0f0000);
696 if (vc == 1 && ram_have(fuc, gpio2E)) {
697 u32 temp = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[1]);
698 if (temp != ram_rd32(fuc, gpio2E)) {
699 ram_wr32(fuc, gpiotrig, 1);
700 ram_nsec(fuc, 20000);
704 ram_mask(fuc, 0x10f200, 0x00000800, 0x00000000);
705 if ((next->bios.ramcfg_11_03_f0))
706 ram_mask(fuc, 0x10f808, 0x04000000, 0x04000000);
708 ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */
709 ram_wr32(fuc, 0x10f210, 0x00000000); /* REFRESH_AUTO = 0 */
710 ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */
711 ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000);
712 ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */
713 ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000);
716 ram_wr32(fuc, 0x10f090, 0x00000060);
717 ram_wr32(fuc, 0x10f090, 0xc000007e);
719 /*XXX: there does appear to be some kind of condition here, simply
720 * modifying these bits in the vbios from the default pl0
721 * entries shows no change. however, the data does appear to
722 * be correct and may be required for the transition back
730 switch (next->bios.ramcfg_11_03_c0) {
731 case 3: data &= ~0x00000040; break;
732 case 2: data &= ~0x00000100; break;
733 case 1: data &= ~0x80000000; break;
734 case 0: data &= ~0x00000400; break;
737 switch (next->bios.ramcfg_11_03_30) {
738 case 3: data &= ~0x00000020; break;
739 case 2: data &= ~0x00000080; break;
740 case 1: data &= ~0x00080000; break;
741 case 0: data &= ~0x00000200; break;
745 if (next->bios.ramcfg_11_02_80)
747 if (next->bios.ramcfg_11_02_40)
749 if (next->bios.ramcfg_11_07_10)
751 if (next->bios.ramcfg_11_07_08)
755 ram_mask(fuc, 0x10f824, mask, data);
757 ram_mask(fuc, 0x132040, 0x00010000, 0x00000000);
759 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00010010);
760 data = ram_rd32(fuc, 0x1373ec) & ~0x00030000;
761 data |= (next->bios.ramcfg_11_03_30) << 12;
762 ram_wr32(fuc, 0x1373ec, data);
763 ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000000);
764 ram_mask(fuc, 0x1373f4, 0x00000010, 0x00000000);
766 /* (re)program refpll, if required */
767 if ((ram_rd32(fuc, 0x132024) & 0xffffffff) != rcoef ||
768 (ram_rd32(fuc, 0x132034) & 0x0000ffff) != runk1) {
769 ram_mask(fuc, 0x132000, 0x00000001, 0x00000000);
770 ram_mask(fuc, 0x132020, 0x00000001, 0x00000000);
771 ram_wr32(fuc, 0x137320, 0x00000000);
772 ram_mask(fuc, 0x132030, 0xffff0000, runk0);
773 ram_mask(fuc, 0x132034, 0x0000ffff, runk1);
774 ram_wr32(fuc, 0x132024, rcoef);
775 ram_mask(fuc, 0x132028, 0x00080000, 0x00080000);
776 ram_mask(fuc, 0x132020, 0x00000001, 0x00000001);
777 ram_wait(fuc, 0x137390, 0x00020000, 0x00020000, 64000);
778 ram_mask(fuc, 0x132028, 0x00080000, 0x00000000);
781 ram_mask(fuc, 0x1373f4, 0x00000010, 0x00000010);
782 ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000001);
783 ram_mask(fuc, 0x1373f4, 0x00010000, 0x00000000);
785 if (ram_have(fuc, gpioMV)) {
786 u32 temp = ram_mask(fuc, gpioMV, 0x3000, fuc->r_funcMV[mv]);
787 if (temp != ram_rd32(fuc, gpioMV)) {
788 ram_wr32(fuc, gpiotrig, 1);
789 ram_nsec(fuc, 64000);
793 if ( (next->bios.ramcfg_11_02_40) ||
794 (next->bios.ramcfg_11_07_10)) {
795 ram_mask(fuc, 0x132040, 0x00010000, 0x00010000);
796 ram_nsec(fuc, 20000);
799 if (ram->mode != 2) /*XXX*/ {
800 if (next->bios.ramcfg_11_07_40)
801 ram_mask(fuc, 0x10f670, 0x80000000, 0x80000000);
804 ram_wr32(fuc, 0x10f65c, 0x00000011 * next->bios.rammap_11_11_0c);
805 ram_wr32(fuc, 0x10f6b8, 0x01010101 * next->bios.ramcfg_11_09);
806 ram_wr32(fuc, 0x10f6bc, 0x01010101 * next->bios.ramcfg_11_09);
810 if (!(next->bios.ramcfg_11_02_80))
812 if (!(next->bios.ramcfg_11_02_40))
814 if (!(next->bios.ramcfg_11_07_10))
816 if (!(next->bios.ramcfg_11_07_08))
820 ram_mask(fuc, 0x10f824, mask, data);
823 if (next->bios.ramcfg_11_08_01)
827 ram_mask(fuc, 0x10f82c, 0x00100000, data);
830 ram_mask(fuc, 0x10f248, 0xffffffff, next->bios.timing[10]);
831 ram_mask(fuc, 0x10f290, 0xffffffff, next->bios.timing[0]);
832 ram_mask(fuc, 0x10f294, 0xffffffff, next->bios.timing[1]);
833 ram_mask(fuc, 0x10f298, 0xffffffff, next->bios.timing[2]);
834 ram_mask(fuc, 0x10f29c, 0xffffffff, next->bios.timing[3]);
835 ram_mask(fuc, 0x10f2a0, 0xffffffff, next->bios.timing[4]);
836 ram_mask(fuc, 0x10f2a4, 0xffffffff, next->bios.timing[5]);
837 ram_mask(fuc, 0x10f2a8, 0xffffffff, next->bios.timing[6]);
838 ram_mask(fuc, 0x10f2ac, 0xffffffff, next->bios.timing[7]);
839 ram_mask(fuc, 0x10f2cc, 0xffffffff, next->bios.timing[8]);
840 ram_mask(fuc, 0x10f2e8, 0xffffffff, next->bios.timing[9]);
844 if (!(next->bios.ramcfg_11_01_04))
846 if (!(next->bios.ramcfg_11_07_80))
848 /*XXX: see note above about there probably being some condition
849 * for the 10f824 stuff that uses ramcfg 3...
851 if ( (next->bios.ramcfg_11_03_f0)) {
852 if (next->bios.rammap_11_08_0c) {
853 if (!(next->bios.ramcfg_11_07_80))
865 ram_mask(fuc, 0x10f808, mask, data);
867 ram_wr32(fuc, 0x10f870, 0x11111111 * next->bios.ramcfg_11_03_0f);
869 ram_mask(fuc, 0x10f250, 0x000003f0, next->bios.timing_20_2c_003f << 4);
871 data = (next->bios.timing[10] & 0x7f000000) >> 24;
872 if ( next->bios.timing_20_2c_1fc0 > data)
873 data = next->bios.timing_20_2c_1fc0;
874 ram_mask(fuc, 0x10f24c, 0x7f000000, data << 24);
876 ram_mask(fuc, 0x10f224, 0x001f0000, next->bios.timing_20_30_f8);
878 ram_wr32(fuc, 0x10f090, 0x4000007f);
881 ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */
882 ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */
883 ram_wr32(fuc, 0x10f210, 0x80000000); /* REFRESH_AUTO = 1 */
886 ram_nuke(fuc, mr[0]);
887 ram_mask(fuc, mr[0], 0x100, 0x100);
888 ram_mask(fuc, mr[0], 0x100, 0x000);
890 ram_mask(fuc, mr[2], 0xfff, ram->base.mr[2]);
891 ram_wr32(fuc, mr[0], ram->base.mr[0]);
894 ram_nuke(fuc, mr[0]);
895 ram_mask(fuc, mr[0], 0x100, 0x100);
896 ram_mask(fuc, mr[0], 0x100, 0x000);
898 if (vc == 0 && ram_have(fuc, gpio2E)) {
899 u32 temp = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[0]);
900 if (temp != ram_rd32(fuc, gpio2E)) {
901 ram_wr32(fuc, gpiotrig, 1);
902 ram_nsec(fuc, 20000);
906 if (ram->mode != 2) {
907 ram_mask(fuc, 0x10f830, 0x01000000, 0x01000000);
908 ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000);
911 ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000);
912 ram_wr32(fuc, 0x10f318, 0x00000001); /* NOP? */
913 ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000);
916 ram_wr32(fuc, 0x62c000, 0x0f0f0f00);
918 if (next->bios.rammap_11_08_01)
922 ram_mask(fuc, 0x10f200, 0x00000800, data);
926 /*******************************************************************************
928 ******************************************************************************/
931 nve0_ram_calc_data(struct nouveau_fb *pfb, u32 freq,
932 struct nouveau_ram_data *data)
934 struct nouveau_bios *bios = nouveau_bios(pfb);
935 struct nve0_ram *ram = (void *)pfb->ram;
938 /* lookup memory config data relevant to the target frequency */
939 ram->base.rammap.data = nvbios_rammapEp(bios, freq / 1000,
940 &ram->base.rammap.version,
941 &ram->base.rammap.size,
942 &cnt, &len, &data->bios);
943 if (!ram->base.rammap.data || ram->base.rammap.version != 0x11 ||
944 ram->base.rammap.size < 0x09) {
945 nv_error(pfb, "invalid/missing rammap entry\n");
949 /* locate specific data set for the attached memory */
950 ram->base.ramcfg.data = nvbios_rammapSp(bios, ram->base.rammap.data,
951 ram->base.rammap.version,
952 ram->base.rammap.size, cnt, len,
953 nvbios_ramcfg_index(bios),
954 &ram->base.ramcfg.version,
955 &ram->base.ramcfg.size,
957 if (!ram->base.ramcfg.data || ram->base.ramcfg.version != 0x11 ||
958 ram->base.ramcfg.size < 0x08) {
959 nv_error(pfb, "invalid/missing ramcfg entry\n");
963 /* lookup memory timings, if bios says they're present */
964 strap = nv_ro08(bios, ram->base.ramcfg.data + 0x00);
966 ram->base.timing.data =
967 nvbios_timingEp(bios, strap, &ram->base.timing.version,
968 &ram->base.timing.size, &cnt, &len,
970 if (!ram->base.timing.data ||
971 ram->base.timing.version != 0x20 ||
972 ram->base.timing.size < 0x33) {
973 nv_error(pfb, "invalid/missing timing entry\n");
977 ram->base.timing.data = 0;
985 nve0_ram_calc_xits(struct nouveau_fb *pfb, struct nouveau_ram_data *next)
987 struct nve0_ram *ram = (void *)pfb->ram;
988 struct nve0_ramfuc *fuc = &ram->fuc;
992 ret = ram_init(fuc, pfb);
996 ram->mode = (next->freq > fuc->refpll.vco1.max_freq) ? 2 : 1;
997 ram->from = ram_rd32(fuc, 0x1373f4) & 0x0000000f;
999 /* XXX: this is *not* what nvidia do. on fermi nvidia generally
1000 * select, based on some unknown condition, one of the two possible
1001 * reference frequencies listed in the vbios table for mempll and
1002 * program refpll to that frequency.
1004 * so far, i've seen very weird values being chosen by nvidia on
1005 * kepler boards, no idea how/why they're chosen.
1007 refclk = next->freq;
1009 refclk = fuc->mempll.refclk;
1011 /* calculate refpll coefficients */
1012 ret = nva3_pll_calc(nv_subdev(pfb), &fuc->refpll, refclk, &ram->N1,
1013 &ram->fN1, &ram->M1, &ram->P1);
1014 fuc->mempll.refclk = ret;
1016 nv_error(pfb, "unable to calc refpll\n");
1020 /* calculate mempll coefficients, if we're using it */
1021 if (ram->mode == 2) {
1022 /* post-divider doesn't work... the reg takes the values but
1023 * appears to completely ignore it. there *is* a bit at
1024 * bit 28 that appears to divide the clock by 2 if set.
1026 fuc->mempll.min_p = 1;
1027 fuc->mempll.max_p = 2;
1029 ret = nva3_pll_calc(nv_subdev(pfb), &fuc->mempll, next->freq,
1030 &ram->N2, NULL, &ram->M2, &ram->P2);
1032 nv_error(pfb, "unable to calc mempll\n");
1037 for (i = 0; i < ARRAY_SIZE(fuc->r_mr); i++) {
1038 if (ram_have(fuc, mr[i]))
1039 ram->base.mr[i] = ram_rd32(fuc, mr[i]);
1041 ram->base.freq = next->freq;
1043 switch (ram->base.type) {
1044 case NV_MEM_TYPE_DDR3:
1045 ret = nouveau_sddr3_calc(&ram->base);
1047 ret = nve0_ram_calc_sddr3(pfb, next->freq);
1049 case NV_MEM_TYPE_GDDR5:
1050 ret = nouveau_gddr5_calc(&ram->base, ram->pnuts != 0);
1052 ret = nve0_ram_calc_gddr5(pfb, next->freq);
1063 nve0_ram_calc(struct nouveau_fb *pfb, u32 freq)
1065 struct nouveau_clock *clk = nouveau_clock(pfb);
1066 struct nve0_ram *ram = (void *)pfb->ram;
1067 struct nouveau_ram_data *xits = &ram->base.xition;
1068 struct nouveau_ram_data *copy;
1071 if (ram->base.next == NULL) {
1072 ret = nve0_ram_calc_data(pfb, clk->read(clk, nv_clk_src_mem),
1077 ret = nve0_ram_calc_data(pfb, freq, &ram->base.target);
1081 if (ram->base.target.freq < ram->base.former.freq) {
1082 *xits = ram->base.target;
1083 copy = &ram->base.former;
1085 *xits = ram->base.former;
1086 copy = &ram->base.target;
1089 xits->bios.ramcfg_11_02_04 = copy->bios.ramcfg_11_02_04;
1090 xits->bios.ramcfg_11_02_03 = copy->bios.ramcfg_11_02_03;
1091 xits->bios.timing_20_30_07 = copy->bios.timing_20_30_07;
1093 ram->base.next = &ram->base.target;
1094 if (memcmp(xits, &ram->base.former, sizeof(xits->bios)))
1095 ram->base.next = &ram->base.xition;
1097 BUG_ON(ram->base.next != &ram->base.xition);
1098 ram->base.next = &ram->base.target;
1101 return nve0_ram_calc_xits(pfb, ram->base.next);
1105 nve0_ram_prog(struct nouveau_fb *pfb)
1107 struct nouveau_device *device = nv_device(pfb);
1108 struct nve0_ram *ram = (void *)pfb->ram;
1109 struct nve0_ramfuc *fuc = &ram->fuc;
1110 ram_exec(fuc, nouveau_boolopt(device->cfgopt, "NvMemExec", false));
1111 return (ram->base.next == &ram->base.xition);
1115 nve0_ram_tidy(struct nouveau_fb *pfb)
1117 struct nve0_ram *ram = (void *)pfb->ram;
1118 struct nve0_ramfuc *fuc = &ram->fuc;
1119 ram->base.next = NULL;
1120 ram_exec(fuc, false);
1124 nve0_ram_init(struct nouveau_object *object)
1126 struct nouveau_fb *pfb = (void *)object->parent;
1127 struct nve0_ram *ram = (void *)object;
1128 struct nouveau_bios *bios = nouveau_bios(pfb);
1129 static const u8 train0[] = {
1130 0x00, 0xff, 0xff, 0x00, 0xff, 0x00,
1131 0x00, 0xff, 0xff, 0x00, 0xff, 0x00,
1133 static const u32 train1[] = {
1134 0x00000000, 0xffffffff,
1135 0x55555555, 0xaaaaaaaa,
1136 0x33333333, 0xcccccccc,
1137 0xf0f0f0f0, 0x0f0f0f0f,
1138 0x00ff00ff, 0xff00ff00,
1139 0x0000ffff, 0xffff0000,
1141 u8 ver, hdr, cnt, len, snr, ssz;
1145 ret = nouveau_ram_init(&ram->base);
1149 /* run a bunch of tables from rammap table. there's actually
1150 * individual pointers for each rammap entry too, but, nvidia
1151 * seem to just run the last two entries' scripts early on in
1152 * their init, and never again.. we'll just run 'em all once
1155 * i strongly suspect that each script is for a separate mode
1156 * (likely selected by 0x10f65c's lower bits?), and the
1157 * binary driver skips the one that's already been setup by
1160 data = nvbios_rammapTe(bios, &ver, &hdr, &cnt, &len, &snr, &ssz);
1161 if (!data || hdr < 0x15)
1164 cnt = nv_ro08(bios, data + 0x14); /* guess at count */
1165 data = nv_ro32(bios, data + 0x10); /* guess u32... */
1166 save = nv_rd32(pfb, 0x10f65c);
1167 for (i = 0; i < cnt; i++) {
1168 nv_mask(pfb, 0x10f65c, 0x000000f0, i << 4);
1169 nvbios_exec(&(struct nvbios_init) {
1170 .subdev = nv_subdev(pfb),
1172 .offset = nv_ro32(bios, data), /* guess u32 */
1177 nv_wr32(pfb, 0x10f65c, save);
1179 switch (ram->base.type) {
1180 case NV_MEM_TYPE_GDDR5:
1181 for (i = 0; i < 0x30; i++) {
1182 nv_wr32(pfb, 0x10f968, 0x00000000 | (i << 8));
1183 nv_wr32(pfb, 0x10f920, 0x00000000 | train0[i % 12]);
1184 nv_wr32(pfb, 0x10f918, train1[i % 12]);
1185 nv_wr32(pfb, 0x10f920, 0x00000100 | train0[i % 12]);
1186 nv_wr32(pfb, 0x10f918, train1[i % 12]);
1188 nv_wr32(pfb, 0x10f96c, 0x00000000 | (i << 8));
1189 nv_wr32(pfb, 0x10f924, 0x00000000 | train0[i % 12]);
1190 nv_wr32(pfb, 0x10f91c, train1[i % 12]);
1191 nv_wr32(pfb, 0x10f924, 0x00000100 | train0[i % 12]);
1192 nv_wr32(pfb, 0x10f91c, train1[i % 12]);
1195 for (i = 0; i < 0x100; i++) {
1196 nv_wr32(pfb, 0x10f968, i);
1197 nv_wr32(pfb, 0x10f900, train1[2 + (i & 1)]);
1200 for (i = 0; i < 0x100; i++) {
1201 nv_wr32(pfb, 0x10f96c, i);
1202 nv_wr32(pfb, 0x10f900, train1[2 + (i & 1)]);
1213 nve0_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
1214 struct nouveau_oclass *oclass, void *data, u32 size,
1215 struct nouveau_object **pobject)
1217 struct nouveau_fb *pfb = nouveau_fb(parent);
1218 struct nouveau_bios *bios = nouveau_bios(pfb);
1219 struct nouveau_gpio *gpio = nouveau_gpio(pfb);
1220 struct dcb_gpio_func func;
1221 struct nve0_ram *ram;
1225 ret = nvc0_ram_create(parent, engine, oclass, &ram);
1226 *pobject = nv_object(ram);
1230 switch (ram->base.type) {
1231 case NV_MEM_TYPE_DDR3:
1232 case NV_MEM_TYPE_GDDR5:
1233 ram->base.calc = nve0_ram_calc;
1234 ram->base.prog = nve0_ram_prog;
1235 ram->base.tidy = nve0_ram_tidy;
1238 nv_warn(pfb, "reclocking of this RAM type is unsupported\n");
1242 /* calculate a mask of differently configured memory partitions,
1243 * because, of course reclocking wasn't complicated enough
1244 * already without having to treat some of them differently to
1247 ram->parts = nv_rd32(pfb, 0x022438);
1248 ram->pmask = nv_rd32(pfb, 0x022554);
1250 for (i = 0, tmp = 0; i < ram->parts; i++) {
1251 if (!(ram->pmask & (1 << i))) {
1252 u32 cfg1 = nv_rd32(pfb, 0x110204 + (i * 0x1000));
1253 if (tmp && tmp != cfg1) {
1254 ram->pnuts |= (1 << i);
1261 // parse bios data for both pll's
1262 ret = nvbios_pll_parse(bios, 0x0c, &ram->fuc.refpll);
1264 nv_error(pfb, "mclk refpll data not found\n");
1268 ret = nvbios_pll_parse(bios, 0x04, &ram->fuc.mempll);
1270 nv_error(pfb, "mclk pll data not found\n");
1274 ret = gpio->find(gpio, 0, 0x18, DCB_GPIO_UNUSED, &func);
1276 ram->fuc.r_gpioMV = ramfuc_reg(0x00d610 + (func.line * 0x04));
1277 ram->fuc.r_funcMV[0] = (func.log[0] ^ 2) << 12;
1278 ram->fuc.r_funcMV[1] = (func.log[1] ^ 2) << 12;
1281 ret = gpio->find(gpio, 0, 0x2e, DCB_GPIO_UNUSED, &func);
1283 ram->fuc.r_gpio2E = ramfuc_reg(0x00d610 + (func.line * 0x04));
1284 ram->fuc.r_func2E[0] = (func.log[0] ^ 2) << 12;
1285 ram->fuc.r_func2E[1] = (func.log[1] ^ 2) << 12;
1288 ram->fuc.r_gpiotrig = ramfuc_reg(0x00d604);
1290 ram->fuc.r_0x132020 = ramfuc_reg(0x132020);
1291 ram->fuc.r_0x132028 = ramfuc_reg(0x132028);
1292 ram->fuc.r_0x132024 = ramfuc_reg(0x132024);
1293 ram->fuc.r_0x132030 = ramfuc_reg(0x132030);
1294 ram->fuc.r_0x132034 = ramfuc_reg(0x132034);
1295 ram->fuc.r_0x132000 = ramfuc_reg(0x132000);
1296 ram->fuc.r_0x132004 = ramfuc_reg(0x132004);
1297 ram->fuc.r_0x132040 = ramfuc_reg(0x132040);
1299 ram->fuc.r_0x10f248 = ramfuc_reg(0x10f248);
1300 ram->fuc.r_0x10f290 = ramfuc_reg(0x10f290);
1301 ram->fuc.r_0x10f294 = ramfuc_reg(0x10f294);
1302 ram->fuc.r_0x10f298 = ramfuc_reg(0x10f298);
1303 ram->fuc.r_0x10f29c = ramfuc_reg(0x10f29c);
1304 ram->fuc.r_0x10f2a0 = ramfuc_reg(0x10f2a0);
1305 ram->fuc.r_0x10f2a4 = ramfuc_reg(0x10f2a4);
1306 ram->fuc.r_0x10f2a8 = ramfuc_reg(0x10f2a8);
1307 ram->fuc.r_0x10f2ac = ramfuc_reg(0x10f2ac);
1308 ram->fuc.r_0x10f2cc = ramfuc_reg(0x10f2cc);
1309 ram->fuc.r_0x10f2e8 = ramfuc_reg(0x10f2e8);
1310 ram->fuc.r_0x10f250 = ramfuc_reg(0x10f250);
1311 ram->fuc.r_0x10f24c = ramfuc_reg(0x10f24c);
1312 ram->fuc.r_0x10fec4 = ramfuc_reg(0x10fec4);
1313 ram->fuc.r_0x10fec8 = ramfuc_reg(0x10fec8);
1314 ram->fuc.r_0x10f604 = ramfuc_reg(0x10f604);
1315 ram->fuc.r_0x10f614 = ramfuc_reg(0x10f614);
1316 ram->fuc.r_0x10f610 = ramfuc_reg(0x10f610);
1317 ram->fuc.r_0x100770 = ramfuc_reg(0x100770);
1318 ram->fuc.r_0x100778 = ramfuc_reg(0x100778);
1319 ram->fuc.r_0x10f224 = ramfuc_reg(0x10f224);
1321 ram->fuc.r_0x10f870 = ramfuc_reg(0x10f870);
1322 ram->fuc.r_0x10f698 = ramfuc_reg(0x10f698);
1323 ram->fuc.r_0x10f694 = ramfuc_reg(0x10f694);
1324 ram->fuc.r_0x10f6b8 = ramfuc_reg(0x10f6b8);
1325 ram->fuc.r_0x10f808 = ramfuc_reg(0x10f808);
1326 ram->fuc.r_0x10f670 = ramfuc_reg(0x10f670);
1327 ram->fuc.r_0x10f60c = ramfuc_reg(0x10f60c);
1328 ram->fuc.r_0x10f830 = ramfuc_reg(0x10f830);
1329 ram->fuc.r_0x1373ec = ramfuc_reg(0x1373ec);
1330 ram->fuc.r_0x10f800 = ramfuc_reg(0x10f800);
1331 ram->fuc.r_0x10f82c = ramfuc_reg(0x10f82c);
1333 ram->fuc.r_0x10f978 = ramfuc_reg(0x10f978);
1334 ram->fuc.r_0x10f910 = ramfuc_reg(0x10f910);
1335 ram->fuc.r_0x10f914 = ramfuc_reg(0x10f914);
1337 switch (ram->base.type) {
1338 case NV_MEM_TYPE_GDDR5:
1339 ram->fuc.r_mr[0] = ramfuc_reg(0x10f300);
1340 ram->fuc.r_mr[1] = ramfuc_reg(0x10f330);
1341 ram->fuc.r_mr[2] = ramfuc_reg(0x10f334);
1342 ram->fuc.r_mr[3] = ramfuc_reg(0x10f338);
1343 ram->fuc.r_mr[4] = ramfuc_reg(0x10f33c);
1344 ram->fuc.r_mr[5] = ramfuc_reg(0x10f340);
1345 ram->fuc.r_mr[6] = ramfuc_reg(0x10f344);
1346 ram->fuc.r_mr[7] = ramfuc_reg(0x10f348);
1347 ram->fuc.r_mr[8] = ramfuc_reg(0x10f354);
1348 ram->fuc.r_mr[15] = ramfuc_reg(0x10f34c);
1350 case NV_MEM_TYPE_DDR3:
1351 ram->fuc.r_mr[0] = ramfuc_reg(0x10f300);
1352 ram->fuc.r_mr[2] = ramfuc_reg(0x10f320);
1358 ram->fuc.r_0x62c000 = ramfuc_reg(0x62c000);
1359 ram->fuc.r_0x10f200 = ramfuc_reg(0x10f200);
1360 ram->fuc.r_0x10f210 = ramfuc_reg(0x10f210);
1361 ram->fuc.r_0x10f310 = ramfuc_reg(0x10f310);
1362 ram->fuc.r_0x10f314 = ramfuc_reg(0x10f314);
1363 ram->fuc.r_0x10f318 = ramfuc_reg(0x10f318);
1364 ram->fuc.r_0x10f090 = ramfuc_reg(0x10f090);
1365 ram->fuc.r_0x10f69c = ramfuc_reg(0x10f69c);
1366 ram->fuc.r_0x10f824 = ramfuc_reg(0x10f824);
1367 ram->fuc.r_0x1373f0 = ramfuc_reg(0x1373f0);
1368 ram->fuc.r_0x1373f4 = ramfuc_reg(0x1373f4);
1369 ram->fuc.r_0x137320 = ramfuc_reg(0x137320);
1370 ram->fuc.r_0x10f65c = ramfuc_reg(0x10f65c);
1371 ram->fuc.r_0x10f6bc = ramfuc_reg(0x10f6bc);
1372 ram->fuc.r_0x100710 = ramfuc_reg(0x100710);
1373 ram->fuc.r_0x100750 = ramfuc_reg(0x100750);
1377 struct nouveau_oclass
1380 .ofuncs = &(struct nouveau_ofuncs) {
1381 .ctor = nve0_ram_ctor,
1382 .dtor = _nouveau_ram_dtor,
1383 .init = nve0_ram_init,
1384 .fini = _nouveau_ram_fini,