2 * Copyright 2013 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <subdev/gpio.h>
27 #include <subdev/bios.h>
28 #include <subdev/bios/pll.h>
29 #include <subdev/bios/init.h>
30 #include <subdev/bios/rammap.h>
31 #include <subdev/bios/timing.h>
33 #include <subdev/clock.h>
34 #include <subdev/clock/pll.h>
36 #include <subdev/timer.h>
38 #include <core/option.h>
44 /* binary driver only executes this path if the condition (a) is true
45 * for any configuration (combination of rammap+ramcfg+timing) that
46 * can be reached on a given card. for now, we will execute the branch
47 * unconditionally in the hope that a "false everywhere" in the bios
48 * tables doesn't actually mean "don't touch this".
55 struct nvbios_pll refpll;
56 struct nvbios_pll mempll;
58 struct ramfuc_reg r_gpioMV;
60 struct ramfuc_reg r_gpio2E;
62 struct ramfuc_reg r_gpiotrig;
64 struct ramfuc_reg r_0x132020;
65 struct ramfuc_reg r_0x132028;
66 struct ramfuc_reg r_0x132024;
67 struct ramfuc_reg r_0x132030;
68 struct ramfuc_reg r_0x132034;
69 struct ramfuc_reg r_0x132000;
70 struct ramfuc_reg r_0x132004;
71 struct ramfuc_reg r_0x132040;
73 struct ramfuc_reg r_0x10f248;
74 struct ramfuc_reg r_0x10f290;
75 struct ramfuc_reg r_0x10f294;
76 struct ramfuc_reg r_0x10f298;
77 struct ramfuc_reg r_0x10f29c;
78 struct ramfuc_reg r_0x10f2a0;
79 struct ramfuc_reg r_0x10f2a4;
80 struct ramfuc_reg r_0x10f2a8;
81 struct ramfuc_reg r_0x10f2ac;
82 struct ramfuc_reg r_0x10f2cc;
83 struct ramfuc_reg r_0x10f2e8;
84 struct ramfuc_reg r_0x10f250;
85 struct ramfuc_reg r_0x10f24c;
86 struct ramfuc_reg r_0x10fec4;
87 struct ramfuc_reg r_0x10fec8;
88 struct ramfuc_reg r_0x10f604;
89 struct ramfuc_reg r_0x10f614;
90 struct ramfuc_reg r_0x10f610;
91 struct ramfuc_reg r_0x100770;
92 struct ramfuc_reg r_0x100778;
93 struct ramfuc_reg r_0x10f224;
95 struct ramfuc_reg r_0x10f870;
96 struct ramfuc_reg r_0x10f698;
97 struct ramfuc_reg r_0x10f694;
98 struct ramfuc_reg r_0x10f6b8;
99 struct ramfuc_reg r_0x10f808;
100 struct ramfuc_reg r_0x10f670;
101 struct ramfuc_reg r_0x10f60c;
102 struct ramfuc_reg r_0x10f830;
103 struct ramfuc_reg r_0x1373ec;
104 struct ramfuc_reg r_0x10f800;
105 struct ramfuc_reg r_0x10f82c;
107 struct ramfuc_reg r_0x10f978;
108 struct ramfuc_reg r_0x10f910;
109 struct ramfuc_reg r_0x10f914;
111 struct ramfuc_reg r_mr[16]; /* MR0 - MR8, MR15 */
113 struct ramfuc_reg r_0x62c000;
115 struct ramfuc_reg r_0x10f200;
117 struct ramfuc_reg r_0x10f210;
118 struct ramfuc_reg r_0x10f310;
119 struct ramfuc_reg r_0x10f314;
120 struct ramfuc_reg r_0x10f318;
121 struct ramfuc_reg r_0x10f090;
122 struct ramfuc_reg r_0x10f69c;
123 struct ramfuc_reg r_0x10f824;
124 struct ramfuc_reg r_0x1373f0;
125 struct ramfuc_reg r_0x1373f4;
126 struct ramfuc_reg r_0x137320;
127 struct ramfuc_reg r_0x10f65c;
128 struct ramfuc_reg r_0x10f6bc;
129 struct ramfuc_reg r_0x100710;
130 struct ramfuc_reg r_0x100750;
134 struct nouveau_ram base;
135 struct nve0_ramfuc fuc;
147 /*******************************************************************************
149 ******************************************************************************/
151 nve0_ram_train(struct nve0_ramfuc *fuc, u32 mask, u32 data)
153 struct nve0_ram *ram = container_of(fuc, typeof(*ram), fuc);
154 u32 addr = 0x110974, i;
156 ram_mask(fuc, 0x10f910, mask, data);
157 ram_mask(fuc, 0x10f914, mask, data);
159 for (i = 0; (data & 0x80000000) && i < ram->parts; addr += 0x1000, i++) {
160 if (ram->pmask & (1 << i))
162 ram_wait(fuc, addr, 0x0000000f, 0x00000000, 500000);
167 r1373f4_init(struct nve0_ramfuc *fuc)
169 struct nve0_ram *ram = container_of(fuc, typeof(*ram), fuc);
170 const u32 mcoef = ((--ram->P2 << 28) | (ram->N2 << 8) | ram->M2);
171 const u32 rcoef = (( ram->P1 << 16) | (ram->N1 << 8) | ram->M1);
172 const u32 runk0 = ram->fN1 << 16;
173 const u32 runk1 = ram->fN1;
175 if (ram->from == 2) {
176 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00001100);
177 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00000010);
179 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00010010);
182 ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000000);
183 ram_mask(fuc, 0x1373f4, 0x00000010, 0x00000000);
185 /* (re)program refpll, if required */
186 if ((ram_rd32(fuc, 0x132024) & 0xffffffff) != rcoef ||
187 (ram_rd32(fuc, 0x132034) & 0x0000ffff) != runk1) {
188 ram_mask(fuc, 0x132000, 0x00000001, 0x00000000);
189 ram_mask(fuc, 0x132020, 0x00000001, 0x00000000);
190 ram_wr32(fuc, 0x137320, 0x00000000);
191 ram_mask(fuc, 0x132030, 0xffff0000, runk0);
192 ram_mask(fuc, 0x132034, 0x0000ffff, runk1);
193 ram_wr32(fuc, 0x132024, rcoef);
194 ram_mask(fuc, 0x132028, 0x00080000, 0x00080000);
195 ram_mask(fuc, 0x132020, 0x00000001, 0x00000001);
196 ram_wait(fuc, 0x137390, 0x00020000, 0x00020000, 64000);
197 ram_mask(fuc, 0x132028, 0x00080000, 0x00000000);
200 /* (re)program mempll, if required */
201 if (ram->mode == 2) {
202 ram_mask(fuc, 0x1373f4, 0x00010000, 0x00000000);
203 ram_mask(fuc, 0x132000, 0x00000001, 0x00000000);
204 ram_mask(fuc, 0x132004, 0x103fffff, mcoef);
205 ram_mask(fuc, 0x132000, 0x00000001, 0x00000001);
206 ram_wait(fuc, 0x137390, 0x00000002, 0x00000002, 64000);
207 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00001100);
209 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00010100);
212 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00000010);
216 r1373f4_fini(struct nve0_ramfuc *fuc, u32 ramcfg)
218 struct nve0_ram *ram = container_of(fuc, typeof(*ram), fuc);
219 struct nouveau_bios *bios = nouveau_bios(ram);
220 u8 v0 = (nv_ro08(bios, ramcfg + 0x03) & 0xc0) >> 6;
221 u8 v1 = (nv_ro08(bios, ramcfg + 0x03) & 0x30) >> 4;
224 tmp = ram_rd32(fuc, 0x1373ec) & ~0x00030000;
225 ram_wr32(fuc, 0x1373ec, tmp | (v1 << 16));
226 ram_mask(fuc, 0x1373f0, (~ram->mode & 3), 0x00000000);
227 if (ram->mode == 2) {
228 ram_mask(fuc, 0x1373f4, 0x00000003, 0x000000002);
229 ram_mask(fuc, 0x1373f4, 0x00001100, 0x000000000);
231 ram_mask(fuc, 0x1373f4, 0x00000003, 0x000000001);
232 ram_mask(fuc, 0x1373f4, 0x00010000, 0x000000000);
234 ram_mask(fuc, 0x10f800, 0x00000030, (v0 ^ v1) << 4);
238 nve0_ram_nuts(struct nve0_ram *ram, struct ramfuc_reg *reg,
239 u32 _mask, u32 _data, u32 _copy)
241 struct nve0_fb_priv *priv = (void *)nouveau_fb(ram);
242 struct ramfuc *fuc = &ram->fuc.base;
243 u32 addr = 0x110000 + (reg->addr[0] & 0xfff);
244 u32 mask = _mask | _copy;
245 u32 data = (_data & _mask) | (reg->data & _copy);
248 for (i = 0; i < 16; i++, addr += 0x1000) {
249 if (ram->pnuts & (1 << i)) {
250 u32 prev = nv_rd32(priv, addr);
251 u32 next = (prev & ~mask) | data;
252 nouveau_memx_wr32(fuc->memx, addr, next);
256 #define ram_nuts(s,r,m,d,c) \
257 nve0_ram_nuts((s), &(s)->fuc.r_##r, (m), (d), (c))
260 nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
262 struct nouveau_bios *bios = nouveau_bios(pfb);
263 struct nve0_ram *ram = (void *)pfb->ram;
264 struct nve0_ramfuc *fuc = &ram->fuc;
265 const u32 rammap = ram->base.rammap.data;
266 const u32 ramcfg = ram->base.ramcfg.data;
267 const u32 timing = ram->base.timing.data;
268 int vc = !(nv_ro08(bios, ramcfg + 0x02) & 0x08);
272 ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000);
273 ram_wr32(fuc, 0x62c000, 0x0f0f0000);
275 /* MR1: turn termination on early, for some reason.. */
276 if ((ram->base.mr[1] & 0x03c) != 0x030) {
277 ram_mask(fuc, mr[1], 0x03c, ram->base.mr[1] & 0x03c);
278 ram_nuts(ram, mr[1], 0x03c, ram->base.mr1_nuts & 0x03c, 0x000);
281 if (vc == 1 && ram_have(fuc, gpio2E)) {
282 u32 temp = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[1]);
283 if (temp != ram_rd32(fuc, gpio2E)) {
284 ram_wr32(fuc, gpiotrig, 1);
285 ram_nsec(fuc, 20000);
289 ram_mask(fuc, 0x10f200, 0x00000800, 0x00000000);
291 nve0_ram_train(fuc, 0x01020000, 0x000c0000);
293 ram_wr32(fuc, 0x10f210, 0x00000000); /* REFRESH_AUTO = 0 */
295 ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */
298 ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000);
299 ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */
300 ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000);
301 ram_wr32(fuc, 0x10f090, 0x00000061);
302 ram_wr32(fuc, 0x10f090, 0xc000007f);
305 ram_wr32(fuc, 0x10f698, 0x00000000);
306 ram_wr32(fuc, 0x10f69c, 0x00000000);
308 /*XXX: there does appear to be some kind of condition here, simply
309 * modifying these bits in the vbios from the default pl0
310 * entries shows no change. however, the data does appear to
311 * be correct and may be required for the transition back
315 if (ram_rd32(fuc, 0x10f978) & 0x00800000)
320 switch (nv_ro08(bios, ramcfg + 0x03) & 0xc0) {
321 case 0xc0: data &= ~0x00000040; break;
322 case 0x80: data &= ~0x00000100; break;
323 case 0x40: data &= ~0x80000000; break;
324 case 0x00: data &= ~0x00000400; break;
327 switch (nv_ro08(bios, ramcfg + 0x03) & 0x30) {
328 case 0x30: data &= ~0x00000020; break;
329 case 0x20: data &= ~0x00000080; break;
330 case 0x10: data &= ~0x00080000; break;
331 case 0x00: data &= ~0x00000200; break;
335 if (nv_ro08(bios, ramcfg + 0x02) & 0x80)
337 if (nv_ro08(bios, ramcfg + 0x02) & 0x40)
339 if (nv_ro08(bios, ramcfg + 0x07) & 0x10)
341 if (nv_ro08(bios, ramcfg + 0x07) & 0x08)
345 if (ram_rd32(fuc, 0x10f978) & 0x00800000)
348 ram_mask(fuc, 0x10f824, mask, data);
350 ram_mask(fuc, 0x132040, 0x00010000, 0x00000000);
352 if (ram->from == 2 && ram->mode != 2) {
353 ram_mask(fuc, 0x10f808, 0x00080000, 0x00000000);
354 ram_mask(fuc, 0x10f200, 0x00008000, 0x00008000);
355 ram_mask(fuc, 0x10f800, 0x00000000, 0x00000004);
356 ram_mask(fuc, 0x10f830, 0x00008000, 0x01040010);
357 ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000);
359 ram_mask(fuc, 0x1373f0, 0x00000002, 0x00000001);
360 r1373f4_fini(fuc, ramcfg);
361 ram_mask(fuc, 0x10f830, 0x00c00000, 0x00240001);
363 if (ram->from != 2 && ram->mode != 2) {
365 r1373f4_fini(fuc, ramcfg);
368 if (ram_have(fuc, gpioMV)) {
369 u32 temp = ram_mask(fuc, gpioMV, 0x3000, fuc->r_funcMV[mv]);
370 if (temp != ram_rd32(fuc, gpioMV)) {
371 ram_wr32(fuc, gpiotrig, 1);
372 ram_nsec(fuc, 64000);
376 if ( (nv_ro08(bios, ramcfg + 0x02) & 0x40) ||
377 (nv_ro08(bios, ramcfg + 0x07) & 0x10)) {
378 ram_mask(fuc, 0x132040, 0x00010000, 0x00010000);
379 ram_nsec(fuc, 20000);
382 if (ram->from != 2 && ram->mode == 2) {
383 ram_mask(fuc, 0x10f800, 0x00000004, 0x00000000);
384 ram_mask(fuc, 0x1373f0, 0x00000000, 0x00000002);
385 ram_mask(fuc, 0x10f830, 0x00800001, 0x00408010);
387 r1373f4_fini(fuc, ramcfg);
388 ram_mask(fuc, 0x10f808, 0x00000000, 0x00080000);
389 ram_mask(fuc, 0x10f200, 0x00808000, 0x00800000);
391 if (ram->from == 2 && ram->mode == 2) {
392 ram_mask(fuc, 0x10f800, 0x00000004, 0x00000000);
394 r1373f4_fini(fuc, ramcfg);
397 if (ram->mode != 2) /*XXX*/ {
398 if (nv_ro08(bios, ramcfg + 0x07) & 0x40)
399 ram_mask(fuc, 0x10f670, 0x80000000, 0x80000000);
402 data = (nv_ro08(bios, rammap + 0x11) & 0x0c) >> 2;
403 ram_wr32(fuc, 0x10f65c, 0x00000011 * data);
404 ram_wr32(fuc, 0x10f6b8, 0x01010101 * nv_ro08(bios, ramcfg + 0x09));
405 ram_wr32(fuc, 0x10f6bc, 0x01010101 * nv_ro08(bios, ramcfg + 0x09));
407 data = nv_ro08(bios, ramcfg + 0x04);
408 if (!(nv_ro08(bios, ramcfg + 0x07) & 0x08)) {
409 ram_wr32(fuc, 0x10f698, 0x01010101 * data);
410 ram_wr32(fuc, 0x10f69c, 0x01010101 * data);
413 if (ram->mode != 2) {
414 u32 temp = ram_rd32(fuc, 0x10f694) & ~0xff00ff00;
415 ram_wr32(fuc, 0x10f694, temp | (0x01000100 * data));
418 if (ram->mode == 2 && (nv_ro08(bios, ramcfg + 0x08) & 0x10))
422 ram_mask(fuc, 0x10f60c, 0x00000080, data);
426 if (!(nv_ro08(bios, ramcfg + 0x02) & 0x80))
428 if (!(nv_ro08(bios, ramcfg + 0x02) & 0x40))
430 if (!(nv_ro08(bios, ramcfg + 0x07) & 0x10))
432 if (!(nv_ro08(bios, ramcfg + 0x07) & 0x08))
436 ram_mask(fuc, 0x10f824, mask, data);
438 if (nv_ro08(bios, ramcfg + 0x01) & 0x08)
442 ram_mask(fuc, 0x10f200, 0x00001000, data);
444 if (ram_rd32(fuc, 0x10f670) & 0x80000000) {
445 ram_nsec(fuc, 10000);
446 ram_mask(fuc, 0x10f670, 0x80000000, 0x00000000);
449 if (nv_ro08(bios, ramcfg + 0x08) & 0x01)
453 ram_mask(fuc, 0x10f82c, 0x00100000, data);
456 if (nv_ro08(bios, ramcfg + 0x08) & 0x08)
458 if (nv_ro08(bios, ramcfg + 0x08) & 0x04)
460 if (nv_ro08(bios, ramcfg + 0x08) & 0x02)
462 ram_mask(fuc, 0x10f830, 0x00007000, data);
465 ram_mask(fuc, 0x10f248, 0xffffffff, nv_ro32(bios, timing + 0x28));
466 ram_mask(fuc, 0x10f290, 0xffffffff, nv_ro32(bios, timing + 0x00));
467 ram_mask(fuc, 0x10f294, 0xffffffff, nv_ro32(bios, timing + 0x04));
468 ram_mask(fuc, 0x10f298, 0xffffffff, nv_ro32(bios, timing + 0x08));
469 ram_mask(fuc, 0x10f29c, 0xffffffff, nv_ro32(bios, timing + 0x0c));
470 ram_mask(fuc, 0x10f2a0, 0xffffffff, nv_ro32(bios, timing + 0x10));
471 ram_mask(fuc, 0x10f2a4, 0xffffffff, nv_ro32(bios, timing + 0x14));
472 ram_mask(fuc, 0x10f2a8, 0xffffffff, nv_ro32(bios, timing + 0x18));
473 ram_mask(fuc, 0x10f2ac, 0xffffffff, nv_ro32(bios, timing + 0x1c));
474 ram_mask(fuc, 0x10f2cc, 0xffffffff, nv_ro32(bios, timing + 0x20));
475 ram_mask(fuc, 0x10f2e8, 0xffffffff, nv_ro32(bios, timing + 0x24));
477 data = mask = 0x00000000;
478 if (NOTE00(ramcfg_02_03 != 0)) {
479 data |= (nv_ro08(bios, ramcfg + 0x02) & 0x03) << 8;
482 if (NOTE00(ramcfg_01_10)) {
483 if (nv_ro08(bios, ramcfg + 0x01) & 0x10)
487 ram_mask(fuc, 0x10f604, mask, data);
489 data = mask = 0x00000000;
490 if (NOTE00(timing_30_07 != 0)) {
491 data |= (nv_ro08(bios, timing + 0x30) & 0x07) << 28;
494 if (NOTE00(ramcfg_01_01)) {
495 if (nv_ro08(bios, ramcfg + 0x01) & 0x01)
499 ram_mask(fuc, 0x10f614, mask, data);
501 data = mask = 0x00000000;
502 if (NOTE00(timing_30_07 != 0)) {
503 data |= (nv_ro08(bios, timing + 0x30) & 0x07) << 28;
506 if (NOTE00(ramcfg_01_02)) {
507 if (nv_ro08(bios, ramcfg + 0x01) & 0x02)
511 ram_mask(fuc, 0x10f610, mask, data);
515 if (!(nv_ro08(bios, ramcfg + 0x01) & 0x04))
517 if (!(nv_ro08(bios, ramcfg + 0x07) & 0x80))
519 /*XXX: see note above about there probably being some condition
520 * for the 10f824 stuff that uses ramcfg 3...
522 if ( (nv_ro08(bios, ramcfg + 0x03) & 0xf0)) {
523 if (nv_ro08(bios, rammap + 0x08) & 0x0c) {
524 if (!(nv_ro08(bios, ramcfg + 0x07) & 0x80))
535 ram_mask(fuc, 0x10f808, mask, data);
537 data = nv_ro08(bios, ramcfg + 0x03) & 0x0f;
538 ram_wr32(fuc, 0x10f870, 0x11111111 * data);
540 data = mask = 0x00000000;
541 if (NOTE00(ramcfg_02_03 != 0)) {
542 data |= nv_ro08(bios, ramcfg + 0x02) & 0x03;
545 if (NOTE00(ramcfg_01_10)) {
546 if (nv_ro08(bios, ramcfg + 0x01) & 0x10)
551 if ((ram_mask(fuc, 0x100770, mask, data) & mask & 4) != (data & 4)) {
552 ram_mask(fuc, 0x100750, 0x00000008, 0x00000008);
553 ram_wr32(fuc, 0x100710, 0x00000000);
554 ram_wait(fuc, 0x100710, 0x80000000, 0x80000000, 200000);
557 data = (nv_ro08(bios, timing + 0x30) & 0x07) << 8;
558 if (nv_ro08(bios, ramcfg + 0x01) & 0x01)
560 ram_mask(fuc, 0x100778, 0x00000700, data);
562 data = nv_ro16(bios, timing + 0x2c);
563 ram_mask(fuc, 0x10f250, 0x000003f0, (data & 0x003f) << 4);
564 ram_mask(fuc, 0x10f24c, 0x7f000000, (data & 0x1fc0) << 18);
566 data = nv_ro08(bios, timing + 0x30);
567 ram_mask(fuc, 0x10f224, 0x001f0000, (data & 0xf8) << 13);
569 data = nv_ro16(bios, timing + 0x31);
570 ram_mask(fuc, 0x10fec4, 0x041e0f07, (data & 0x0800) << 15 |
571 (data & 0x0780) << 10 |
572 (data & 0x0078) << 5 |
574 ram_mask(fuc, 0x10fec8, 0x00000027, (data & 0x8000) >> 10 |
575 (data & 0x7000) >> 12);
577 ram_wr32(fuc, 0x10f090, 0x4000007e);
579 ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */
580 ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */
581 ram_wr32(fuc, 0x10f210, 0x80000000); /* REFRESH_AUTO = 1 */
583 if ((nv_ro08(bios, ramcfg + 0x08) & 0x10) && (ram->mode == 2) /*XXX*/) {
584 u32 temp = ram_mask(fuc, 0x10f294, 0xff000000, 0x24000000);
585 nve0_ram_train(fuc, 0xbc0e0000, 0xa4010000); /*XXX*/
587 ram_wr32(fuc, 0x10f294, temp);
590 ram_mask(fuc, mr[3], 0xfff, ram->base.mr[3]);
591 ram_wr32(fuc, mr[0], ram->base.mr[0]);
592 ram_mask(fuc, mr[8], 0xfff, ram->base.mr[8]);
594 ram_mask(fuc, mr[1], 0xfff, ram->base.mr[1]);
595 ram_mask(fuc, mr[5], 0xfff, ram->base.mr[5] & ~0x004); /* LP3 later */
596 ram_mask(fuc, mr[6], 0xfff, ram->base.mr[6]);
597 ram_mask(fuc, mr[7], 0xfff, ram->base.mr[7]);
599 if (vc == 0 && ram_have(fuc, gpio2E)) {
600 u32 temp = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[0]);
601 if (temp != ram_rd32(fuc, gpio2E)) {
602 ram_wr32(fuc, gpiotrig, 1);
603 ram_nsec(fuc, 20000);
607 ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000);
608 ram_wr32(fuc, 0x10f318, 0x00000001); /* NOP? */
609 ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000);
611 ram_nuts(ram, 0x10f200, 0x00808800, 0x00000000, 0x00808800);
613 data = ram_rd32(fuc, 0x10f978);
616 if (!(nv_ro08(bios, ramcfg + 0x07) & 0x08)) {
617 if (!(nv_ro08(bios, ramcfg + 0x07) & 0x04))
624 ram_wr32(fuc, 0x10f978, data);
626 if (ram->mode == 1) {
627 data = ram_rd32(fuc, 0x10f830) | 0x00000001;
628 ram_wr32(fuc, 0x10f830, data);
631 if (!(nv_ro08(bios, ramcfg + 0x07) & 0x08)) {
633 if ( (nv_ro08(bios, ramcfg + 0x07) & 0x04))
635 if (!(nv_ro08(bios, rammap + 0x08) & 0x10))
640 nve0_ram_train(fuc, 0xbc0f0000, data);
643 if (ram->mode == 2) { /*XXX*/
644 ram_mask(fuc, 0x10f800, 0x00000004, 0x00000004);
647 /* MR5: (re)enable LP3 if necessary
648 * XXX: need to find the switch, keeping off for now
650 ram_mask(fuc, mr[5], 0xfff, ram->base.mr[5]);
652 if (ram->mode != 2) {
653 ram_mask(fuc, 0x10f830, 0x01000000, 0x01000000);
654 ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000);
657 if (nv_ro08(bios, ramcfg + 0x07) & 0x02)
658 nve0_ram_train(fuc, 0x80020000, 0x01000000);
660 ram_wr32(fuc, 0x62c000, 0x0f0f0f00);
662 if (nv_ro08(bios, rammap + 0x08) & 0x01)
666 ram_mask(fuc, 0x10f200, 0x00000800, data);
667 ram_nuts(ram, 0x10f200, 0x00808800, data, 0x00808800);
671 /*******************************************************************************
673 ******************************************************************************/
676 nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq)
678 struct nouveau_bios *bios = nouveau_bios(pfb);
679 struct nve0_ram *ram = (void *)pfb->ram;
680 struct nve0_ramfuc *fuc = &ram->fuc;
681 const u32 rcoef = (( ram->P1 << 16) | (ram->N1 << 8) | ram->M1);
682 const u32 runk0 = ram->fN1 << 16;
683 const u32 runk1 = ram->fN1;
684 const u32 rammap = ram->base.rammap.data;
685 const u32 ramcfg = ram->base.ramcfg.data;
686 const u32 timing = ram->base.timing.data;
687 int vc = !(nv_ro08(bios, ramcfg + 0x02) & 0x08);
691 ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000);
692 ram_wr32(fuc, 0x62c000, 0x0f0f0000);
694 if (vc == 1 && ram_have(fuc, gpio2E)) {
695 u32 temp = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[1]);
696 if (temp != ram_rd32(fuc, gpio2E)) {
697 ram_wr32(fuc, gpiotrig, 1);
698 ram_nsec(fuc, 20000);
702 ram_mask(fuc, 0x10f200, 0x00000800, 0x00000000);
703 if ((nv_ro08(bios, ramcfg + 0x03) & 0xf0))
704 ram_mask(fuc, 0x10f808, 0x04000000, 0x04000000);
706 ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */
707 ram_wr32(fuc, 0x10f210, 0x00000000); /* REFRESH_AUTO = 0 */
708 ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */
709 ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000);
710 ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */
711 ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000);
714 ram_wr32(fuc, 0x10f090, 0x00000060);
715 ram_wr32(fuc, 0x10f090, 0xc000007e);
717 /*XXX: there does appear to be some kind of condition here, simply
718 * modifying these bits in the vbios from the default pl0
719 * entries shows no change. however, the data does appear to
720 * be correct and may be required for the transition back
728 switch (nv_ro08(bios, ramcfg + 0x03) & 0xc0) {
729 case 0xc0: data &= ~0x00000040; break;
730 case 0x80: data &= ~0x00000100; break;
731 case 0x40: data &= ~0x80000000; break;
732 case 0x00: data &= ~0x00000400; break;
735 switch (nv_ro08(bios, ramcfg + 0x03) & 0x30) {
736 case 0x30: data &= ~0x00000020; break;
737 case 0x20: data &= ~0x00000080; break;
738 case 0x10: data &= ~0x00080000; break;
739 case 0x00: data &= ~0x00000200; break;
743 if (nv_ro08(bios, ramcfg + 0x02) & 0x80)
745 if (nv_ro08(bios, ramcfg + 0x02) & 0x40)
747 if (nv_ro08(bios, ramcfg + 0x07) & 0x10)
749 if (nv_ro08(bios, ramcfg + 0x07) & 0x08)
753 ram_mask(fuc, 0x10f824, mask, data);
755 ram_mask(fuc, 0x132040, 0x00010000, 0x00000000);
757 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00010010);
758 data = ram_rd32(fuc, 0x1373ec) & ~0x00030000;
759 data |= (nv_ro08(bios, ramcfg + 0x03) & 0x30) << 12;
760 ram_wr32(fuc, 0x1373ec, data);
761 ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000000);
762 ram_mask(fuc, 0x1373f4, 0x00000010, 0x00000000);
764 /* (re)program refpll, if required */
765 if ((ram_rd32(fuc, 0x132024) & 0xffffffff) != rcoef ||
766 (ram_rd32(fuc, 0x132034) & 0x0000ffff) != runk1) {
767 ram_mask(fuc, 0x132000, 0x00000001, 0x00000000);
768 ram_mask(fuc, 0x132020, 0x00000001, 0x00000000);
769 ram_wr32(fuc, 0x137320, 0x00000000);
770 ram_mask(fuc, 0x132030, 0xffff0000, runk0);
771 ram_mask(fuc, 0x132034, 0x0000ffff, runk1);
772 ram_wr32(fuc, 0x132024, rcoef);
773 ram_mask(fuc, 0x132028, 0x00080000, 0x00080000);
774 ram_mask(fuc, 0x132020, 0x00000001, 0x00000001);
775 ram_wait(fuc, 0x137390, 0x00020000, 0x00020000, 64000);
776 ram_mask(fuc, 0x132028, 0x00080000, 0x00000000);
779 ram_mask(fuc, 0x1373f4, 0x00000010, 0x00000010);
780 ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000001);
781 ram_mask(fuc, 0x1373f4, 0x00010000, 0x00000000);
783 if (ram_have(fuc, gpioMV)) {
784 u32 temp = ram_mask(fuc, gpioMV, 0x3000, fuc->r_funcMV[mv]);
785 if (temp != ram_rd32(fuc, gpioMV)) {
786 ram_wr32(fuc, gpiotrig, 1);
787 ram_nsec(fuc, 64000);
791 if ( (nv_ro08(bios, ramcfg + 0x02) & 0x40) ||
792 (nv_ro08(bios, ramcfg + 0x07) & 0x10)) {
793 ram_mask(fuc, 0x132040, 0x00010000, 0x00010000);
794 ram_nsec(fuc, 20000);
797 if (ram->mode != 2) /*XXX*/ {
798 if (nv_ro08(bios, ramcfg + 0x07) & 0x40)
799 ram_mask(fuc, 0x10f670, 0x80000000, 0x80000000);
802 data = (nv_ro08(bios, rammap + 0x11) & 0x0c) >> 2;
803 ram_wr32(fuc, 0x10f65c, 0x00000011 * data);
804 ram_wr32(fuc, 0x10f6b8, 0x01010101 * nv_ro08(bios, ramcfg + 0x09));
805 ram_wr32(fuc, 0x10f6bc, 0x01010101 * nv_ro08(bios, ramcfg + 0x09));
809 if (!(nv_ro08(bios, ramcfg + 0x02) & 0x80))
811 if (!(nv_ro08(bios, ramcfg + 0x02) & 0x40))
813 if (!(nv_ro08(bios, ramcfg + 0x07) & 0x10))
815 if (!(nv_ro08(bios, ramcfg + 0x07) & 0x08))
819 ram_mask(fuc, 0x10f824, mask, data);
822 if (nv_ro08(bios, ramcfg + 0x08) & 0x01)
826 ram_mask(fuc, 0x10f82c, 0x00100000, data);
829 ram_mask(fuc, 0x10f248, 0xffffffff, nv_ro32(bios, timing + 0x28));
830 ram_mask(fuc, 0x10f290, 0xffffffff, nv_ro32(bios, timing + 0x00));
831 ram_mask(fuc, 0x10f294, 0xffffffff, nv_ro32(bios, timing + 0x04));
832 ram_mask(fuc, 0x10f298, 0xffffffff, nv_ro32(bios, timing + 0x08));
833 ram_mask(fuc, 0x10f29c, 0xffffffff, nv_ro32(bios, timing + 0x0c));
834 ram_mask(fuc, 0x10f2a0, 0xffffffff, nv_ro32(bios, timing + 0x10));
835 ram_mask(fuc, 0x10f2a4, 0xffffffff, nv_ro32(bios, timing + 0x14));
836 ram_mask(fuc, 0x10f2a8, 0xffffffff, nv_ro32(bios, timing + 0x18));
837 ram_mask(fuc, 0x10f2ac, 0xffffffff, nv_ro32(bios, timing + 0x1c));
838 ram_mask(fuc, 0x10f2cc, 0xffffffff, nv_ro32(bios, timing + 0x20));
839 ram_mask(fuc, 0x10f2e8, 0xffffffff, nv_ro32(bios, timing + 0x24));
843 if (!(nv_ro08(bios, ramcfg + 0x01) & 0x04))
845 if (!(nv_ro08(bios, ramcfg + 0x07) & 0x80))
847 /*XXX: see note above about there probably being some condition
848 * for the 10f824 stuff that uses ramcfg 3...
850 if ( (nv_ro08(bios, ramcfg + 0x03) & 0xf0)) {
851 if (nv_ro08(bios, rammap + 0x08) & 0x0c) {
852 if (!(nv_ro08(bios, ramcfg + 0x07) & 0x80))
864 ram_mask(fuc, 0x10f808, mask, data);
866 data = nv_ro08(bios, ramcfg + 0x03) & 0x0f;
867 ram_wr32(fuc, 0x10f870, 0x11111111 * data);
869 data = nv_ro16(bios, timing + 0x2c);
870 ram_mask(fuc, 0x10f250, 0x000003f0, (data & 0x003f) << 4);
872 if (((nv_ro32(bios, timing + 0x2c) & 0x00001fc0) >> 6) >
873 ((nv_ro32(bios, timing + 0x28) & 0x7f000000) >> 24))
874 data = (nv_ro32(bios, timing + 0x2c) & 0x00001fc0) >> 6;
876 data = (nv_ro32(bios, timing + 0x28) & 0x1f000000) >> 24;
877 ram_mask(fuc, 0x10f24c, 0x7f000000, data << 24);
879 data = nv_ro08(bios, timing + 0x30);
880 ram_mask(fuc, 0x10f224, 0x001f0000, (data & 0xf8) << 13);
882 ram_wr32(fuc, 0x10f090, 0x4000007f);
885 ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */
886 ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */
887 ram_wr32(fuc, 0x10f210, 0x80000000); /* REFRESH_AUTO = 1 */
890 ram_nuke(fuc, mr[0]);
891 ram_mask(fuc, mr[0], 0x100, 0x100);
892 ram_mask(fuc, mr[0], 0x100, 0x000);
894 ram_mask(fuc, mr[2], 0xfff, ram->base.mr[2]);
895 ram_wr32(fuc, mr[0], ram->base.mr[0]);
898 ram_nuke(fuc, mr[0]);
899 ram_mask(fuc, mr[0], 0x100, 0x100);
900 ram_mask(fuc, mr[0], 0x100, 0x000);
902 if (vc == 0 && ram_have(fuc, gpio2E)) {
903 u32 temp = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[0]);
904 if (temp != ram_rd32(fuc, gpio2E)) {
905 ram_wr32(fuc, gpiotrig, 1);
906 ram_nsec(fuc, 20000);
910 if (ram->mode != 2) {
911 ram_mask(fuc, 0x10f830, 0x01000000, 0x01000000);
912 ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000);
915 ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000);
916 ram_wr32(fuc, 0x10f318, 0x00000001); /* NOP? */
917 ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000);
920 ram_wr32(fuc, 0x62c000, 0x0f0f0f00);
922 if (nv_ro08(bios, rammap + 0x08) & 0x01)
926 ram_mask(fuc, 0x10f200, 0x00000800, data);
930 /*******************************************************************************
932 ******************************************************************************/
935 nve0_ram_calc(struct nouveau_fb *pfb, u32 freq)
937 struct nouveau_bios *bios = nouveau_bios(pfb);
938 struct nve0_ram *ram = (void *)pfb->ram;
939 struct nve0_ramfuc *fuc = &ram->fuc;
940 int ret, refclk, strap, i;
944 /* lookup memory config data relevant to the target frequency */
945 ram->base.rammap.data = nvbios_rammap_match(bios, freq / 1000,
946 &ram->base.rammap.version,
947 &ram->base.rammap.size, &cnt,
948 &ram->base.ramcfg.size);
949 if (!ram->base.rammap.data || ram->base.rammap.version != 0x11 ||
950 ram->base.rammap.size < 0x09) {
951 nv_error(pfb, "invalid/missing rammap entry\n");
955 /* locate specific data set for the attached memory */
956 strap = nvbios_ramcfg_index(bios);
958 nv_error(pfb, "invalid ramcfg strap\n");
962 ram->base.ramcfg.version = ram->base.rammap.version;
963 ram->base.ramcfg.data = ram->base.rammap.data + ram->base.rammap.size +
964 (ram->base.ramcfg.size * strap);
965 if (!ram->base.ramcfg.data || ram->base.ramcfg.version != 0x11 ||
966 ram->base.ramcfg.size < 0x08) {
967 nv_error(pfb, "invalid/missing ramcfg entry\n");
971 /* lookup memory timings, if bios says they're present */
972 strap = nv_ro08(bios, ram->base.ramcfg.data + 0x00);
974 ram->base.timing.data =
975 nvbios_timingEe(bios, strap, &ram->base.timing.version,
976 &ram->base.timing.size, &cnt, &len);
977 if (!ram->base.timing.data ||
978 ram->base.timing.version != 0x20 ||
979 ram->base.timing.size < 0x33) {
980 nv_error(pfb, "invalid/missing timing entry\n");
984 ram->base.timing.data = 0;
987 ret = ram_init(fuc, pfb);
991 ram->mode = (freq > fuc->refpll.vco1.max_freq) ? 2 : 1;
992 ram->from = ram_rd32(fuc, 0x1373f4) & 0x0000000f;
994 /* XXX: this is *not* what nvidia do. on fermi nvidia generally
995 * select, based on some unknown condition, one of the two possible
996 * reference frequencies listed in the vbios table for mempll and
997 * program refpll to that frequency.
999 * so far, i've seen very weird values being chosen by nvidia on
1000 * kepler boards, no idea how/why they're chosen.
1004 refclk = fuc->mempll.refclk;
1006 /* calculate refpll coefficients */
1007 ret = nva3_pll_calc(nv_subdev(pfb), &fuc->refpll, refclk, &ram->N1,
1008 &ram->fN1, &ram->M1, &ram->P1);
1009 fuc->mempll.refclk = ret;
1011 nv_error(pfb, "unable to calc refpll\n");
1015 /* calculate mempll coefficients, if we're using it */
1016 if (ram->mode == 2) {
1017 /* post-divider doesn't work... the reg takes the values but
1018 * appears to completely ignore it. there *is* a bit at
1019 * bit 28 that appears to divide the clock by 2 if set.
1021 fuc->mempll.min_p = 1;
1022 fuc->mempll.max_p = 2;
1024 ret = nva3_pll_calc(nv_subdev(pfb), &fuc->mempll, freq,
1025 &ram->N2, NULL, &ram->M2, &ram->P2);
1027 nv_error(pfb, "unable to calc mempll\n");
1032 for (i = 0; i < ARRAY_SIZE(fuc->r_mr); i++) {
1033 if (ram_have(fuc, mr[i]))
1034 ram->base.mr[i] = ram_rd32(fuc, mr[i]);
1036 ram->base.freq = freq;
1038 switch (ram->base.type) {
1039 case NV_MEM_TYPE_DDR3:
1040 ret = nouveau_sddr3_calc(&ram->base);
1042 ret = nve0_ram_calc_sddr3(pfb, freq);
1044 case NV_MEM_TYPE_GDDR5:
1045 ret = nouveau_gddr5_calc(&ram->base, ram->pnuts != 0);
1047 ret = nve0_ram_calc_gddr5(pfb, freq);
1058 nve0_ram_prog(struct nouveau_fb *pfb)
1060 struct nouveau_device *device = nv_device(pfb);
1061 struct nve0_ram *ram = (void *)pfb->ram;
1062 struct nve0_ramfuc *fuc = &ram->fuc;
1063 ram_exec(fuc, nouveau_boolopt(device->cfgopt, "NvMemExec", false));
1068 nve0_ram_tidy(struct nouveau_fb *pfb)
1070 struct nve0_ram *ram = (void *)pfb->ram;
1071 struct nve0_ramfuc *fuc = &ram->fuc;
1072 ram_exec(fuc, false);
1076 nve0_ram_init(struct nouveau_object *object)
1078 struct nouveau_fb *pfb = (void *)object->parent;
1079 struct nve0_ram *ram = (void *)object;
1080 struct nouveau_bios *bios = nouveau_bios(pfb);
1081 static const u8 train0[] = {
1082 0x00, 0xff, 0xff, 0x00, 0xff, 0x00,
1083 0x00, 0xff, 0xff, 0x00, 0xff, 0x00,
1085 static const u32 train1[] = {
1086 0x00000000, 0xffffffff,
1087 0x55555555, 0xaaaaaaaa,
1088 0x33333333, 0xcccccccc,
1089 0xf0f0f0f0, 0x0f0f0f0f,
1090 0x00ff00ff, 0xff00ff00,
1091 0x0000ffff, 0xffff0000,
1093 u8 ver, hdr, cnt, len, snr, ssz;
1097 ret = nouveau_ram_init(&ram->base);
1101 /* run a bunch of tables from rammap table. there's actually
1102 * individual pointers for each rammap entry too, but, nvidia
1103 * seem to just run the last two entries' scripts early on in
1104 * their init, and never again.. we'll just run 'em all once
1107 * i strongly suspect that each script is for a separate mode
1108 * (likely selected by 0x10f65c's lower bits?), and the
1109 * binary driver skips the one that's already been setup by
1112 data = nvbios_rammap_table(bios, &ver, &hdr, &cnt, &len, &snr, &ssz);
1113 if (!data || hdr < 0x15)
1116 cnt = nv_ro08(bios, data + 0x14); /* guess at count */
1117 data = nv_ro32(bios, data + 0x10); /* guess u32... */
1118 save = nv_rd32(pfb, 0x10f65c);
1119 for (i = 0; i < cnt; i++) {
1120 nv_mask(pfb, 0x10f65c, 0x000000f0, i << 4);
1121 nvbios_exec(&(struct nvbios_init) {
1122 .subdev = nv_subdev(pfb),
1124 .offset = nv_ro32(bios, data), /* guess u32 */
1129 nv_wr32(pfb, 0x10f65c, save);
1131 switch (ram->base.type) {
1132 case NV_MEM_TYPE_GDDR5:
1133 for (i = 0; i < 0x30; i++) {
1134 nv_wr32(pfb, 0x10f968, 0x00000000 | (i << 8));
1135 nv_wr32(pfb, 0x10f920, 0x00000000 | train0[i % 12]);
1136 nv_wr32(pfb, 0x10f918, train1[i % 12]);
1137 nv_wr32(pfb, 0x10f920, 0x00000100 | train0[i % 12]);
1138 nv_wr32(pfb, 0x10f918, train1[i % 12]);
1140 nv_wr32(pfb, 0x10f96c, 0x00000000 | (i << 8));
1141 nv_wr32(pfb, 0x10f924, 0x00000000 | train0[i % 12]);
1142 nv_wr32(pfb, 0x10f91c, train1[i % 12]);
1143 nv_wr32(pfb, 0x10f924, 0x00000100 | train0[i % 12]);
1144 nv_wr32(pfb, 0x10f91c, train1[i % 12]);
1147 for (i = 0; i < 0x100; i++) {
1148 nv_wr32(pfb, 0x10f968, i);
1149 nv_wr32(pfb, 0x10f900, train1[2 + (i & 1)]);
1152 for (i = 0; i < 0x100; i++) {
1153 nv_wr32(pfb, 0x10f96c, i);
1154 nv_wr32(pfb, 0x10f900, train1[2 + (i & 1)]);
1165 nve0_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
1166 struct nouveau_oclass *oclass, void *data, u32 size,
1167 struct nouveau_object **pobject)
1169 struct nouveau_fb *pfb = nouveau_fb(parent);
1170 struct nouveau_bios *bios = nouveau_bios(pfb);
1171 struct nouveau_gpio *gpio = nouveau_gpio(pfb);
1172 struct dcb_gpio_func func;
1173 struct nve0_ram *ram;
1177 ret = nvc0_ram_create(parent, engine, oclass, &ram);
1178 *pobject = nv_object(ram);
1182 switch (ram->base.type) {
1183 case NV_MEM_TYPE_DDR3:
1184 case NV_MEM_TYPE_GDDR5:
1185 ram->base.calc = nve0_ram_calc;
1186 ram->base.prog = nve0_ram_prog;
1187 ram->base.tidy = nve0_ram_tidy;
1190 nv_warn(pfb, "reclocking of this RAM type is unsupported\n");
1194 /* calculate a mask of differently configured memory partitions,
1195 * because, of course reclocking wasn't complicated enough
1196 * already without having to treat some of them differently to
1199 ram->parts = nv_rd32(pfb, 0x022438);
1200 ram->pmask = nv_rd32(pfb, 0x022554);
1202 for (i = 0, tmp = 0; i < ram->parts; i++) {
1203 if (!(ram->pmask & (1 << i))) {
1204 u32 cfg1 = nv_rd32(pfb, 0x110204 + (i * 0x1000));
1205 if (tmp && tmp != cfg1) {
1206 ram->pnuts |= (1 << i);
1213 // parse bios data for both pll's
1214 ret = nvbios_pll_parse(bios, 0x0c, &ram->fuc.refpll);
1216 nv_error(pfb, "mclk refpll data not found\n");
1220 ret = nvbios_pll_parse(bios, 0x04, &ram->fuc.mempll);
1222 nv_error(pfb, "mclk pll data not found\n");
1226 ret = gpio->find(gpio, 0, 0x18, DCB_GPIO_UNUSED, &func);
1228 ram->fuc.r_gpioMV = ramfuc_reg(0x00d610 + (func.line * 0x04));
1229 ram->fuc.r_funcMV[0] = (func.log[0] ^ 2) << 12;
1230 ram->fuc.r_funcMV[1] = (func.log[1] ^ 2) << 12;
1233 ret = gpio->find(gpio, 0, 0x2e, DCB_GPIO_UNUSED, &func);
1235 ram->fuc.r_gpio2E = ramfuc_reg(0x00d610 + (func.line * 0x04));
1236 ram->fuc.r_func2E[0] = (func.log[0] ^ 2) << 12;
1237 ram->fuc.r_func2E[1] = (func.log[1] ^ 2) << 12;
1240 ram->fuc.r_gpiotrig = ramfuc_reg(0x00d604);
1242 ram->fuc.r_0x132020 = ramfuc_reg(0x132020);
1243 ram->fuc.r_0x132028 = ramfuc_reg(0x132028);
1244 ram->fuc.r_0x132024 = ramfuc_reg(0x132024);
1245 ram->fuc.r_0x132030 = ramfuc_reg(0x132030);
1246 ram->fuc.r_0x132034 = ramfuc_reg(0x132034);
1247 ram->fuc.r_0x132000 = ramfuc_reg(0x132000);
1248 ram->fuc.r_0x132004 = ramfuc_reg(0x132004);
1249 ram->fuc.r_0x132040 = ramfuc_reg(0x132040);
1251 ram->fuc.r_0x10f248 = ramfuc_reg(0x10f248);
1252 ram->fuc.r_0x10f290 = ramfuc_reg(0x10f290);
1253 ram->fuc.r_0x10f294 = ramfuc_reg(0x10f294);
1254 ram->fuc.r_0x10f298 = ramfuc_reg(0x10f298);
1255 ram->fuc.r_0x10f29c = ramfuc_reg(0x10f29c);
1256 ram->fuc.r_0x10f2a0 = ramfuc_reg(0x10f2a0);
1257 ram->fuc.r_0x10f2a4 = ramfuc_reg(0x10f2a4);
1258 ram->fuc.r_0x10f2a8 = ramfuc_reg(0x10f2a8);
1259 ram->fuc.r_0x10f2ac = ramfuc_reg(0x10f2ac);
1260 ram->fuc.r_0x10f2cc = ramfuc_reg(0x10f2cc);
1261 ram->fuc.r_0x10f2e8 = ramfuc_reg(0x10f2e8);
1262 ram->fuc.r_0x10f250 = ramfuc_reg(0x10f250);
1263 ram->fuc.r_0x10f24c = ramfuc_reg(0x10f24c);
1264 ram->fuc.r_0x10fec4 = ramfuc_reg(0x10fec4);
1265 ram->fuc.r_0x10fec8 = ramfuc_reg(0x10fec8);
1266 ram->fuc.r_0x10f604 = ramfuc_reg(0x10f604);
1267 ram->fuc.r_0x10f614 = ramfuc_reg(0x10f614);
1268 ram->fuc.r_0x10f610 = ramfuc_reg(0x10f610);
1269 ram->fuc.r_0x100770 = ramfuc_reg(0x100770);
1270 ram->fuc.r_0x100778 = ramfuc_reg(0x100778);
1271 ram->fuc.r_0x10f224 = ramfuc_reg(0x10f224);
1273 ram->fuc.r_0x10f870 = ramfuc_reg(0x10f870);
1274 ram->fuc.r_0x10f698 = ramfuc_reg(0x10f698);
1275 ram->fuc.r_0x10f694 = ramfuc_reg(0x10f694);
1276 ram->fuc.r_0x10f6b8 = ramfuc_reg(0x10f6b8);
1277 ram->fuc.r_0x10f808 = ramfuc_reg(0x10f808);
1278 ram->fuc.r_0x10f670 = ramfuc_reg(0x10f670);
1279 ram->fuc.r_0x10f60c = ramfuc_reg(0x10f60c);
1280 ram->fuc.r_0x10f830 = ramfuc_reg(0x10f830);
1281 ram->fuc.r_0x1373ec = ramfuc_reg(0x1373ec);
1282 ram->fuc.r_0x10f800 = ramfuc_reg(0x10f800);
1283 ram->fuc.r_0x10f82c = ramfuc_reg(0x10f82c);
1285 ram->fuc.r_0x10f978 = ramfuc_reg(0x10f978);
1286 ram->fuc.r_0x10f910 = ramfuc_reg(0x10f910);
1287 ram->fuc.r_0x10f914 = ramfuc_reg(0x10f914);
1289 switch (ram->base.type) {
1290 case NV_MEM_TYPE_GDDR5:
1291 ram->fuc.r_mr[0] = ramfuc_reg(0x10f300);
1292 ram->fuc.r_mr[1] = ramfuc_reg(0x10f330);
1293 ram->fuc.r_mr[2] = ramfuc_reg(0x10f334);
1294 ram->fuc.r_mr[3] = ramfuc_reg(0x10f338);
1295 ram->fuc.r_mr[4] = ramfuc_reg(0x10f33c);
1296 ram->fuc.r_mr[5] = ramfuc_reg(0x10f340);
1297 ram->fuc.r_mr[6] = ramfuc_reg(0x10f344);
1298 ram->fuc.r_mr[7] = ramfuc_reg(0x10f348);
1299 ram->fuc.r_mr[8] = ramfuc_reg(0x10f354);
1300 ram->fuc.r_mr[15] = ramfuc_reg(0x10f34c);
1302 case NV_MEM_TYPE_DDR3:
1303 ram->fuc.r_mr[0] = ramfuc_reg(0x10f300);
1304 ram->fuc.r_mr[2] = ramfuc_reg(0x10f320);
1310 ram->fuc.r_0x62c000 = ramfuc_reg(0x62c000);
1311 ram->fuc.r_0x10f200 = ramfuc_reg(0x10f200);
1312 ram->fuc.r_0x10f210 = ramfuc_reg(0x10f210);
1313 ram->fuc.r_0x10f310 = ramfuc_reg(0x10f310);
1314 ram->fuc.r_0x10f314 = ramfuc_reg(0x10f314);
1315 ram->fuc.r_0x10f318 = ramfuc_reg(0x10f318);
1316 ram->fuc.r_0x10f090 = ramfuc_reg(0x10f090);
1317 ram->fuc.r_0x10f69c = ramfuc_reg(0x10f69c);
1318 ram->fuc.r_0x10f824 = ramfuc_reg(0x10f824);
1319 ram->fuc.r_0x1373f0 = ramfuc_reg(0x1373f0);
1320 ram->fuc.r_0x1373f4 = ramfuc_reg(0x1373f4);
1321 ram->fuc.r_0x137320 = ramfuc_reg(0x137320);
1322 ram->fuc.r_0x10f65c = ramfuc_reg(0x10f65c);
1323 ram->fuc.r_0x10f6bc = ramfuc_reg(0x10f6bc);
1324 ram->fuc.r_0x100710 = ramfuc_reg(0x100710);
1325 ram->fuc.r_0x100750 = ramfuc_reg(0x100750);
1329 struct nouveau_oclass
1332 .ofuncs = &(struct nouveau_ofuncs) {
1333 .ctor = nve0_ram_ctor,
1334 .dtor = _nouveau_ram_dtor,
1335 .init = nve0_ram_init,
1336 .fini = _nouveau_ram_fini,