2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
27 struct nvd0_therm_priv {
28 struct nouveau_therm_priv base;
32 pwm_info(struct nouveau_therm *therm, int line)
34 u32 gpio = nv_rd32(therm, 0x00d610 + (line * 0x04));
36 switch (gpio & 0x000000c0) {
37 case 0x00000000: /* normal mode, possibly pwm forced off by us */
38 case 0x00000040: /* nvio special */
39 switch (gpio & 0x0000001f) {
50 nv_error(therm, "GPIO %d unknown PWM: 0x%08x\n", line, gpio);
55 nvd0_fan_pwm_ctrl(struct nouveau_therm *therm, int line, bool enable)
57 u32 data = enable ? 0x00000040 : 0x00000000;
58 int indx = pwm_info(therm, line);
62 nv_mask(therm, 0x00d610 + (line * 0x04), 0x000000c0, data);
63 /* nothing to do for indx == 2, it seems hardwired to PTHERM */
68 nvd0_fan_pwm_get(struct nouveau_therm *therm, int line, u32 *divs, u32 *duty)
70 int indx = pwm_info(therm, line);
74 if (nv_rd32(therm, 0x00d610 + (line * 0x04)) & 0x00000040) {
75 *divs = nv_rd32(therm, 0x00e114 + (indx * 8));
76 *duty = nv_rd32(therm, 0x00e118 + (indx * 8));
79 } else if (indx == 2) {
80 *divs = nv_rd32(therm, 0x0200d8) & 0x1fff;
81 *duty = nv_rd32(therm, 0x0200dc) & 0x1fff;
89 nvd0_fan_pwm_set(struct nouveau_therm *therm, int line, u32 divs, u32 duty)
91 int indx = pwm_info(therm, line);
95 nv_wr32(therm, 0x00e114 + (indx * 8), divs);
96 nv_wr32(therm, 0x00e118 + (indx * 8), duty | 0x80000000);
97 } else if (indx == 2) {
98 nv_mask(therm, 0x0200d8, 0x1fff, divs); /* keep the high bits */
99 nv_wr32(therm, 0x0200dc, duty | 0x40000000);
105 nvd0_fan_pwm_clock(struct nouveau_therm *therm, int line)
107 int indx = pwm_info(therm, line);
111 return (nv_device(therm)->crystal * 1000) / 20;
113 return nv_device(therm)->crystal * 1000 / 10;
117 nvd0_therm_init(struct nouveau_object *object)
119 struct nvd0_therm_priv *priv = (void *)object;
122 ret = nouveau_therm_init(&priv->base.base);
126 /* enable fan tach, count revolutions per-second */
127 nv_mask(priv, 0x00e720, 0x00000003, 0x00000002);
128 if (priv->base.fan->tach.func != DCB_GPIO_UNUSED) {
129 nv_mask(priv, 0x00d79c, 0x000000ff, priv->base.fan->tach.line);
130 nv_wr32(priv, 0x00e724, nv_device(priv)->crystal * 1000);
131 nv_mask(priv, 0x00e720, 0x00000001, 0x00000001);
133 nv_mask(priv, 0x00e720, 0x00000002, 0x00000000);
139 nvd0_therm_ctor(struct nouveau_object *parent,
140 struct nouveau_object *engine,
141 struct nouveau_oclass *oclass, void *data, u32 size,
142 struct nouveau_object **pobject)
144 struct nvd0_therm_priv *priv;
147 ret = nouveau_therm_create(parent, engine, oclass, &priv);
148 *pobject = nv_object(priv);
152 priv->base.base.pwm_ctrl = nvd0_fan_pwm_ctrl;
153 priv->base.base.pwm_get = nvd0_fan_pwm_get;
154 priv->base.base.pwm_set = nvd0_fan_pwm_set;
155 priv->base.base.pwm_clock = nvd0_fan_pwm_clock;
156 priv->base.base.temp_get = nv84_temp_get;
157 priv->base.base.fan_sense = nva3_therm_fan_sense;
158 priv->base.sensor.program_alarms = nouveau_therm_program_alarms_polling;
159 return nouveau_therm_preinit(&priv->base.base);
162 struct nouveau_oclass
163 nvd0_therm_oclass = {
164 .handle = NV_SUBDEV(THERM, 0xd0),
165 .ofuncs = &(struct nouveau_ofuncs) {
166 .ctor = nvd0_therm_ctor,
167 .dtor = _nouveau_therm_dtor,
168 .init = nvd0_therm_init,
169 .fini = nv84_therm_fini,