drivers/gpu/drm/nouveau/core/subdev/therm/nvd0.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include "priv.h"
  26
  27 struct nvd0_therm_priv {
  28         struct nouveau_therm_priv base;
  29 };
  30
  31 static int
  32 pwm_info(struct nouveau_therm *therm, int line)
  33 {
  34         u32 gpio = nv_rd32(therm, 0x00d610 + (line * 0x04));
  35
  36         switch (gpio & 0x000000c0) {
  37         case 0x00000000: /* normal mode, possibly pwm forced off by us */
  38         case 0x00000040: /* nvio special */
  39                 switch (gpio & 0x0000001f) {
  40                 case 0x00: return 2;
  41                 case 0x19: return 1;
  42                 case 0x1c: return 0;
  43                 case 0x1e: return 2;
  44                 default:
  45                         break;
  46                 }
  47         default:
  48                 break;
  49         }
  50
  51         nv_error(therm, "GPIO %d unknown PWM: 0x%08x\n", line, gpio);
  52         return -ENODEV;
  53 }
  54
  55 static int
  56 nvd0_fan_pwm_ctrl(struct nouveau_therm *therm, int line, bool enable)
  57 {
  58         u32 data = enable ? 0x00000040 : 0x00000000;
  59         int indx = pwm_info(therm, line);
  60         if (indx < 0)
  61                 return indx;
  62         else if (indx < 2)
  63                 nv_mask(therm, 0x00d610 + (line * 0x04), 0x000000c0, data);
  64         /* nothing to do for indx == 2, it seems hardwired to PTHERM */
  65         return 0;
  66 }
  67
  68 static int
  69 nvd0_fan_pwm_get(struct nouveau_therm *therm, int line, u32 *divs, u32 *duty)
  70 {
  71         int indx = pwm_info(therm, line);
  72         if (indx < 0)
  73                 return indx;
  74         else if (indx < 2) {
  75                 if (nv_rd32(therm, 0x00d610 + (line * 0x04)) & 0x00000040) {
  76                         *divs = nv_rd32(therm, 0x00e114 + (indx * 8));
  77                         *duty = nv_rd32(therm, 0x00e118 + (indx * 8));
  78                         return 0;
  79                 }
  80         } else if (indx == 2) {
  81                 *divs = nv_rd32(therm, 0x0200d8) & 0x1fff;
  82                 *duty = nv_rd32(therm, 0x0200dc) & 0x1fff;
  83                 return 0;
  84         }
  85
  86         return -EINVAL;
  87 }
  88
  89 static int
  90 nvd0_fan_pwm_set(struct nouveau_therm *therm, int line, u32 divs, u32 duty)
  91 {
  92         int indx = pwm_info(therm, line);
  93         if (indx < 0)
  94                 return indx;
  95         else if (indx < 2) {
  96                 nv_wr32(therm, 0x00e114 + (indx * 8), divs);
  97                 nv_wr32(therm, 0x00e118 + (indx * 8), duty | 0x80000000);
  98         } else if (indx == 2) {
  99                 nv_mask(therm, 0x0200d8, 0x1fff, divs); /* keep the high bits */
 100                 nv_wr32(therm, 0x0200dc, duty | 0x40000000);
 101         }
 102         return 0;
 103 }
 104
 105 static int
 106 nvd0_fan_pwm_clock(struct nouveau_therm *therm, int line)
 107 {
 108         int indx = pwm_info(therm, line);
 109         if (indx < 0)
 110                 return 0;
 111         else if (indx < 2)
 112                 return (nv_device(therm)->crystal * 1000) / 20;
 113         else
 114                 return nv_device(therm)->crystal * 1000 / 10;
 115 }
 116
 117 static int
 118 nvd0_therm_init(struct nouveau_object *object)
 119 {
 120         struct nvd0_therm_priv *priv = (void *)object;
 121         int ret;
 122
 123         ret = nouveau_therm_init(&priv->base.base);
 124         if (ret)
 125                 return ret;
 126
 127         /* enable fan tach, count revolutions per-second */
 128         nv_mask(priv, 0x00e720, 0x00000003, 0x00000002);
 129         if (priv->base.fan->tach.func != DCB_GPIO_UNUSED) {
 130                 nv_mask(priv, 0x00d79c, 0x000000ff, priv->base.fan->tach.line);
 131                 nv_wr32(priv, 0x00e724, nv_device(priv)->crystal * 1000);
 132                 nv_mask(priv, 0x00e720, 0x00000001, 0x00000001);
 133         }
 134         nv_mask(priv, 0x00e720, 0x00000002, 0x00000000);
 135
 136         return 0;
 137 }
 138
 139 static int
 140 nvd0_therm_ctor(struct nouveau_object *parent,
 141                 struct nouveau_object *engine,
 142                 struct nouveau_oclass *oclass, void *data, u32 size,
 143                 struct nouveau_object **pobject)
 144 {
 145         struct nvd0_therm_priv *priv;
 146         int ret;
 147
 148         ret = nouveau_therm_create(parent, engine, oclass, &priv);
 149         *pobject = nv_object(priv);
 150         if (ret)
 151                 return ret;
 152
 153         priv->base.base.pwm_ctrl = nvd0_fan_pwm_ctrl;
 154         priv->base.base.pwm_get = nvd0_fan_pwm_get;
 155         priv->base.base.pwm_set = nvd0_fan_pwm_set;
 156         priv->base.base.pwm_clock = nvd0_fan_pwm_clock;
 157         priv->base.base.temp_get = nv84_temp_get;
 158         priv->base.base.fan_sense = nva3_therm_fan_sense;
 159         priv->base.sensor.program_alarms = nouveau_therm_program_alarms_polling;
 160         return nouveau_therm_preinit(&priv->base.base);
 161 }
 162
 163 struct nouveau_oclass
 164 nvd0_therm_oclass = {
 165         .handle = NV_SUBDEV(THERM, 0xd0),
 166         .ofuncs = &(struct nouveau_ofuncs) {
 167                 .ctor = nvd0_therm_ctor,
 168                 .dtor = _nouveau_therm_dtor,
 169                 .init = nvd0_therm_init,
 170                 .fini = nv84_therm_fini,
 171         },
 172 };