2 * Copyright 2007-2008 Nouveau Project
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #ifndef __NOUVEAU_BIOS_H__
25 #define __NOUVEAU_BIOS_H__
28 #include "nouveau_i2c.h"
30 #define DCB_MAX_NUM_ENTRIES 16
31 #define DCB_MAX_NUM_I2C_ENTRIES 16
32 #define DCB_MAX_NUM_GPIO_ENTRIES 32
33 #define DCB_MAX_NUM_CONNECTOR_ENTRIES 16
35 #define DCB_LOC_ON_CHIP 0
37 #define ROM16(x) le16_to_cpu(*(u16 *)&(x))
38 #define ROM32(x) le32_to_cpu(*(u32 *)&(x))
39 #define ROM48(x) ({ u8 *p = &(x); (u64)ROM16(p[4]) << 32 | ROM32(p[0]); })
40 #define ROM64(x) le64_to_cpu(*(u64 *)&(x))
41 #define ROMPTR(d,x) ({ \
42 struct drm_nouveau_private *dev_priv = (d)->dev_private; \
43 ROM16(x) ? &dev_priv->vbios.data[ROM16(x)] : NULL; \
54 int bit_table(struct drm_device *, u8 id, struct bit_entry *);
57 DCB_GPIO_PANEL_POWER = 0x01,
58 DCB_GPIO_TVDAC0 = 0x0c,
59 DCB_GPIO_TVDAC1 = 0x2d,
60 DCB_GPIO_PWM_FAN = 0x09,
61 DCB_GPIO_FAN_SENSE = 0x3d,
62 DCB_GPIO_UNUSED = 0xff
65 enum dcb_connector_type {
66 DCB_CONNECTOR_VGA = 0x00,
67 DCB_CONNECTOR_TV_0 = 0x10,
68 DCB_CONNECTOR_TV_1 = 0x11,
69 DCB_CONNECTOR_TV_3 = 0x13,
70 DCB_CONNECTOR_DVI_I = 0x30,
71 DCB_CONNECTOR_DVI_D = 0x31,
72 DCB_CONNECTOR_LVDS = 0x40,
73 DCB_CONNECTOR_LVDS_SPWG = 0x41,
74 DCB_CONNECTOR_DP = 0x46,
75 DCB_CONNECTOR_eDP = 0x47,
76 DCB_CONNECTOR_HDMI_0 = 0x60,
77 DCB_CONNECTOR_HDMI_1 = 0x61,
78 DCB_CONNECTOR_NONE = 0xff
87 OUTPUT_EOL = 14, /* DCB 4.0+, appears to be end-of-list */
93 int index; /* may not be raw dcb index if merging has happened */
101 bool duallink_possible;
111 bool use_straps_for_mode;
112 bool use_acpi_for_edid;
113 bool use_power_scripts;
116 bool has_component_output;
128 bool i2c_upper_default;
134 struct dcb_entry entry[DCB_MAX_NUM_ENTRIES];
144 /* Order *does* matter here */
153 /* these match types in pll limits table version 0x40,
154 * nouveau uses them on all chipsets internally where a
155 * specific pll needs to be referenced, but the exact
156 * register isn't known.
189 * for most pre nv50 cards setting a log2P of 7 (the common max_log2p
190 * value) is no different to 6 (at least for vplls) so allowing the MNP
191 * calc to use 7 causes the generated clock to be out by a factor of 2.
192 * however, max_log2p cannot be fixed-up during parsing as the
193 * unmodified max_log2p value is still needed for setting mplls, hence
194 * an additional max_usable_log2p member
196 uint8_t max_usable_log2p;
206 struct drm_device *dev;
213 uint8_t chip_version;
216 uint32_t tvdactestval;
217 uint8_t digital_min_front_porch;
222 uint8_t data[NV_PROM_SIZE];
226 uint8_t major_version;
227 uint8_t feature_byte;
230 uint32_t fmaxvco, fminvco;
233 uint16_t init_script_tbls_ptr;
234 uint16_t extra_init_script_tbl_ptr;
235 uint16_t macro_index_tbl_ptr;
236 uint16_t macro_tbl_ptr;
237 uint16_t condition_tbl_ptr;
238 uint16_t io_condition_tbl_ptr;
239 uint16_t io_flag_condition_tbl_ptr;
240 uint16_t init_function_tbl_ptr;
242 uint16_t pll_limit_tbl_ptr;
243 uint16_t ram_restrict_tbl_ptr;
244 uint8_t ram_restrict_group_count;
246 uint16_t some_script_ptr; /* BIT I + 14 */
247 uint16_t init96_tbl_ptr; /* BIT I + 16 */
249 struct dcb_table dcb;
256 struct dcb_entry *output;
258 uint16_t script_table_ptr;
262 uint16_t fptablepointer; /* also used by tmds */
263 uint16_t fpxlatetableptr;
265 uint16_t lvdsmanufacturerpointer;
266 uint16_t fpxlatemanufacturertableptr;
268 uint16_t xlated_entry;
269 bool power_off_for_reset;
270 bool reset_after_pclk_change;
272 bool link_c_increment;
274 int duallink_transition_clk;
275 uint8_t strapless_is_24bit;
278 /* will need resetting after suspend */
279 int last_script_invoc;
284 uint16_t output0_script_ptr;
285 uint16_t output1_script_ptr;
289 uint16_t mem_init_tbl_ptr;
290 uint16_t sdr_seq_tbl_ptr;
291 uint16_t ddr_seq_tbl_ptr;
294 uint8_t crt, tv, panel;
297 uint16_t lvds_single_a_script_ptr;
301 void *dcb_table(struct drm_device *);
302 void *dcb_outp(struct drm_device *, u8 idx);
303 int dcb_outp_foreach(struct drm_device *, void *data,
304 int (*)(struct drm_device *, void *, int idx, u8 *outp));
305 u8 *dcb_conntab(struct drm_device *);
306 u8 *dcb_conn(struct drm_device *, u8 idx);