2 * Copyright 2007 Dave Airlied
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 * Authors: Dave Airlied <airlied@linux.ie>
26 * Ben Skeggs <darktama@iinet.net.au>
27 * Jeremy Kolb <jkolb@brandeis.edu>
30 #include <core/engine.h>
32 #include <subdev/fb.h>
33 #include <subdev/vm.h>
34 #include <subdev/bar.h>
36 #include "nouveau_drm.h"
37 #include "nouveau_dma.h"
38 #include "nouveau_fence.h"
40 #include "nouveau_bo.h"
41 #include "nouveau_ttm.h"
42 #include "nouveau_gem.h"
45 * NV10-NV40 tiling helpers
49 nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg,
50 u32 addr, u32 size, u32 pitch, u32 flags)
52 struct nouveau_drm *drm = nouveau_drm(dev);
53 int i = reg - drm->tile.reg;
54 struct nouveau_fb *pfb = nouveau_fb(drm->device);
55 struct nouveau_fb_tile *tile = &pfb->tile.region[i];
56 struct nouveau_engine *engine;
58 nouveau_fence_unref(®->fence);
61 pfb->tile.fini(pfb, i, tile);
64 pfb->tile.init(pfb, i, addr, size, pitch, flags, tile);
66 pfb->tile.prog(pfb, i, tile);
68 if ((engine = nouveau_engine(pfb, NVDEV_ENGINE_GR)))
69 engine->tile_prog(engine, i);
70 if ((engine = nouveau_engine(pfb, NVDEV_ENGINE_MPEG)))
71 engine->tile_prog(engine, i);
74 static struct nouveau_drm_tile *
75 nv10_bo_get_tile_region(struct drm_device *dev, int i)
77 struct nouveau_drm *drm = nouveau_drm(dev);
78 struct nouveau_drm_tile *tile = &drm->tile.reg[i];
80 spin_lock(&drm->tile.lock);
83 (!tile->fence || nouveau_fence_done(tile->fence)))
88 spin_unlock(&drm->tile.lock);
93 nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile,
94 struct nouveau_fence *fence)
96 struct nouveau_drm *drm = nouveau_drm(dev);
99 spin_lock(&drm->tile.lock);
101 /* Mark it as pending. */
103 nouveau_fence_ref(fence);
107 spin_unlock(&drm->tile.lock);
111 static struct nouveau_drm_tile *
112 nv10_bo_set_tiling(struct drm_device *dev, u32 addr,
113 u32 size, u32 pitch, u32 flags)
115 struct nouveau_drm *drm = nouveau_drm(dev);
116 struct nouveau_fb *pfb = nouveau_fb(drm->device);
117 struct nouveau_drm_tile *tile, *found = NULL;
120 for (i = 0; i < pfb->tile.regions; i++) {
121 tile = nv10_bo_get_tile_region(dev, i);
123 if (pitch && !found) {
127 } else if (tile && pfb->tile.region[i].pitch) {
128 /* Kill an unused tile region. */
129 nv10_bo_update_tile_region(dev, tile, 0, 0, 0, 0);
132 nv10_bo_put_tile_region(dev, tile, NULL);
136 nv10_bo_update_tile_region(dev, found, addr, size,
142 nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
144 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
145 struct drm_device *dev = drm->dev;
146 struct nouveau_bo *nvbo = nouveau_bo(bo);
148 if (unlikely(nvbo->gem))
149 DRM_ERROR("bo %p still attached to GEM object\n", bo);
150 nv10_bo_put_tile_region(dev, nvbo->tile, NULL);
155 nouveau_bo_fixup_align(struct nouveau_bo *nvbo, u32 flags,
156 int *align, int *size)
158 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
159 struct nouveau_device *device = nv_device(drm->device);
161 if (device->card_type < NV_50) {
162 if (nvbo->tile_mode) {
163 if (device->chipset >= 0x40) {
165 *size = roundup(*size, 64 * nvbo->tile_mode);
167 } else if (device->chipset >= 0x30) {
169 *size = roundup(*size, 64 * nvbo->tile_mode);
171 } else if (device->chipset >= 0x20) {
173 *size = roundup(*size, 64 * nvbo->tile_mode);
175 } else if (device->chipset >= 0x10) {
177 *size = roundup(*size, 32 * nvbo->tile_mode);
181 *size = roundup(*size, (1 << nvbo->page_shift));
182 *align = max((1 << nvbo->page_shift), *align);
185 *size = roundup(*size, PAGE_SIZE);
189 nouveau_bo_new(struct drm_device *dev, int size, int align,
190 uint32_t flags, uint32_t tile_mode, uint32_t tile_flags,
192 struct nouveau_bo **pnvbo)
194 struct nouveau_drm *drm = nouveau_drm(dev);
195 struct nouveau_bo *nvbo;
198 int type = ttm_bo_type_device;
201 type = ttm_bo_type_sg;
203 nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
206 INIT_LIST_HEAD(&nvbo->head);
207 INIT_LIST_HEAD(&nvbo->entry);
208 INIT_LIST_HEAD(&nvbo->vma_list);
209 nvbo->tile_mode = tile_mode;
210 nvbo->tile_flags = tile_flags;
211 nvbo->bo.bdev = &drm->ttm.bdev;
213 nvbo->page_shift = 12;
214 if (drm->client.base.vm) {
215 if (!(flags & TTM_PL_FLAG_TT) && size > 256 * 1024)
216 nvbo->page_shift = drm->client.base.vm->vmm->lpg_shift;
219 nouveau_bo_fixup_align(nvbo, flags, &align, &size);
220 nvbo->bo.mem.num_pages = size >> PAGE_SHIFT;
221 nouveau_bo_placement_set(nvbo, flags, 0);
223 acc_size = ttm_bo_dma_acc_size(&drm->ttm.bdev, size,
224 sizeof(struct nouveau_bo));
226 ret = ttm_bo_init(&drm->ttm.bdev, &nvbo->bo, size,
227 type, &nvbo->placement,
228 align >> PAGE_SHIFT, 0, false, NULL, acc_size, sg,
231 /* ttm will call nouveau_bo_del_ttm if it fails.. */
240 set_placement_list(uint32_t *pl, unsigned *n, uint32_t type, uint32_t flags)
244 if (type & TTM_PL_FLAG_VRAM)
245 pl[(*n)++] = TTM_PL_FLAG_VRAM | flags;
246 if (type & TTM_PL_FLAG_TT)
247 pl[(*n)++] = TTM_PL_FLAG_TT | flags;
248 if (type & TTM_PL_FLAG_SYSTEM)
249 pl[(*n)++] = TTM_PL_FLAG_SYSTEM | flags;
253 set_placement_range(struct nouveau_bo *nvbo, uint32_t type)
255 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
256 struct nouveau_fb *pfb = nouveau_fb(drm->device);
257 u32 vram_pages = pfb->ram.size >> PAGE_SHIFT;
259 if (nv_device(drm->device)->card_type == NV_10 &&
260 nvbo->tile_mode && (type & TTM_PL_FLAG_VRAM) &&
261 nvbo->bo.mem.num_pages < vram_pages / 4) {
263 * Make sure that the color and depth buffers are handled
264 * by independent memory controller units. Up to a 9x
265 * speed up when alpha-blending and depth-test are enabled
268 if (nvbo->tile_flags & NOUVEAU_GEM_TILE_ZETA) {
269 nvbo->placement.fpfn = vram_pages / 2;
270 nvbo->placement.lpfn = ~0;
272 nvbo->placement.fpfn = 0;
273 nvbo->placement.lpfn = vram_pages / 2;
279 nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy)
281 struct ttm_placement *pl = &nvbo->placement;
282 uint32_t flags = TTM_PL_MASK_CACHING |
283 (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0);
285 pl->placement = nvbo->placements;
286 set_placement_list(nvbo->placements, &pl->num_placement,
289 pl->busy_placement = nvbo->busy_placements;
290 set_placement_list(nvbo->busy_placements, &pl->num_busy_placement,
293 set_placement_range(nvbo, type);
297 nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype)
299 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
300 struct ttm_buffer_object *bo = &nvbo->bo;
303 if (nvbo->pin_refcnt && !(memtype & (1 << bo->mem.mem_type))) {
304 NV_ERROR(drm, "bo %p pinned elsewhere: 0x%08x vs 0x%08x\n", bo,
305 1 << bo->mem.mem_type, memtype);
309 if (nvbo->pin_refcnt++)
312 ret = ttm_bo_reserve(bo, false, false, false, 0);
316 nouveau_bo_placement_set(nvbo, memtype, 0);
318 ret = nouveau_bo_validate(nvbo, false, false, false);
320 switch (bo->mem.mem_type) {
322 drm->gem.vram_available -= bo->mem.size;
325 drm->gem.gart_available -= bo->mem.size;
331 ttm_bo_unreserve(bo);
339 nouveau_bo_unpin(struct nouveau_bo *nvbo)
341 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
342 struct ttm_buffer_object *bo = &nvbo->bo;
345 if (--nvbo->pin_refcnt)
348 ret = ttm_bo_reserve(bo, false, false, false, 0);
352 nouveau_bo_placement_set(nvbo, bo->mem.placement, 0);
354 ret = nouveau_bo_validate(nvbo, false, false, false);
356 switch (bo->mem.mem_type) {
358 drm->gem.vram_available += bo->mem.size;
361 drm->gem.gart_available += bo->mem.size;
368 ttm_bo_unreserve(bo);
373 nouveau_bo_map(struct nouveau_bo *nvbo)
377 ret = ttm_bo_reserve(&nvbo->bo, false, false, false, 0);
381 ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap);
382 ttm_bo_unreserve(&nvbo->bo);
387 nouveau_bo_unmap(struct nouveau_bo *nvbo)
390 ttm_bo_kunmap(&nvbo->kmap);
394 nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible,
395 bool no_wait_reserve, bool no_wait_gpu)
399 ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, interruptible,
400 no_wait_reserve, no_wait_gpu);
408 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index)
411 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
414 return ioread16_native((void __force __iomem *)mem);
420 nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
423 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
426 iowrite16_native(val, (void __force __iomem *)mem);
432 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
435 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
438 return ioread32_native((void __force __iomem *)mem);
444 nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
447 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
450 iowrite32_native(val, (void __force __iomem *)mem);
455 static struct ttm_tt *
456 nouveau_ttm_tt_create(struct ttm_bo_device *bdev, unsigned long size,
457 uint32_t page_flags, struct page *dummy_read)
460 struct nouveau_drm *drm = nouveau_bdev(bdev);
461 struct drm_device *dev = drm->dev;
463 if (drm->agp.stat == ENABLED) {
464 return ttm_agp_tt_create(bdev, dev->agp->bridge, size,
465 page_flags, dummy_read);
469 return nouveau_sgdma_create_ttm(bdev, size, page_flags, dummy_read);
473 nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
475 /* We'll do this from user space. */
480 nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
481 struct ttm_mem_type_manager *man)
483 struct nouveau_drm *drm = nouveau_bdev(bdev);
487 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
488 man->available_caching = TTM_PL_MASK_CACHING;
489 man->default_caching = TTM_PL_FLAG_CACHED;
492 if (nv_device(drm->device)->card_type >= NV_50) {
493 man->func = &nouveau_vram_manager;
494 man->io_reserve_fastpath = false;
495 man->use_io_reserve_lru = true;
497 man->func = &ttm_bo_manager_func;
499 man->flags = TTM_MEMTYPE_FLAG_FIXED |
500 TTM_MEMTYPE_FLAG_MAPPABLE;
501 man->available_caching = TTM_PL_FLAG_UNCACHED |
503 man->default_caching = TTM_PL_FLAG_WC;
506 if (nv_device(drm->device)->card_type >= NV_50)
507 man->func = &nouveau_gart_manager;
509 if (drm->agp.stat != ENABLED)
510 man->func = &nv04_gart_manager;
512 man->func = &ttm_bo_manager_func;
514 if (drm->agp.stat == ENABLED) {
515 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
516 man->available_caching = TTM_PL_FLAG_UNCACHED |
518 man->default_caching = TTM_PL_FLAG_WC;
520 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE |
521 TTM_MEMTYPE_FLAG_CMA;
522 man->available_caching = TTM_PL_MASK_CACHING;
523 man->default_caching = TTM_PL_FLAG_CACHED;
534 nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
536 struct nouveau_bo *nvbo = nouveau_bo(bo);
538 switch (bo->mem.mem_type) {
540 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT,
544 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0);
548 *pl = nvbo->placement;
552 /* GPU-assisted copy using NV_MEMORY_TO_MEMORY_FORMAT, can access
553 * TTM_PL_{VRAM,TT} directly.
557 nouveau_bo_move_accel_cleanup(struct nouveau_channel *chan,
558 struct nouveau_bo *nvbo, bool evict,
559 bool no_wait_reserve, bool no_wait_gpu,
560 struct ttm_mem_reg *new_mem)
562 struct nouveau_fence *fence = NULL;
565 ret = nouveau_fence_new(chan, &fence);
569 ret = ttm_bo_move_accel_cleanup(&nvbo->bo, fence, NULL, evict,
570 no_wait_reserve, no_wait_gpu, new_mem);
571 nouveau_fence_unref(&fence);
576 nve0_bo_move_init(struct nouveau_channel *chan, u32 handle)
578 int ret = RING_SPACE(chan, 2);
580 BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1);
581 OUT_RING (chan, handle);
588 nve0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
589 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
591 struct nouveau_mem *node = old_mem->mm_node;
592 int ret = RING_SPACE(chan, 10);
594 BEGIN_NVC0(chan, NvSubCopy, 0x0400, 8);
595 OUT_RING (chan, upper_32_bits(node->vma[0].offset));
596 OUT_RING (chan, lower_32_bits(node->vma[0].offset));
597 OUT_RING (chan, upper_32_bits(node->vma[1].offset));
598 OUT_RING (chan, lower_32_bits(node->vma[1].offset));
599 OUT_RING (chan, PAGE_SIZE);
600 OUT_RING (chan, PAGE_SIZE);
601 OUT_RING (chan, PAGE_SIZE);
602 OUT_RING (chan, new_mem->num_pages);
603 BEGIN_IMC0(chan, NvSubCopy, 0x0300, 0x0386);
609 nvc0_bo_move_init(struct nouveau_channel *chan, u32 handle)
611 int ret = RING_SPACE(chan, 2);
613 BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1);
614 OUT_RING (chan, handle);
620 nvc0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
621 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
623 struct nouveau_mem *node = old_mem->mm_node;
624 u64 src_offset = node->vma[0].offset;
625 u64 dst_offset = node->vma[1].offset;
626 u32 page_count = new_mem->num_pages;
629 page_count = new_mem->num_pages;
631 int line_count = (page_count > 8191) ? 8191 : page_count;
633 ret = RING_SPACE(chan, 11);
637 BEGIN_NVC0(chan, NvSubCopy, 0x030c, 8);
638 OUT_RING (chan, upper_32_bits(src_offset));
639 OUT_RING (chan, lower_32_bits(src_offset));
640 OUT_RING (chan, upper_32_bits(dst_offset));
641 OUT_RING (chan, lower_32_bits(dst_offset));
642 OUT_RING (chan, PAGE_SIZE);
643 OUT_RING (chan, PAGE_SIZE);
644 OUT_RING (chan, PAGE_SIZE);
645 OUT_RING (chan, line_count);
646 BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1);
647 OUT_RING (chan, 0x00000110);
649 page_count -= line_count;
650 src_offset += (PAGE_SIZE * line_count);
651 dst_offset += (PAGE_SIZE * line_count);
658 nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
659 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
661 struct nouveau_mem *node = old_mem->mm_node;
662 u64 src_offset = node->vma[0].offset;
663 u64 dst_offset = node->vma[1].offset;
664 u32 page_count = new_mem->num_pages;
667 page_count = new_mem->num_pages;
669 int line_count = (page_count > 2047) ? 2047 : page_count;
671 ret = RING_SPACE(chan, 12);
675 BEGIN_NVC0(chan, NvSubCopy, 0x0238, 2);
676 OUT_RING (chan, upper_32_bits(dst_offset));
677 OUT_RING (chan, lower_32_bits(dst_offset));
678 BEGIN_NVC0(chan, NvSubCopy, 0x030c, 6);
679 OUT_RING (chan, upper_32_bits(src_offset));
680 OUT_RING (chan, lower_32_bits(src_offset));
681 OUT_RING (chan, PAGE_SIZE); /* src_pitch */
682 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */
683 OUT_RING (chan, PAGE_SIZE); /* line_length */
684 OUT_RING (chan, line_count);
685 BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1);
686 OUT_RING (chan, 0x00100110);
688 page_count -= line_count;
689 src_offset += (PAGE_SIZE * line_count);
690 dst_offset += (PAGE_SIZE * line_count);
697 nva3_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
698 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
700 struct nouveau_mem *node = old_mem->mm_node;
701 u64 src_offset = node->vma[0].offset;
702 u64 dst_offset = node->vma[1].offset;
703 u32 page_count = new_mem->num_pages;
706 page_count = new_mem->num_pages;
708 int line_count = (page_count > 8191) ? 8191 : page_count;
710 ret = RING_SPACE(chan, 11);
714 BEGIN_NV04(chan, NvSubCopy, 0x030c, 8);
715 OUT_RING (chan, upper_32_bits(src_offset));
716 OUT_RING (chan, lower_32_bits(src_offset));
717 OUT_RING (chan, upper_32_bits(dst_offset));
718 OUT_RING (chan, lower_32_bits(dst_offset));
719 OUT_RING (chan, PAGE_SIZE);
720 OUT_RING (chan, PAGE_SIZE);
721 OUT_RING (chan, PAGE_SIZE);
722 OUT_RING (chan, line_count);
723 BEGIN_NV04(chan, NvSubCopy, 0x0300, 1);
724 OUT_RING (chan, 0x00000110);
726 page_count -= line_count;
727 src_offset += (PAGE_SIZE * line_count);
728 dst_offset += (PAGE_SIZE * line_count);
735 nv98_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
736 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
738 struct nouveau_mem *node = old_mem->mm_node;
739 int ret = RING_SPACE(chan, 7);
741 BEGIN_NV04(chan, NvSubCopy, 0x0320, 6);
742 OUT_RING (chan, upper_32_bits(node->vma[0].offset));
743 OUT_RING (chan, lower_32_bits(node->vma[0].offset));
744 OUT_RING (chan, upper_32_bits(node->vma[1].offset));
745 OUT_RING (chan, lower_32_bits(node->vma[1].offset));
746 OUT_RING (chan, 0x00000000 /* COPY */);
747 OUT_RING (chan, new_mem->num_pages << PAGE_SHIFT);
753 nv84_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
754 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
756 struct nouveau_mem *node = old_mem->mm_node;
757 int ret = RING_SPACE(chan, 7);
759 BEGIN_NV04(chan, NvSubCopy, 0x0304, 6);
760 OUT_RING (chan, new_mem->num_pages << PAGE_SHIFT);
761 OUT_RING (chan, upper_32_bits(node->vma[0].offset));
762 OUT_RING (chan, lower_32_bits(node->vma[0].offset));
763 OUT_RING (chan, upper_32_bits(node->vma[1].offset));
764 OUT_RING (chan, lower_32_bits(node->vma[1].offset));
765 OUT_RING (chan, 0x00000000 /* MODE_COPY, QUERY_NONE */);
771 nv50_bo_move_init(struct nouveau_channel *chan, u32 handle)
773 int ret = RING_SPACE(chan, 6);
775 BEGIN_NV04(chan, NvSubCopy, 0x0000, 1);
776 OUT_RING (chan, handle);
777 BEGIN_NV04(chan, NvSubCopy, 0x0180, 3);
778 OUT_RING (chan, NvNotify0);
779 OUT_RING (chan, NvDmaFB);
780 OUT_RING (chan, NvDmaFB);
787 nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
788 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
790 struct nouveau_mem *node = old_mem->mm_node;
791 struct nouveau_bo *nvbo = nouveau_bo(bo);
792 u64 length = (new_mem->num_pages << PAGE_SHIFT);
793 u64 src_offset = node->vma[0].offset;
794 u64 dst_offset = node->vma[1].offset;
798 u32 amount, stride, height;
800 amount = min(length, (u64)(4 * 1024 * 1024));
802 height = amount / stride;
804 if (new_mem->mem_type == TTM_PL_VRAM &&
805 nouveau_bo_tile_layout(nvbo)) {
806 ret = RING_SPACE(chan, 8);
810 BEGIN_NV04(chan, NvSubCopy, 0x0200, 7);
813 OUT_RING (chan, stride);
814 OUT_RING (chan, height);
819 ret = RING_SPACE(chan, 2);
823 BEGIN_NV04(chan, NvSubCopy, 0x0200, 1);
826 if (old_mem->mem_type == TTM_PL_VRAM &&
827 nouveau_bo_tile_layout(nvbo)) {
828 ret = RING_SPACE(chan, 8);
832 BEGIN_NV04(chan, NvSubCopy, 0x021c, 7);
835 OUT_RING (chan, stride);
836 OUT_RING (chan, height);
841 ret = RING_SPACE(chan, 2);
845 BEGIN_NV04(chan, NvSubCopy, 0x021c, 1);
849 ret = RING_SPACE(chan, 14);
853 BEGIN_NV04(chan, NvSubCopy, 0x0238, 2);
854 OUT_RING (chan, upper_32_bits(src_offset));
855 OUT_RING (chan, upper_32_bits(dst_offset));
856 BEGIN_NV04(chan, NvSubCopy, 0x030c, 8);
857 OUT_RING (chan, lower_32_bits(src_offset));
858 OUT_RING (chan, lower_32_bits(dst_offset));
859 OUT_RING (chan, stride);
860 OUT_RING (chan, stride);
861 OUT_RING (chan, stride);
862 OUT_RING (chan, height);
863 OUT_RING (chan, 0x00000101);
864 OUT_RING (chan, 0x00000000);
865 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
869 src_offset += amount;
870 dst_offset += amount;
877 nv04_bo_move_init(struct nouveau_channel *chan, u32 handle)
879 int ret = RING_SPACE(chan, 4);
881 BEGIN_NV04(chan, NvSubCopy, 0x0000, 1);
882 OUT_RING (chan, handle);
883 BEGIN_NV04(chan, NvSubCopy, 0x0180, 1);
884 OUT_RING (chan, NvNotify0);
890 static inline uint32_t
891 nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo,
892 struct nouveau_channel *chan, struct ttm_mem_reg *mem)
894 if (mem->mem_type == TTM_PL_TT)
900 nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
901 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
903 u32 src_offset = old_mem->start << PAGE_SHIFT;
904 u32 dst_offset = new_mem->start << PAGE_SHIFT;
905 u32 page_count = new_mem->num_pages;
908 ret = RING_SPACE(chan, 3);
912 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2);
913 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, old_mem));
914 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, new_mem));
916 page_count = new_mem->num_pages;
918 int line_count = (page_count > 2047) ? 2047 : page_count;
920 ret = RING_SPACE(chan, 11);
924 BEGIN_NV04(chan, NvSubCopy,
925 NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
926 OUT_RING (chan, src_offset);
927 OUT_RING (chan, dst_offset);
928 OUT_RING (chan, PAGE_SIZE); /* src_pitch */
929 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */
930 OUT_RING (chan, PAGE_SIZE); /* line_length */
931 OUT_RING (chan, line_count);
932 OUT_RING (chan, 0x00000101);
933 OUT_RING (chan, 0x00000000);
934 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
937 page_count -= line_count;
938 src_offset += (PAGE_SIZE * line_count);
939 dst_offset += (PAGE_SIZE * line_count);
946 nouveau_vma_getmap(struct nouveau_channel *chan, struct nouveau_bo *nvbo,
947 struct ttm_mem_reg *mem, struct nouveau_vma *vma)
949 struct nouveau_mem *node = mem->mm_node;
952 ret = nouveau_vm_get(nv_client(chan->cli)->vm, mem->num_pages <<
953 PAGE_SHIFT, node->page_shift,
954 NV_MEM_ACCESS_RW, vma);
958 if (mem->mem_type == TTM_PL_VRAM)
959 nouveau_vm_map(vma, node);
961 nouveau_vm_map_sg(vma, 0, mem->num_pages << PAGE_SHIFT, node);
967 nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr,
968 bool no_wait_reserve, bool no_wait_gpu,
969 struct ttm_mem_reg *new_mem)
971 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
972 struct nouveau_channel *chan = chan = drm->channel;
973 struct nouveau_bo *nvbo = nouveau_bo(bo);
974 struct ttm_mem_reg *old_mem = &bo->mem;
977 mutex_lock(&chan->cli->mutex);
979 /* create temporary vmas for the transfer and attach them to the
980 * old nouveau_mem node, these will get cleaned up after ttm has
981 * destroyed the ttm_mem_reg
983 if (nv_device(drm->device)->card_type >= NV_50) {
984 struct nouveau_mem *node = old_mem->mm_node;
986 ret = nouveau_vma_getmap(chan, nvbo, old_mem, &node->vma[0]);
990 ret = nouveau_vma_getmap(chan, nvbo, new_mem, &node->vma[1]);
995 ret = drm->ttm.move(chan, bo, &bo->mem, new_mem);
997 ret = nouveau_bo_move_accel_cleanup(chan, nvbo, evict,
999 no_wait_gpu, new_mem);
1003 mutex_unlock(&chan->cli->mutex);
1008 nouveau_bo_move_init(struct nouveau_drm *drm)
1010 static const struct {
1014 int (*exec)(struct nouveau_channel *,
1015 struct ttm_buffer_object *,
1016 struct ttm_mem_reg *, struct ttm_mem_reg *);
1017 int (*init)(struct nouveau_channel *, u32 handle);
1019 { "COPY", 0, 0xa0b5, nve0_bo_move_copy, nve0_bo_move_init },
1020 { "GRCE", 0, 0xa0b5, nve0_bo_move_copy, nvc0_bo_move_init },
1021 { "COPY1", 5, 0x90b8, nvc0_bo_move_copy, nvc0_bo_move_init },
1022 { "COPY0", 4, 0x90b5, nvc0_bo_move_copy, nvc0_bo_move_init },
1023 { "COPY", 0, 0x85b5, nva3_bo_move_copy, nv50_bo_move_init },
1024 { "CRYPT", 0, 0x74c1, nv84_bo_move_exec, nv50_bo_move_init },
1025 { "M2MF", 0, 0x9039, nvc0_bo_move_m2mf, nvc0_bo_move_init },
1026 { "M2MF", 0, 0x5039, nv50_bo_move_m2mf, nv50_bo_move_init },
1027 { "M2MF", 0, 0x0039, nv04_bo_move_m2mf, nv04_bo_move_init },
1029 { "CRYPT", 0, 0x88b4, nv98_bo_move_exec, nv50_bo_move_init },
1030 }, *mthd = _methods;
1031 const char *name = "CPU";
1035 struct nouveau_object *object;
1036 struct nouveau_channel *chan;
1037 u32 handle = (mthd->engine << 16) | mthd->oclass;
1039 if (mthd->init == nve0_bo_move_init)
1042 chan = drm->channel;
1046 ret = nouveau_object_new(nv_object(drm), chan->handle, handle,
1047 mthd->oclass, NULL, 0, &object);
1049 ret = mthd->init(chan, handle);
1051 nouveau_object_del(nv_object(drm),
1052 chan->handle, handle);
1056 drm->ttm.move = mthd->exec;
1060 } while ((++mthd)->exec);
1062 NV_INFO(drm, "MM: using %s for buffer copies\n", name);
1066 nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
1067 bool no_wait_reserve, bool no_wait_gpu,
1068 struct ttm_mem_reg *new_mem)
1070 u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
1071 struct ttm_placement placement;
1072 struct ttm_mem_reg tmp_mem;
1075 placement.fpfn = placement.lpfn = 0;
1076 placement.num_placement = placement.num_busy_placement = 1;
1077 placement.placement = placement.busy_placement = &placement_memtype;
1080 tmp_mem.mm_node = NULL;
1081 ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_reserve, no_wait_gpu);
1085 ret = ttm_tt_bind(bo->ttm, &tmp_mem);
1089 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_reserve, no_wait_gpu, &tmp_mem);
1093 ret = ttm_bo_move_ttm(bo, true, no_wait_reserve, no_wait_gpu, new_mem);
1095 ttm_bo_mem_put(bo, &tmp_mem);
1100 nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
1101 bool no_wait_reserve, bool no_wait_gpu,
1102 struct ttm_mem_reg *new_mem)
1104 u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
1105 struct ttm_placement placement;
1106 struct ttm_mem_reg tmp_mem;
1109 placement.fpfn = placement.lpfn = 0;
1110 placement.num_placement = placement.num_busy_placement = 1;
1111 placement.placement = placement.busy_placement = &placement_memtype;
1114 tmp_mem.mm_node = NULL;
1115 ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_reserve, no_wait_gpu);
1119 ret = ttm_bo_move_ttm(bo, true, no_wait_reserve, no_wait_gpu, &tmp_mem);
1123 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_reserve, no_wait_gpu, new_mem);
1128 ttm_bo_mem_put(bo, &tmp_mem);
1133 nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem)
1135 struct nouveau_bo *nvbo = nouveau_bo(bo);
1136 struct nouveau_vma *vma;
1138 /* ttm can now (stupidly) pass the driver bos it didn't create... */
1139 if (bo->destroy != nouveau_bo_del_ttm)
1142 list_for_each_entry(vma, &nvbo->vma_list, head) {
1143 if (new_mem && new_mem->mem_type == TTM_PL_VRAM) {
1144 nouveau_vm_map(vma, new_mem->mm_node);
1146 if (new_mem && new_mem->mem_type == TTM_PL_TT &&
1147 nvbo->page_shift == vma->vm->vmm->spg_shift) {
1148 if (((struct nouveau_mem *)new_mem->mm_node)->sg)
1149 nouveau_vm_map_sg_table(vma, 0, new_mem->
1150 num_pages << PAGE_SHIFT,
1153 nouveau_vm_map_sg(vma, 0, new_mem->
1154 num_pages << PAGE_SHIFT,
1157 nouveau_vm_unmap(vma);
1163 nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem,
1164 struct nouveau_drm_tile **new_tile)
1166 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1167 struct drm_device *dev = drm->dev;
1168 struct nouveau_bo *nvbo = nouveau_bo(bo);
1169 u64 offset = new_mem->start << PAGE_SHIFT;
1172 if (new_mem->mem_type != TTM_PL_VRAM)
1175 if (nv_device(drm->device)->card_type >= NV_10) {
1176 *new_tile = nv10_bo_set_tiling(dev, offset, new_mem->size,
1185 nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
1186 struct nouveau_drm_tile *new_tile,
1187 struct nouveau_drm_tile **old_tile)
1189 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1190 struct drm_device *dev = drm->dev;
1192 nv10_bo_put_tile_region(dev, *old_tile, bo->sync_obj);
1193 *old_tile = new_tile;
1197 nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr,
1198 bool no_wait_reserve, bool no_wait_gpu,
1199 struct ttm_mem_reg *new_mem)
1201 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1202 struct nouveau_bo *nvbo = nouveau_bo(bo);
1203 struct ttm_mem_reg *old_mem = &bo->mem;
1204 struct nouveau_drm_tile *new_tile = NULL;
1207 if (nv_device(drm->device)->card_type < NV_50) {
1208 ret = nouveau_bo_vm_bind(bo, new_mem, &new_tile);
1214 if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
1215 BUG_ON(bo->mem.mm_node != NULL);
1217 new_mem->mm_node = NULL;
1221 /* CPU copy if we have no accelerated method available */
1222 if (!drm->ttm.move) {
1223 ret = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
1227 /* Hardware assisted copy. */
1228 if (new_mem->mem_type == TTM_PL_SYSTEM)
1229 ret = nouveau_bo_move_flipd(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
1230 else if (old_mem->mem_type == TTM_PL_SYSTEM)
1231 ret = nouveau_bo_move_flips(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
1233 ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
1238 /* Fallback to software copy. */
1239 ret = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
1242 if (nv_device(drm->device)->card_type < NV_50) {
1244 nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
1246 nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
1253 nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp)
1259 nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
1261 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
1262 struct nouveau_drm *drm = nouveau_bdev(bdev);
1263 struct drm_device *dev = drm->dev;
1266 mem->bus.addr = NULL;
1267 mem->bus.offset = 0;
1268 mem->bus.size = mem->num_pages << PAGE_SHIFT;
1270 mem->bus.is_iomem = false;
1271 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
1273 switch (mem->mem_type) {
1279 if (drm->agp.stat == ENABLED) {
1280 mem->bus.offset = mem->start << PAGE_SHIFT;
1281 mem->bus.base = drm->agp.base;
1282 mem->bus.is_iomem = true;
1287 mem->bus.offset = mem->start << PAGE_SHIFT;
1288 mem->bus.base = pci_resource_start(dev->pdev, 1);
1289 mem->bus.is_iomem = true;
1290 if (nv_device(drm->device)->card_type >= NV_50) {
1291 struct nouveau_bar *bar = nouveau_bar(drm->device);
1292 struct nouveau_mem *node = mem->mm_node;
1294 ret = bar->umap(bar, node, NV_MEM_ACCESS_RW,
1299 mem->bus.offset = node->bar_vma.offset;
1309 nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
1311 struct nouveau_drm *drm = nouveau_bdev(bdev);
1312 struct nouveau_bar *bar = nouveau_bar(drm->device);
1313 struct nouveau_mem *node = mem->mm_node;
1315 if (!node->bar_vma.node)
1318 bar->unmap(bar, &node->bar_vma);
1322 nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
1324 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1325 struct nouveau_bo *nvbo = nouveau_bo(bo);
1326 struct nouveau_device *device = nv_device(drm->device);
1327 u32 mappable = pci_resource_len(device->pdev, 1) >> PAGE_SHIFT;
1329 /* as long as the bo isn't in vram, and isn't tiled, we've got
1330 * nothing to do here.
1332 if (bo->mem.mem_type != TTM_PL_VRAM) {
1333 if (nv_device(drm->device)->card_type < NV_50 ||
1334 !nouveau_bo_tile_layout(nvbo))
1338 /* make sure bo is in mappable vram */
1339 if (bo->mem.start + bo->mem.num_pages < mappable)
1343 nvbo->placement.fpfn = 0;
1344 nvbo->placement.lpfn = mappable;
1345 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_VRAM, 0);
1346 return nouveau_bo_validate(nvbo, false, true, false);
1350 nouveau_ttm_tt_populate(struct ttm_tt *ttm)
1352 struct ttm_dma_tt *ttm_dma = (void *)ttm;
1353 struct nouveau_drm *drm;
1354 struct drm_device *dev;
1357 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1359 if (ttm->state != tt_unpopulated)
1362 if (slave && ttm->sg) {
1363 /* make userspace faulting work */
1364 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1365 ttm_dma->dma_address, ttm->num_pages);
1366 ttm->state = tt_unbound;
1370 drm = nouveau_bdev(ttm->bdev);
1374 if (drm->agp.stat == ENABLED) {
1375 return ttm_agp_tt_populate(ttm);
1379 #ifdef CONFIG_SWIOTLB
1380 if (swiotlb_nr_tbl()) {
1381 return ttm_dma_populate((void *)ttm, dev->dev);
1385 r = ttm_pool_populate(ttm);
1390 for (i = 0; i < ttm->num_pages; i++) {
1391 ttm_dma->dma_address[i] = pci_map_page(dev->pdev, ttm->pages[i],
1393 PCI_DMA_BIDIRECTIONAL);
1394 if (pci_dma_mapping_error(dev->pdev, ttm_dma->dma_address[i])) {
1396 pci_unmap_page(dev->pdev, ttm_dma->dma_address[i],
1397 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
1398 ttm_dma->dma_address[i] = 0;
1400 ttm_pool_unpopulate(ttm);
1408 nouveau_ttm_tt_unpopulate(struct ttm_tt *ttm)
1410 struct ttm_dma_tt *ttm_dma = (void *)ttm;
1411 struct nouveau_drm *drm;
1412 struct drm_device *dev;
1414 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1419 drm = nouveau_bdev(ttm->bdev);
1423 if (drm->agp.stat == ENABLED) {
1424 ttm_agp_tt_unpopulate(ttm);
1429 #ifdef CONFIG_SWIOTLB
1430 if (swiotlb_nr_tbl()) {
1431 ttm_dma_unpopulate((void *)ttm, dev->dev);
1436 for (i = 0; i < ttm->num_pages; i++) {
1437 if (ttm_dma->dma_address[i]) {
1438 pci_unmap_page(dev->pdev, ttm_dma->dma_address[i],
1439 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
1443 ttm_pool_unpopulate(ttm);
1447 nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence)
1449 struct nouveau_fence *old_fence = NULL;
1452 nouveau_fence_ref(fence);
1454 spin_lock(&nvbo->bo.bdev->fence_lock);
1455 old_fence = nvbo->bo.sync_obj;
1456 nvbo->bo.sync_obj = fence;
1457 spin_unlock(&nvbo->bo.bdev->fence_lock);
1459 nouveau_fence_unref(&old_fence);
1463 nouveau_bo_fence_unref(void **sync_obj)
1465 nouveau_fence_unref((struct nouveau_fence **)sync_obj);
1469 nouveau_bo_fence_ref(void *sync_obj)
1471 return nouveau_fence_ref(sync_obj);
1475 nouveau_bo_fence_signalled(void *sync_obj, void *sync_arg)
1477 return nouveau_fence_done(sync_obj);
1481 nouveau_bo_fence_wait(void *sync_obj, void *sync_arg, bool lazy, bool intr)
1483 return nouveau_fence_wait(sync_obj, lazy, intr);
1487 nouveau_bo_fence_flush(void *sync_obj, void *sync_arg)
1492 struct ttm_bo_driver nouveau_bo_driver = {
1493 .ttm_tt_create = &nouveau_ttm_tt_create,
1494 .ttm_tt_populate = &nouveau_ttm_tt_populate,
1495 .ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate,
1496 .invalidate_caches = nouveau_bo_invalidate_caches,
1497 .init_mem_type = nouveau_bo_init_mem_type,
1498 .evict_flags = nouveau_bo_evict_flags,
1499 .move_notify = nouveau_bo_move_ntfy,
1500 .move = nouveau_bo_move,
1501 .verify_access = nouveau_bo_verify_access,
1502 .sync_obj_signaled = nouveau_bo_fence_signalled,
1503 .sync_obj_wait = nouveau_bo_fence_wait,
1504 .sync_obj_flush = nouveau_bo_fence_flush,
1505 .sync_obj_unref = nouveau_bo_fence_unref,
1506 .sync_obj_ref = nouveau_bo_fence_ref,
1507 .fault_reserve_notify = &nouveau_ttm_fault_reserve_notify,
1508 .io_mem_reserve = &nouveau_ttm_io_mem_reserve,
1509 .io_mem_free = &nouveau_ttm_io_mem_free,
1512 struct nouveau_vma *
1513 nouveau_bo_vma_find(struct nouveau_bo *nvbo, struct nouveau_vm *vm)
1515 struct nouveau_vma *vma;
1516 list_for_each_entry(vma, &nvbo->vma_list, head) {
1525 nouveau_bo_vma_add(struct nouveau_bo *nvbo, struct nouveau_vm *vm,
1526 struct nouveau_vma *vma)
1528 const u32 size = nvbo->bo.mem.num_pages << PAGE_SHIFT;
1529 struct nouveau_mem *node = nvbo->bo.mem.mm_node;
1532 ret = nouveau_vm_get(vm, size, nvbo->page_shift,
1533 NV_MEM_ACCESS_RW, vma);
1537 if (nvbo->bo.mem.mem_type == TTM_PL_VRAM)
1538 nouveau_vm_map(vma, nvbo->bo.mem.mm_node);
1539 else if (nvbo->bo.mem.mem_type == TTM_PL_TT) {
1541 nouveau_vm_map_sg_table(vma, 0, size, node);
1543 nouveau_vm_map_sg(vma, 0, size, node);
1546 list_add_tail(&vma->head, &nvbo->vma_list);
1552 nouveau_bo_vma_del(struct nouveau_bo *nvbo, struct nouveau_vma *vma)
1555 if (nvbo->bo.mem.mem_type != TTM_PL_SYSTEM) {
1556 spin_lock(&nvbo->bo.bdev->fence_lock);
1557 ttm_bo_wait(&nvbo->bo, false, false, false);
1558 spin_unlock(&nvbo->bo.bdev->fence_lock);
1559 nouveau_vm_unmap(vma);
1562 nouveau_vm_put(vma);
1563 list_del(&vma->head);