2 * Copyright 2007 Dave Airlied
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 * Authors: Dave Airlied <airlied@linux.ie>
26 * Ben Skeggs <darktama@iinet.net.au>
27 * Jeremy Kolb <jkolb@brandeis.edu>
32 #include "nouveau_drm.h"
33 #include "nouveau_drv.h"
34 #include "nouveau_dma.h"
36 #include <linux/log2.h>
39 nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
41 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
42 struct drm_device *dev = dev_priv->dev;
43 struct nouveau_bo *nvbo = nouveau_bo(bo);
45 ttm_bo_kunmap(&nvbo->kmap);
47 if (unlikely(nvbo->gem))
48 DRM_ERROR("bo %p still attached to GEM object\n", bo);
51 nv10_mem_expire_tiling(dev, nvbo->tile, NULL);
53 spin_lock(&dev_priv->ttm.bo_list_lock);
54 list_del(&nvbo->head);
55 spin_unlock(&dev_priv->ttm.bo_list_lock);
60 nouveau_bo_fixup_align(struct drm_device *dev,
61 uint32_t tile_mode, uint32_t tile_flags,
62 int *align, int *size)
64 struct drm_nouveau_private *dev_priv = dev->dev_private;
67 * Some of the tile_flags have a periodic structure of N*4096 bytes,
68 * align to to that as well as the page size. Align the size to the
69 * appropriate boundaries. This does imply that sizes are rounded up
70 * 3-7 pages, so be aware of this and do not waste memory by allocating
73 if (dev_priv->card_type == NV_50) {
74 uint32_t block_size = nouveau_mem_fb_amount(dev) >> 15;
82 if (is_power_of_2(block_size)) {
83 for (i = 1; i < 10; i++) {
84 *align = 12 * i * block_size;
85 if (!(*align % 65536))
89 for (i = 1; i < 10; i++) {
90 *align = 8 * i * block_size;
91 if (!(*align % 65536))
95 *size = roundup(*size, *align);
103 if (dev_priv->chipset >= 0x40) {
105 *size = roundup(*size, 64 * tile_mode);
107 } else if (dev_priv->chipset >= 0x30) {
109 *size = roundup(*size, 64 * tile_mode);
111 } else if (dev_priv->chipset >= 0x20) {
113 *size = roundup(*size, 64 * tile_mode);
115 } else if (dev_priv->chipset >= 0x10) {
117 *size = roundup(*size, 32 * tile_mode);
122 /* ALIGN works only on powers of two. */
123 *size = roundup(*size, PAGE_SIZE);
125 if (dev_priv->card_type == NV_50) {
126 *size = roundup(*size, 65536);
127 *align = max(65536, *align);
132 nouveau_bo_new(struct drm_device *dev, struct nouveau_channel *chan,
133 int size, int align, uint32_t flags, uint32_t tile_mode,
134 uint32_t tile_flags, bool no_vm, bool mappable,
135 struct nouveau_bo **pnvbo)
137 struct drm_nouveau_private *dev_priv = dev->dev_private;
138 struct nouveau_bo *nvbo;
141 nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
144 INIT_LIST_HEAD(&nvbo->head);
145 INIT_LIST_HEAD(&nvbo->entry);
146 nvbo->mappable = mappable;
148 nvbo->tile_mode = tile_mode;
149 nvbo->tile_flags = tile_flags;
151 nouveau_bo_fixup_align(dev, tile_mode, tile_flags, &align, &size);
152 align >>= PAGE_SHIFT;
154 nvbo->placement.fpfn = 0;
155 nvbo->placement.lpfn = mappable ? dev_priv->fb_mappable_pages : 0;
156 nouveau_bo_placement_set(nvbo, flags, 0);
158 nvbo->channel = chan;
159 ret = ttm_bo_init(&dev_priv->ttm.bdev, &nvbo->bo, size,
160 ttm_bo_type_device, &nvbo->placement, align, 0,
161 false, NULL, size, nouveau_bo_del_ttm);
162 nvbo->channel = NULL;
164 /* ttm will call nouveau_bo_del_ttm if it fails.. */
168 spin_lock(&dev_priv->ttm.bo_list_lock);
169 list_add_tail(&nvbo->head, &dev_priv->ttm.bo_list);
170 spin_unlock(&dev_priv->ttm.bo_list_lock);
176 set_placement_list(uint32_t *pl, unsigned *n, uint32_t type, uint32_t flags)
180 if (type & TTM_PL_FLAG_VRAM)
181 pl[(*n)++] = TTM_PL_FLAG_VRAM | flags;
182 if (type & TTM_PL_FLAG_TT)
183 pl[(*n)++] = TTM_PL_FLAG_TT | flags;
184 if (type & TTM_PL_FLAG_SYSTEM)
185 pl[(*n)++] = TTM_PL_FLAG_SYSTEM | flags;
189 nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy)
191 struct ttm_placement *pl = &nvbo->placement;
192 uint32_t flags = TTM_PL_MASK_CACHING |
193 (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0);
195 pl->placement = nvbo->placements;
196 set_placement_list(nvbo->placements, &pl->num_placement,
199 pl->busy_placement = nvbo->busy_placements;
200 set_placement_list(nvbo->busy_placements, &pl->num_busy_placement,
205 nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype)
207 struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
208 struct ttm_buffer_object *bo = &nvbo->bo;
211 if (nvbo->pin_refcnt && !(memtype & (1 << bo->mem.mem_type))) {
212 NV_ERROR(nouveau_bdev(bo->bdev)->dev,
213 "bo %p pinned elsewhere: 0x%08x vs 0x%08x\n", bo,
214 1 << bo->mem.mem_type, memtype);
218 if (nvbo->pin_refcnt++)
221 ret = ttm_bo_reserve(bo, false, false, false, 0);
225 nouveau_bo_placement_set(nvbo, memtype, 0);
227 ret = ttm_bo_validate(bo, &nvbo->placement, false, false);
229 switch (bo->mem.mem_type) {
231 dev_priv->fb_aper_free -= bo->mem.size;
234 dev_priv->gart_info.aper_free -= bo->mem.size;
240 ttm_bo_unreserve(bo);
248 nouveau_bo_unpin(struct nouveau_bo *nvbo)
250 struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
251 struct ttm_buffer_object *bo = &nvbo->bo;
254 if (--nvbo->pin_refcnt)
257 ret = ttm_bo_reserve(bo, false, false, false, 0);
261 nouveau_bo_placement_set(nvbo, bo->mem.placement, 0);
263 ret = ttm_bo_validate(bo, &nvbo->placement, false, false);
265 switch (bo->mem.mem_type) {
267 dev_priv->fb_aper_free += bo->mem.size;
270 dev_priv->gart_info.aper_free += bo->mem.size;
277 ttm_bo_unreserve(bo);
282 nouveau_bo_map(struct nouveau_bo *nvbo)
286 ret = ttm_bo_reserve(&nvbo->bo, false, false, false, 0);
290 ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap);
291 ttm_bo_unreserve(&nvbo->bo);
296 nouveau_bo_unmap(struct nouveau_bo *nvbo)
298 ttm_bo_kunmap(&nvbo->kmap);
302 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index)
305 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
308 return ioread16_native((void __force __iomem *)mem);
314 nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
317 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
320 iowrite16_native(val, (void __force __iomem *)mem);
326 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
329 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
332 return ioread32_native((void __force __iomem *)mem);
338 nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
341 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
344 iowrite32_native(val, (void __force __iomem *)mem);
349 static struct ttm_backend *
350 nouveau_bo_create_ttm_backend_entry(struct ttm_bo_device *bdev)
352 struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
353 struct drm_device *dev = dev_priv->dev;
355 switch (dev_priv->gart_info.type) {
357 case NOUVEAU_GART_AGP:
358 return ttm_agp_backend_init(bdev, dev->agp->bridge);
360 case NOUVEAU_GART_SGDMA:
361 return nouveau_sgdma_init_ttm(dev);
363 NV_ERROR(dev, "Unknown GART type %d\n",
364 dev_priv->gart_info.type);
372 nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
374 /* We'll do this from user space. */
379 nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
380 struct ttm_mem_type_manager *man)
382 struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
383 struct drm_device *dev = dev_priv->dev;
387 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
388 man->available_caching = TTM_PL_MASK_CACHING;
389 man->default_caching = TTM_PL_FLAG_CACHED;
392 man->flags = TTM_MEMTYPE_FLAG_FIXED |
393 TTM_MEMTYPE_FLAG_MAPPABLE |
394 TTM_MEMTYPE_FLAG_NEEDS_IOREMAP;
395 man->available_caching = TTM_PL_FLAG_UNCACHED |
397 man->default_caching = TTM_PL_FLAG_WC;
400 man->io_offset = drm_get_resource_start(dev, 1);
401 man->io_size = drm_get_resource_len(dev, 1);
402 if (man->io_size > nouveau_mem_fb_amount(dev))
403 man->io_size = nouveau_mem_fb_amount(dev);
405 man->gpu_offset = dev_priv->vm_vram_base;
408 switch (dev_priv->gart_info.type) {
409 case NOUVEAU_GART_AGP:
410 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE |
411 TTM_MEMTYPE_FLAG_NEEDS_IOREMAP;
412 man->available_caching = TTM_PL_FLAG_UNCACHED;
413 man->default_caching = TTM_PL_FLAG_UNCACHED;
415 case NOUVEAU_GART_SGDMA:
416 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE |
417 TTM_MEMTYPE_FLAG_CMA;
418 man->available_caching = TTM_PL_MASK_CACHING;
419 man->default_caching = TTM_PL_FLAG_CACHED;
422 NV_ERROR(dev, "Unknown GART type: %d\n",
423 dev_priv->gart_info.type);
427 man->io_offset = dev_priv->gart_info.aper_base;
428 man->io_size = dev_priv->gart_info.aper_size;
430 man->gpu_offset = dev_priv->vm_gart_base;
433 NV_ERROR(dev, "Unsupported memory type %u\n", (unsigned)type);
440 nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
442 struct nouveau_bo *nvbo = nouveau_bo(bo);
444 switch (bo->mem.mem_type) {
446 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT,
450 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0);
454 *pl = nvbo->placement;
458 /* GPU-assisted copy using NV_MEMORY_TO_MEMORY_FORMAT, can access
459 * TTM_PL_{VRAM,TT} directly.
463 nouveau_bo_move_accel_cleanup(struct nouveau_channel *chan,
464 struct nouveau_bo *nvbo, bool evict, bool no_wait,
465 struct ttm_mem_reg *new_mem)
467 struct nouveau_fence *fence = NULL;
470 ret = nouveau_fence_new(chan, &fence, true);
474 ret = ttm_bo_move_accel_cleanup(&nvbo->bo, fence, NULL,
475 evict, no_wait, new_mem);
476 if (nvbo->channel && nvbo->channel != chan)
477 ret = nouveau_fence_wait(fence, NULL, false, false);
478 nouveau_fence_unref((void *)&fence);
482 static inline uint32_t
483 nouveau_bo_mem_ctxdma(struct nouveau_bo *nvbo, struct nouveau_channel *chan,
484 struct ttm_mem_reg *mem)
486 if (chan == nouveau_bdev(nvbo->bo.bdev)->channel) {
487 if (mem->mem_type == TTM_PL_TT)
492 if (mem->mem_type == TTM_PL_TT)
493 return chan->gart_handle;
494 return chan->vram_handle;
498 nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr,
499 int no_wait, struct ttm_mem_reg *new_mem)
501 struct nouveau_bo *nvbo = nouveau_bo(bo);
502 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
503 struct ttm_mem_reg *old_mem = &bo->mem;
504 struct nouveau_channel *chan;
505 uint64_t src_offset, dst_offset;
509 chan = nvbo->channel;
510 if (!chan || nvbo->tile_flags || nvbo->no_vm)
511 chan = dev_priv->channel;
513 src_offset = old_mem->mm_node->start << PAGE_SHIFT;
514 dst_offset = new_mem->mm_node->start << PAGE_SHIFT;
515 if (chan != dev_priv->channel) {
516 if (old_mem->mem_type == TTM_PL_TT)
517 src_offset += dev_priv->vm_gart_base;
519 src_offset += dev_priv->vm_vram_base;
521 if (new_mem->mem_type == TTM_PL_TT)
522 dst_offset += dev_priv->vm_gart_base;
524 dst_offset += dev_priv->vm_vram_base;
527 ret = RING_SPACE(chan, 3);
530 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2);
531 OUT_RING(chan, nouveau_bo_mem_ctxdma(nvbo, chan, old_mem));
532 OUT_RING(chan, nouveau_bo_mem_ctxdma(nvbo, chan, new_mem));
534 if (dev_priv->card_type >= NV_50) {
535 ret = RING_SPACE(chan, 4);
538 BEGIN_RING(chan, NvSubM2MF, 0x0200, 1);
540 BEGIN_RING(chan, NvSubM2MF, 0x021c, 1);
544 page_count = new_mem->num_pages;
546 int line_count = (page_count > 2047) ? 2047 : page_count;
548 if (dev_priv->card_type >= NV_50) {
549 ret = RING_SPACE(chan, 3);
552 BEGIN_RING(chan, NvSubM2MF, 0x0238, 2);
553 OUT_RING(chan, upper_32_bits(src_offset));
554 OUT_RING(chan, upper_32_bits(dst_offset));
556 ret = RING_SPACE(chan, 11);
559 BEGIN_RING(chan, NvSubM2MF,
560 NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
561 OUT_RING(chan, lower_32_bits(src_offset));
562 OUT_RING(chan, lower_32_bits(dst_offset));
563 OUT_RING(chan, PAGE_SIZE); /* src_pitch */
564 OUT_RING(chan, PAGE_SIZE); /* dst_pitch */
565 OUT_RING(chan, PAGE_SIZE); /* line_length */
566 OUT_RING(chan, line_count);
567 OUT_RING(chan, (1<<8)|(1<<0));
569 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
572 page_count -= line_count;
573 src_offset += (PAGE_SIZE * line_count);
574 dst_offset += (PAGE_SIZE * line_count);
577 return nouveau_bo_move_accel_cleanup(chan, nvbo, evict, no_wait, new_mem);
581 nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
582 bool no_wait, struct ttm_mem_reg *new_mem)
584 u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
585 struct ttm_placement placement;
586 struct ttm_mem_reg tmp_mem;
589 placement.fpfn = placement.lpfn = 0;
590 placement.num_placement = placement.num_busy_placement = 1;
591 placement.placement = placement.busy_placement = &placement_memtype;
594 tmp_mem.mm_node = NULL;
595 ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait);
599 ret = ttm_tt_bind(bo->ttm, &tmp_mem);
603 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait, &tmp_mem);
607 ret = ttm_bo_move_ttm(bo, evict, no_wait, new_mem);
609 if (tmp_mem.mm_node) {
610 spin_lock(&bo->bdev->glob->lru_lock);
611 drm_mm_put_block(tmp_mem.mm_node);
612 spin_unlock(&bo->bdev->glob->lru_lock);
619 nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
620 bool no_wait, struct ttm_mem_reg *new_mem)
622 u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
623 struct ttm_placement placement;
624 struct ttm_mem_reg tmp_mem;
627 placement.fpfn = placement.lpfn = 0;
628 placement.num_placement = placement.num_busy_placement = 1;
629 placement.placement = placement.busy_placement = &placement_memtype;
632 tmp_mem.mm_node = NULL;
633 ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait);
637 ret = ttm_bo_move_ttm(bo, evict, no_wait, &tmp_mem);
641 ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait, new_mem);
646 if (tmp_mem.mm_node) {
647 spin_lock(&bo->bdev->glob->lru_lock);
648 drm_mm_put_block(tmp_mem.mm_node);
649 spin_unlock(&bo->bdev->glob->lru_lock);
656 nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem,
657 struct nouveau_tile_reg **new_tile)
659 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
660 struct drm_device *dev = dev_priv->dev;
661 struct nouveau_bo *nvbo = nouveau_bo(bo);
665 if (nvbo->no_vm || new_mem->mem_type != TTM_PL_VRAM) {
671 offset = new_mem->mm_node->start << PAGE_SHIFT;
673 if (dev_priv->card_type == NV_50) {
674 ret = nv50_mem_vm_bind_linear(dev,
675 offset + dev_priv->vm_vram_base,
676 new_mem->size, nvbo->tile_flags,
681 } else if (dev_priv->card_type >= NV_10) {
682 *new_tile = nv10_mem_set_tiling(dev, offset, new_mem->size,
690 nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
691 struct nouveau_tile_reg *new_tile,
692 struct nouveau_tile_reg **old_tile)
694 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
695 struct drm_device *dev = dev_priv->dev;
697 if (dev_priv->card_type >= NV_10 &&
698 dev_priv->card_type < NV_50) {
700 nv10_mem_expire_tiling(dev, *old_tile, bo->sync_obj);
702 *old_tile = new_tile;
707 nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr,
708 bool no_wait, struct ttm_mem_reg *new_mem)
710 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
711 struct nouveau_bo *nvbo = nouveau_bo(bo);
712 struct ttm_mem_reg *old_mem = &bo->mem;
713 struct nouveau_tile_reg *new_tile = NULL;
716 ret = nouveau_bo_vm_bind(bo, new_mem, &new_tile);
720 /* Software copy if the card isn't up and running yet. */
721 if (dev_priv->init_state != NOUVEAU_CARD_INIT_DONE ||
722 !dev_priv->channel) {
723 ret = ttm_bo_move_memcpy(bo, evict, no_wait, new_mem);
728 if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
729 BUG_ON(bo->mem.mm_node != NULL);
731 new_mem->mm_node = NULL;
735 /* Hardware assisted copy. */
736 if (new_mem->mem_type == TTM_PL_SYSTEM)
737 ret = nouveau_bo_move_flipd(bo, evict, intr, no_wait, new_mem);
738 else if (old_mem->mem_type == TTM_PL_SYSTEM)
739 ret = nouveau_bo_move_flips(bo, evict, intr, no_wait, new_mem);
741 ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait, new_mem);
746 /* Fallback to software copy. */
747 ret = ttm_bo_move_memcpy(bo, evict, no_wait, new_mem);
751 nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
753 nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
759 nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp)
764 struct ttm_bo_driver nouveau_bo_driver = {
765 .create_ttm_backend_entry = nouveau_bo_create_ttm_backend_entry,
766 .invalidate_caches = nouveau_bo_invalidate_caches,
767 .init_mem_type = nouveau_bo_init_mem_type,
768 .evict_flags = nouveau_bo_evict_flags,
769 .move = nouveau_bo_move,
770 .verify_access = nouveau_bo_verify_access,
771 .sync_obj_signaled = nouveau_fence_signalled,
772 .sync_obj_wait = nouveau_fence_wait,
773 .sync_obj_flush = nouveau_fence_flush,
774 .sync_obj_unref = nouveau_fence_unref,
775 .sync_obj_ref = nouveau_fence_ref,