2 * Copyright 2007 Dave Airlied
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 * Authors: Dave Airlied <airlied@linux.ie>
26 * Ben Skeggs <darktama@iinet.net.au>
27 * Jeremy Kolb <jkolb@brandeis.edu>
32 #include "nouveau_drm.h"
33 #include "nouveau_drv.h"
34 #include "nouveau_dma.h"
36 #include <linux/log2.h>
37 #include <linux/slab.h>
40 nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
42 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
43 struct drm_device *dev = dev_priv->dev;
44 struct nouveau_bo *nvbo = nouveau_bo(bo);
46 ttm_bo_kunmap(&nvbo->kmap);
48 if (unlikely(nvbo->gem))
49 DRM_ERROR("bo %p still attached to GEM object\n", bo);
52 nv10_mem_expire_tiling(dev, nvbo->tile, NULL);
54 spin_lock(&dev_priv->ttm.bo_list_lock);
55 list_del(&nvbo->head);
56 spin_unlock(&dev_priv->ttm.bo_list_lock);
61 nouveau_bo_fixup_align(struct drm_device *dev,
62 uint32_t tile_mode, uint32_t tile_flags,
63 int *align, int *size)
65 struct drm_nouveau_private *dev_priv = dev->dev_private;
68 * Some of the tile_flags have a periodic structure of N*4096 bytes,
69 * align to to that as well as the page size. Align the size to the
70 * appropriate boundaries. This does imply that sizes are rounded up
71 * 3-7 pages, so be aware of this and do not waste memory by allocating
74 if (dev_priv->card_type == NV_50) {
75 uint32_t block_size = dev_priv->vram_size >> 15;
83 if (is_power_of_2(block_size)) {
84 for (i = 1; i < 10; i++) {
85 *align = 12 * i * block_size;
86 if (!(*align % 65536))
90 for (i = 1; i < 10; i++) {
91 *align = 8 * i * block_size;
92 if (!(*align % 65536))
96 *size = roundup(*size, *align);
104 if (dev_priv->chipset >= 0x40) {
106 *size = roundup(*size, 64 * tile_mode);
108 } else if (dev_priv->chipset >= 0x30) {
110 *size = roundup(*size, 64 * tile_mode);
112 } else if (dev_priv->chipset >= 0x20) {
114 *size = roundup(*size, 64 * tile_mode);
116 } else if (dev_priv->chipset >= 0x10) {
118 *size = roundup(*size, 32 * tile_mode);
123 /* ALIGN works only on powers of two. */
124 *size = roundup(*size, PAGE_SIZE);
126 if (dev_priv->card_type == NV_50) {
127 *size = roundup(*size, 65536);
128 *align = max(65536, *align);
133 nouveau_bo_new(struct drm_device *dev, struct nouveau_channel *chan,
134 int size, int align, uint32_t flags, uint32_t tile_mode,
135 uint32_t tile_flags, bool no_vm, bool mappable,
136 struct nouveau_bo **pnvbo)
138 struct drm_nouveau_private *dev_priv = dev->dev_private;
139 struct nouveau_bo *nvbo;
142 nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
145 INIT_LIST_HEAD(&nvbo->head);
146 INIT_LIST_HEAD(&nvbo->entry);
147 nvbo->mappable = mappable;
149 nvbo->tile_mode = tile_mode;
150 nvbo->tile_flags = tile_flags;
152 nouveau_bo_fixup_align(dev, tile_mode, tile_flags, &align, &size);
153 align >>= PAGE_SHIFT;
155 nvbo->placement.fpfn = 0;
156 nvbo->placement.lpfn = mappable ? dev_priv->fb_mappable_pages : 0;
157 nouveau_bo_placement_set(nvbo, flags, 0);
159 nvbo->channel = chan;
160 ret = ttm_bo_init(&dev_priv->ttm.bdev, &nvbo->bo, size,
161 ttm_bo_type_device, &nvbo->placement, align, 0,
162 false, NULL, size, nouveau_bo_del_ttm);
164 /* ttm will call nouveau_bo_del_ttm if it fails.. */
167 nvbo->channel = NULL;
169 spin_lock(&dev_priv->ttm.bo_list_lock);
170 list_add_tail(&nvbo->head, &dev_priv->ttm.bo_list);
171 spin_unlock(&dev_priv->ttm.bo_list_lock);
177 set_placement_list(uint32_t *pl, unsigned *n, uint32_t type, uint32_t flags)
181 if (type & TTM_PL_FLAG_VRAM)
182 pl[(*n)++] = TTM_PL_FLAG_VRAM | flags;
183 if (type & TTM_PL_FLAG_TT)
184 pl[(*n)++] = TTM_PL_FLAG_TT | flags;
185 if (type & TTM_PL_FLAG_SYSTEM)
186 pl[(*n)++] = TTM_PL_FLAG_SYSTEM | flags;
190 nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy)
192 struct ttm_placement *pl = &nvbo->placement;
193 uint32_t flags = TTM_PL_MASK_CACHING |
194 (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0);
196 pl->placement = nvbo->placements;
197 set_placement_list(nvbo->placements, &pl->num_placement,
200 pl->busy_placement = nvbo->busy_placements;
201 set_placement_list(nvbo->busy_placements, &pl->num_busy_placement,
206 nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype)
208 struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
209 struct ttm_buffer_object *bo = &nvbo->bo;
212 if (nvbo->pin_refcnt && !(memtype & (1 << bo->mem.mem_type))) {
213 NV_ERROR(nouveau_bdev(bo->bdev)->dev,
214 "bo %p pinned elsewhere: 0x%08x vs 0x%08x\n", bo,
215 1 << bo->mem.mem_type, memtype);
219 if (nvbo->pin_refcnt++)
222 ret = ttm_bo_reserve(bo, false, false, false, 0);
226 nouveau_bo_placement_set(nvbo, memtype, 0);
228 ret = ttm_bo_validate(bo, &nvbo->placement, false, false, false);
230 switch (bo->mem.mem_type) {
232 dev_priv->fb_aper_free -= bo->mem.size;
235 dev_priv->gart_info.aper_free -= bo->mem.size;
241 ttm_bo_unreserve(bo);
249 nouveau_bo_unpin(struct nouveau_bo *nvbo)
251 struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
252 struct ttm_buffer_object *bo = &nvbo->bo;
255 if (--nvbo->pin_refcnt)
258 ret = ttm_bo_reserve(bo, false, false, false, 0);
262 nouveau_bo_placement_set(nvbo, bo->mem.placement, 0);
264 ret = ttm_bo_validate(bo, &nvbo->placement, false, false, false);
266 switch (bo->mem.mem_type) {
268 dev_priv->fb_aper_free += bo->mem.size;
271 dev_priv->gart_info.aper_free += bo->mem.size;
278 ttm_bo_unreserve(bo);
283 nouveau_bo_map(struct nouveau_bo *nvbo)
287 ret = ttm_bo_reserve(&nvbo->bo, false, false, false, 0);
291 ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap);
292 ttm_bo_unreserve(&nvbo->bo);
297 nouveau_bo_unmap(struct nouveau_bo *nvbo)
299 ttm_bo_kunmap(&nvbo->kmap);
303 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index)
306 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
309 return ioread16_native((void __force __iomem *)mem);
315 nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
318 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
321 iowrite16_native(val, (void __force __iomem *)mem);
327 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
330 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
333 return ioread32_native((void __force __iomem *)mem);
339 nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
342 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
345 iowrite32_native(val, (void __force __iomem *)mem);
350 static struct ttm_backend *
351 nouveau_bo_create_ttm_backend_entry(struct ttm_bo_device *bdev)
353 struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
354 struct drm_device *dev = dev_priv->dev;
356 switch (dev_priv->gart_info.type) {
358 case NOUVEAU_GART_AGP:
359 return ttm_agp_backend_init(bdev, dev->agp->bridge);
361 case NOUVEAU_GART_SGDMA:
362 return nouveau_sgdma_init_ttm(dev);
364 NV_ERROR(dev, "Unknown GART type %d\n",
365 dev_priv->gart_info.type);
373 nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
375 /* We'll do this from user space. */
380 nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
381 struct ttm_mem_type_manager *man)
383 struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
384 struct drm_device *dev = dev_priv->dev;
388 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
389 man->available_caching = TTM_PL_MASK_CACHING;
390 man->default_caching = TTM_PL_FLAG_CACHED;
393 man->flags = TTM_MEMTYPE_FLAG_FIXED |
394 TTM_MEMTYPE_FLAG_MAPPABLE;
395 man->available_caching = TTM_PL_FLAG_UNCACHED |
397 man->default_caching = TTM_PL_FLAG_WC;
398 man->gpu_offset = dev_priv->vm_vram_base;
401 switch (dev_priv->gart_info.type) {
402 case NOUVEAU_GART_AGP:
403 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
404 man->available_caching = TTM_PL_FLAG_UNCACHED;
405 man->default_caching = TTM_PL_FLAG_UNCACHED;
407 case NOUVEAU_GART_SGDMA:
408 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE |
409 TTM_MEMTYPE_FLAG_CMA;
410 man->available_caching = TTM_PL_MASK_CACHING;
411 man->default_caching = TTM_PL_FLAG_CACHED;
414 NV_ERROR(dev, "Unknown GART type: %d\n",
415 dev_priv->gart_info.type);
418 man->gpu_offset = dev_priv->vm_gart_base;
421 NV_ERROR(dev, "Unsupported memory type %u\n", (unsigned)type);
428 nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
430 struct nouveau_bo *nvbo = nouveau_bo(bo);
432 switch (bo->mem.mem_type) {
434 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT,
438 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0);
442 *pl = nvbo->placement;
446 /* GPU-assisted copy using NV_MEMORY_TO_MEMORY_FORMAT, can access
447 * TTM_PL_{VRAM,TT} directly.
451 nouveau_bo_move_accel_cleanup(struct nouveau_channel *chan,
452 struct nouveau_bo *nvbo, bool evict,
453 bool no_wait_reserve, bool no_wait_gpu,
454 struct ttm_mem_reg *new_mem)
456 struct nouveau_fence *fence = NULL;
459 ret = nouveau_fence_new(chan, &fence, true);
463 ret = ttm_bo_move_accel_cleanup(&nvbo->bo, fence, NULL,
464 evict, no_wait_reserve, no_wait_gpu, new_mem);
465 if (nvbo->channel && nvbo->channel != chan)
466 ret = nouveau_fence_wait(fence, NULL, false, false);
467 nouveau_fence_unref((void *)&fence);
471 static inline uint32_t
472 nouveau_bo_mem_ctxdma(struct nouveau_bo *nvbo, struct nouveau_channel *chan,
473 struct ttm_mem_reg *mem)
475 if (chan == nouveau_bdev(nvbo->bo.bdev)->channel) {
476 if (mem->mem_type == TTM_PL_TT)
481 if (mem->mem_type == TTM_PL_TT)
482 return chan->gart_handle;
483 return chan->vram_handle;
487 nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr,
488 bool no_wait_reserve, bool no_wait_gpu,
489 struct ttm_mem_reg *new_mem)
491 struct nouveau_bo *nvbo = nouveau_bo(bo);
492 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
493 struct ttm_mem_reg *old_mem = &bo->mem;
494 struct nouveau_channel *chan;
495 uint64_t src_offset, dst_offset;
499 chan = nvbo->channel;
500 if (!chan || nvbo->tile_flags || nvbo->no_vm)
501 chan = dev_priv->channel;
503 src_offset = old_mem->mm_node->start << PAGE_SHIFT;
504 dst_offset = new_mem->mm_node->start << PAGE_SHIFT;
505 if (chan != dev_priv->channel) {
506 if (old_mem->mem_type == TTM_PL_TT)
507 src_offset += dev_priv->vm_gart_base;
509 src_offset += dev_priv->vm_vram_base;
511 if (new_mem->mem_type == TTM_PL_TT)
512 dst_offset += dev_priv->vm_gart_base;
514 dst_offset += dev_priv->vm_vram_base;
517 ret = RING_SPACE(chan, 3);
520 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2);
521 OUT_RING(chan, nouveau_bo_mem_ctxdma(nvbo, chan, old_mem));
522 OUT_RING(chan, nouveau_bo_mem_ctxdma(nvbo, chan, new_mem));
524 if (dev_priv->card_type >= NV_50) {
525 ret = RING_SPACE(chan, 4);
528 BEGIN_RING(chan, NvSubM2MF, 0x0200, 1);
530 BEGIN_RING(chan, NvSubM2MF, 0x021c, 1);
534 page_count = new_mem->num_pages;
536 int line_count = (page_count > 2047) ? 2047 : page_count;
538 if (dev_priv->card_type >= NV_50) {
539 ret = RING_SPACE(chan, 3);
542 BEGIN_RING(chan, NvSubM2MF, 0x0238, 2);
543 OUT_RING(chan, upper_32_bits(src_offset));
544 OUT_RING(chan, upper_32_bits(dst_offset));
546 ret = RING_SPACE(chan, 11);
549 BEGIN_RING(chan, NvSubM2MF,
550 NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
551 OUT_RING(chan, lower_32_bits(src_offset));
552 OUT_RING(chan, lower_32_bits(dst_offset));
553 OUT_RING(chan, PAGE_SIZE); /* src_pitch */
554 OUT_RING(chan, PAGE_SIZE); /* dst_pitch */
555 OUT_RING(chan, PAGE_SIZE); /* line_length */
556 OUT_RING(chan, line_count);
557 OUT_RING(chan, (1<<8)|(1<<0));
559 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
562 page_count -= line_count;
563 src_offset += (PAGE_SIZE * line_count);
564 dst_offset += (PAGE_SIZE * line_count);
567 return nouveau_bo_move_accel_cleanup(chan, nvbo, evict, no_wait_reserve, no_wait_gpu, new_mem);
571 nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
572 bool no_wait_reserve, bool no_wait_gpu,
573 struct ttm_mem_reg *new_mem)
575 u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
576 struct ttm_placement placement;
577 struct ttm_mem_reg tmp_mem;
580 placement.fpfn = placement.lpfn = 0;
581 placement.num_placement = placement.num_busy_placement = 1;
582 placement.placement = placement.busy_placement = &placement_memtype;
585 tmp_mem.mm_node = NULL;
586 ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_reserve, no_wait_gpu);
590 ret = ttm_tt_bind(bo->ttm, &tmp_mem);
594 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_reserve, no_wait_gpu, &tmp_mem);
598 ret = ttm_bo_move_ttm(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
600 if (tmp_mem.mm_node) {
601 spin_lock(&bo->bdev->glob->lru_lock);
602 drm_mm_put_block(tmp_mem.mm_node);
603 spin_unlock(&bo->bdev->glob->lru_lock);
610 nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
611 bool no_wait_reserve, bool no_wait_gpu,
612 struct ttm_mem_reg *new_mem)
614 u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
615 struct ttm_placement placement;
616 struct ttm_mem_reg tmp_mem;
619 placement.fpfn = placement.lpfn = 0;
620 placement.num_placement = placement.num_busy_placement = 1;
621 placement.placement = placement.busy_placement = &placement_memtype;
624 tmp_mem.mm_node = NULL;
625 ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_reserve, no_wait_gpu);
629 ret = ttm_bo_move_ttm(bo, evict, no_wait_reserve, no_wait_gpu, &tmp_mem);
633 ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
638 if (tmp_mem.mm_node) {
639 spin_lock(&bo->bdev->glob->lru_lock);
640 drm_mm_put_block(tmp_mem.mm_node);
641 spin_unlock(&bo->bdev->glob->lru_lock);
648 nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem,
649 struct nouveau_tile_reg **new_tile)
651 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
652 struct drm_device *dev = dev_priv->dev;
653 struct nouveau_bo *nvbo = nouveau_bo(bo);
657 if (nvbo->no_vm || new_mem->mem_type != TTM_PL_VRAM) {
663 offset = new_mem->mm_node->start << PAGE_SHIFT;
665 if (dev_priv->card_type == NV_50) {
666 ret = nv50_mem_vm_bind_linear(dev,
667 offset + dev_priv->vm_vram_base,
668 new_mem->size, nvbo->tile_flags,
673 } else if (dev_priv->card_type >= NV_10) {
674 *new_tile = nv10_mem_set_tiling(dev, offset, new_mem->size,
682 nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
683 struct nouveau_tile_reg *new_tile,
684 struct nouveau_tile_reg **old_tile)
686 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
687 struct drm_device *dev = dev_priv->dev;
689 if (dev_priv->card_type >= NV_10 &&
690 dev_priv->card_type < NV_50) {
692 nv10_mem_expire_tiling(dev, *old_tile, bo->sync_obj);
694 *old_tile = new_tile;
699 nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr,
700 bool no_wait_reserve, bool no_wait_gpu,
701 struct ttm_mem_reg *new_mem)
703 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
704 struct nouveau_bo *nvbo = nouveau_bo(bo);
705 struct ttm_mem_reg *old_mem = &bo->mem;
706 struct nouveau_tile_reg *new_tile = NULL;
709 ret = nouveau_bo_vm_bind(bo, new_mem, &new_tile);
713 /* Software copy if the card isn't up and running yet. */
714 if (dev_priv->init_state != NOUVEAU_CARD_INIT_DONE ||
715 !dev_priv->channel) {
716 ret = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
721 if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
722 BUG_ON(bo->mem.mm_node != NULL);
724 new_mem->mm_node = NULL;
728 /* Hardware assisted copy. */
729 if (new_mem->mem_type == TTM_PL_SYSTEM)
730 ret = nouveau_bo_move_flipd(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
731 else if (old_mem->mem_type == TTM_PL_SYSTEM)
732 ret = nouveau_bo_move_flips(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
734 ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
739 /* Fallback to software copy. */
740 ret = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
744 nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
746 nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
752 nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp)
758 nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
760 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
761 struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
762 struct drm_device *dev = dev_priv->dev;
764 mem->bus.addr = NULL;
766 mem->bus.size = mem->num_pages << PAGE_SHIFT;
768 mem->bus.is_iomem = false;
769 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
771 switch (mem->mem_type) {
777 if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) {
778 mem->bus.offset = mem->mm_node->start << PAGE_SHIFT;
779 mem->bus.base = dev_priv->gart_info.aper_base;
780 mem->bus.is_iomem = true;
785 mem->bus.offset = mem->mm_node->start << PAGE_SHIFT;
786 mem->bus.base = drm_get_resource_start(dev, 1);
787 mem->bus.is_iomem = true;
796 nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
801 nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
806 struct ttm_bo_driver nouveau_bo_driver = {
807 .create_ttm_backend_entry = nouveau_bo_create_ttm_backend_entry,
808 .invalidate_caches = nouveau_bo_invalidate_caches,
809 .init_mem_type = nouveau_bo_init_mem_type,
810 .evict_flags = nouveau_bo_evict_flags,
811 .move = nouveau_bo_move,
812 .verify_access = nouveau_bo_verify_access,
813 .sync_obj_signaled = nouveau_fence_signalled,
814 .sync_obj_wait = nouveau_fence_wait,
815 .sync_obj_flush = nouveau_fence_flush,
816 .sync_obj_unref = nouveau_fence_unref,
817 .sync_obj_ref = nouveau_fence_ref,
818 .fault_reserve_notify = &nouveau_ttm_fault_reserve_notify,
819 .io_mem_reserve = &nouveau_ttm_io_mem_reserve,
820 .io_mem_free = &nouveau_ttm_io_mem_free,