drivers/gpu/drm/nouveau/nouveau_bo.c

   1 /*
   2  * Copyright 2007 Dave Airlied
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24 /*
  25  * Authors: Dave Airlied <airlied@linux.ie>
  26  *          Ben Skeggs   <darktama@iinet.net.au>
  27  *          Jeremy Kolb  <jkolb@brandeis.edu>
  28  */
  29
  30 #include "drmP.h"
  31
  32 #include "nouveau_drm.h"
  33 #include "nouveau_drv.h"
  34 #include "nouveau_dma.h"
  35
  36 #include <linux/log2.h>
  37 #include <linux/slab.h>
  38
  39 static void
  40 nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
  41 {
  42         struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
  43         struct drm_device *dev = dev_priv->dev;
  44         struct nouveau_bo *nvbo = nouveau_bo(bo);
  45
  46         if (unlikely(nvbo->gem))
  47                 DRM_ERROR("bo %p still attached to GEM object\n", bo);
  48
  49         nv10_mem_put_tile_region(dev, nvbo->tile, NULL);
  50         kfree(nvbo);
  51 }
  52
  53 static void
  54 nouveau_bo_fixup_align(struct drm_device *dev,
  55                        uint32_t tile_mode, uint32_t tile_flags,
  56                        int *align, int *size)
  57 {
  58         struct drm_nouveau_private *dev_priv = dev->dev_private;
  59
  60         /*
  61          * Some of the tile_flags have a periodic structure of N*4096 bytes,
  62          * align to to that as well as the page size. Align the size to the
  63          * appropriate boundaries. This does imply that sizes are rounded up
  64          * 3-7 pages, so be aware of this and do not waste memory by allocating
  65          * many small buffers.
  66          */
  67         if (dev_priv->card_type == NV_50) {
  68                 uint32_t block_size = dev_priv->vram_size >> 15;
  69                 int i;
  70
  71                 switch (tile_flags) {
  72                 case 0x1800:
  73                 case 0x2800:
  74                 case 0x4800:
  75                 case 0x7a00:
  76                         if (is_power_of_2(block_size)) {
  77                                 for (i = 1; i < 10; i++) {
  78                                         *align = 12 * i * block_size;
  79                                         if (!(*align % 65536))
  80                                                 break;
  81                                 }
  82                         } else {
  83                                 for (i = 1; i < 10; i++) {
  84                                         *align = 8 * i * block_size;
  85                                         if (!(*align % 65536))
  86                                                 break;
  87                                 }
  88                         }
  89                         *size = roundup(*size, *align);
  90                         break;
  91                 default:
  92                         break;
  93                 }
  94
  95         } else {
  96                 if (tile_mode) {
  97                         if (dev_priv->chipset >= 0x40) {
  98                                 *align = 65536;
  99                                 *size = roundup(*size, 64 * tile_mode);
 100
 101                         } else if (dev_priv->chipset >= 0x30) {
 102                                 *align = 32768;
 103                                 *size = roundup(*size, 64 * tile_mode);
 104
 105                         } else if (dev_priv->chipset >= 0x20) {
 106                                 *align = 16384;
 107                                 *size = roundup(*size, 64 * tile_mode);
 108
 109                         } else if (dev_priv->chipset >= 0x10) {
 110                                 *align = 16384;
 111                                 *size = roundup(*size, 32 * tile_mode);
 112                         }
 113                 }
 114         }
 115
 116         /* ALIGN works only on powers of two. */
 117         *size = roundup(*size, PAGE_SIZE);
 118
 119         if (dev_priv->card_type == NV_50) {
 120                 *size = roundup(*size, 65536);
 121                 *align = max(65536, *align);
 122         }
 123 }
 124
 125 int
 126 nouveau_bo_new(struct drm_device *dev, struct nouveau_channel *chan,
 127                int size, int align, uint32_t flags, uint32_t tile_mode,
 128                uint32_t tile_flags, bool no_vm, bool mappable,
 129                struct nouveau_bo **pnvbo)
 130 {
 131         struct drm_nouveau_private *dev_priv = dev->dev_private;
 132         struct nouveau_bo *nvbo;
 133         int ret = 0;
 134
 135         nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
 136         if (!nvbo)
 137                 return -ENOMEM;
 138         INIT_LIST_HEAD(&nvbo->head);
 139         INIT_LIST_HEAD(&nvbo->entry);
 140         nvbo->mappable = mappable;
 141         nvbo->no_vm = no_vm;
 142         nvbo->tile_mode = tile_mode;
 143         nvbo->tile_flags = tile_flags;
 144         nvbo->bo.bdev = &dev_priv->ttm.bdev;
 145
 146         nouveau_bo_fixup_align(dev, tile_mode, nouveau_bo_tile_layout(nvbo),
 147                                &align, &size);
 148         align >>= PAGE_SHIFT;
 149
 150         nouveau_bo_placement_set(nvbo, flags, 0);
 151
 152         nvbo->channel = chan;
 153         ret = ttm_bo_init(&dev_priv->ttm.bdev, &nvbo->bo, size,
 154                           ttm_bo_type_device, &nvbo->placement, align, 0,
 155                           false, NULL, size, nouveau_bo_del_ttm);
 156         if (ret) {
 157                 /* ttm will call nouveau_bo_del_ttm if it fails.. */
 158                 return ret;
 159         }
 160         nvbo->channel = NULL;
 161
 162         *pnvbo = nvbo;
 163         return 0;
 164 }
 165
 166 static void
 167 set_placement_list(uint32_t *pl, unsigned *n, uint32_t type, uint32_t flags)
 168 {
 169         *n = 0;
 170
 171         if (type & TTM_PL_FLAG_VRAM)
 172                 pl[(*n)++] = TTM_PL_FLAG_VRAM | flags;
 173         if (type & TTM_PL_FLAG_TT)
 174                 pl[(*n)++] = TTM_PL_FLAG_TT | flags;
 175         if (type & TTM_PL_FLAG_SYSTEM)
 176                 pl[(*n)++] = TTM_PL_FLAG_SYSTEM | flags;
 177 }
 178
 179 static void
 180 set_placement_range(struct nouveau_bo *nvbo, uint32_t type)
 181 {
 182         struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
 183
 184         if (dev_priv->card_type == NV_10 &&
 185             nvbo->tile_mode && (type & TTM_PL_FLAG_VRAM)) {
 186                 /*
 187                  * Make sure that the color and depth buffers are handled
 188                  * by independent memory controller units. Up to a 9x
 189                  * speed up when alpha-blending and depth-test are enabled
 190                  * at the same time.
 191                  */
 192                 int vram_pages = dev_priv->vram_size >> PAGE_SHIFT;
 193
 194                 if (nvbo->tile_flags & NOUVEAU_GEM_TILE_ZETA) {
 195                         nvbo->placement.fpfn = vram_pages / 2;
 196                         nvbo->placement.lpfn = ~0;
 197                 } else {
 198                         nvbo->placement.fpfn = 0;
 199                         nvbo->placement.lpfn = vram_pages / 2;
 200                 }
 201         }
 202 }
 203
 204 void
 205 nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy)
 206 {
 207         struct ttm_placement *pl = &nvbo->placement;
 208         uint32_t flags = TTM_PL_MASK_CACHING |
 209                 (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0);
 210
 211         pl->placement = nvbo->placements;
 212         set_placement_list(nvbo->placements, &pl->num_placement,
 213                            type, flags);
 214
 215         pl->busy_placement = nvbo->busy_placements;
 216         set_placement_list(nvbo->busy_placements, &pl->num_busy_placement,
 217                            type | busy, flags);
 218
 219         set_placement_range(nvbo, type);
 220 }
 221
 222 int
 223 nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype)
 224 {
 225         struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
 226         struct ttm_buffer_object *bo = &nvbo->bo;
 227         int ret;
 228
 229         if (nvbo->pin_refcnt && !(memtype & (1 << bo->mem.mem_type))) {
 230                 NV_ERROR(nouveau_bdev(bo->bdev)->dev,
 231                          "bo %p pinned elsewhere: 0x%08x vs 0x%08x\n", bo,
 232                          1 << bo->mem.mem_type, memtype);
 233                 return -EINVAL;
 234         }
 235
 236         if (nvbo->pin_refcnt++)
 237                 return 0;
 238
 239         ret = ttm_bo_reserve(bo, false, false, false, 0);
 240         if (ret)
 241                 goto out;
 242
 243         nouveau_bo_placement_set(nvbo, memtype, 0);
 244
 245         ret = ttm_bo_validate(bo, &nvbo->placement, false, false, false);
 246         if (ret == 0) {
 247                 switch (bo->mem.mem_type) {
 248                 case TTM_PL_VRAM:
 249                         dev_priv->fb_aper_free -= bo->mem.size;
 250                         break;
 251                 case TTM_PL_TT:
 252                         dev_priv->gart_info.aper_free -= bo->mem.size;
 253                         break;
 254                 default:
 255                         break;
 256                 }
 257         }
 258         ttm_bo_unreserve(bo);
 259 out:
 260         if (unlikely(ret))
 261                 nvbo->pin_refcnt--;
 262         return ret;
 263 }
 264
 265 int
 266 nouveau_bo_unpin(struct nouveau_bo *nvbo)
 267 {
 268         struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
 269         struct ttm_buffer_object *bo = &nvbo->bo;
 270         int ret;
 271
 272         if (--nvbo->pin_refcnt)
 273                 return 0;
 274
 275         ret = ttm_bo_reserve(bo, false, false, false, 0);
 276         if (ret)
 277                 return ret;
 278
 279         nouveau_bo_placement_set(nvbo, bo->mem.placement, 0);
 280
 281         ret = ttm_bo_validate(bo, &nvbo->placement, false, false, false);
 282         if (ret == 0) {
 283                 switch (bo->mem.mem_type) {
 284                 case TTM_PL_VRAM:
 285                         dev_priv->fb_aper_free += bo->mem.size;
 286                         break;
 287                 case TTM_PL_TT:
 288                         dev_priv->gart_info.aper_free += bo->mem.size;
 289                         break;
 290                 default:
 291                         break;
 292                 }
 293         }
 294
 295         ttm_bo_unreserve(bo);
 296         return ret;
 297 }
 298
 299 int
 300 nouveau_bo_map(struct nouveau_bo *nvbo)
 301 {
 302         int ret;
 303
 304         ret = ttm_bo_reserve(&nvbo->bo, false, false, false, 0);
 305         if (ret)
 306                 return ret;
 307
 308         ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap);
 309         ttm_bo_unreserve(&nvbo->bo);
 310         return ret;
 311 }
 312
 313 void
 314 nouveau_bo_unmap(struct nouveau_bo *nvbo)
 315 {
 316         if (nvbo)
 317                 ttm_bo_kunmap(&nvbo->kmap);
 318 }
 319
 320 u16
 321 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index)
 322 {
 323         bool is_iomem;
 324         u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
 325         mem = &mem[index];
 326         if (is_iomem)
 327                 return ioread16_native((void __force __iomem *)mem);
 328         else
 329                 return *mem;
 330 }
 331
 332 void
 333 nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
 334 {
 335         bool is_iomem;
 336         u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
 337         mem = &mem[index];
 338         if (is_iomem)
 339                 iowrite16_native(val, (void __force __iomem *)mem);
 340         else
 341                 *mem = val;
 342 }
 343
 344 u32
 345 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
 346 {
 347         bool is_iomem;
 348         u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
 349         mem = &mem[index];
 350         if (is_iomem)
 351                 return ioread32_native((void __force __iomem *)mem);
 352         else
 353                 return *mem;
 354 }
 355
 356 void
 357 nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
 358 {
 359         bool is_iomem;
 360         u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
 361         mem = &mem[index];
 362         if (is_iomem)
 363                 iowrite32_native(val, (void __force __iomem *)mem);
 364         else
 365                 *mem = val;
 366 }
 367
 368 static struct ttm_backend *
 369 nouveau_bo_create_ttm_backend_entry(struct ttm_bo_device *bdev)
 370 {
 371         struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
 372         struct drm_device *dev = dev_priv->dev;
 373
 374         switch (dev_priv->gart_info.type) {
 375 #if __OS_HAS_AGP
 376         case NOUVEAU_GART_AGP:
 377                 return ttm_agp_backend_init(bdev, dev->agp->bridge);
 378 #endif
 379         case NOUVEAU_GART_SGDMA:
 380                 return nouveau_sgdma_init_ttm(dev);
 381         default:
 382                 NV_ERROR(dev, "Unknown GART type %d\n",
 383                          dev_priv->gart_info.type);
 384                 break;
 385         }
 386
 387         return NULL;
 388 }
 389
 390 static int
 391 nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
 392 {
 393         /* We'll do this from user space. */
 394         return 0;
 395 }
 396
 397 static int
 398 nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
 399                          struct ttm_mem_type_manager *man)
 400 {
 401         struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
 402         struct drm_device *dev = dev_priv->dev;
 403
 404         switch (type) {
 405         case TTM_PL_SYSTEM:
 406                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
 407                 man->available_caching = TTM_PL_MASK_CACHING;
 408                 man->default_caching = TTM_PL_FLAG_CACHED;
 409                 break;
 410         case TTM_PL_VRAM:
 411                 man->func = &ttm_bo_manager_func;
 412                 man->flags = TTM_MEMTYPE_FLAG_FIXED |
 413                              TTM_MEMTYPE_FLAG_MAPPABLE;
 414                 man->available_caching = TTM_PL_FLAG_UNCACHED |
 415                                          TTM_PL_FLAG_WC;
 416                 man->default_caching = TTM_PL_FLAG_WC;
 417                 if (dev_priv->card_type == NV_50)
 418                         man->gpu_offset = 0x40000000;
 419                 else
 420                         man->gpu_offset = 0;
 421                 break;
 422         case TTM_PL_TT:
 423                 man->func = &ttm_bo_manager_func;
 424                 switch (dev_priv->gart_info.type) {
 425                 case NOUVEAU_GART_AGP:
 426                         man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
 427                         man->available_caching = TTM_PL_FLAG_UNCACHED |
 428                                 TTM_PL_FLAG_WC;
 429                         man->default_caching = TTM_PL_FLAG_WC;
 430                         break;
 431                 case NOUVEAU_GART_SGDMA:
 432                         man->flags = TTM_MEMTYPE_FLAG_MAPPABLE |
 433                                      TTM_MEMTYPE_FLAG_CMA;
 434                         man->available_caching = TTM_PL_MASK_CACHING;
 435                         man->default_caching = TTM_PL_FLAG_CACHED;
 436                         break;
 437                 default:
 438                         NV_ERROR(dev, "Unknown GART type: %d\n",
 439                                  dev_priv->gart_info.type);
 440                         return -EINVAL;
 441                 }
 442                 man->gpu_offset = dev_priv->vm_gart_base;
 443                 break;
 444         default:
 445                 NV_ERROR(dev, "Unsupported memory type %u\n", (unsigned)type);
 446                 return -EINVAL;
 447         }
 448         return 0;
 449 }
 450
 451 static void
 452 nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
 453 {
 454         struct nouveau_bo *nvbo = nouveau_bo(bo);
 455
 456         switch (bo->mem.mem_type) {
 457         case TTM_PL_VRAM:
 458                 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT,
 459                                          TTM_PL_FLAG_SYSTEM);
 460                 break;
 461         default:
 462                 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0);
 463                 break;
 464         }
 465
 466         *pl = nvbo->placement;
 467 }
 468
 469
 470 /* GPU-assisted copy using NV_MEMORY_TO_MEMORY_FORMAT, can access
 471  * TTM_PL_{VRAM,TT} directly.
 472  */
 473
 474 static int
 475 nouveau_bo_move_accel_cleanup(struct nouveau_channel *chan,
 476                               struct nouveau_bo *nvbo, bool evict,
 477                               bool no_wait_reserve, bool no_wait_gpu,
 478                               struct ttm_mem_reg *new_mem)
 479 {
 480         struct nouveau_fence *fence = NULL;
 481         int ret;
 482
 483         ret = nouveau_fence_new(chan, &fence, true);
 484         if (ret)
 485                 return ret;
 486
 487         ret = ttm_bo_move_accel_cleanup(&nvbo->bo, fence, NULL, evict,
 488                                         no_wait_reserve, no_wait_gpu, new_mem);
 489         nouveau_fence_unref(&fence);
 490         return ret;
 491 }
 492
 493 static inline uint32_t
 494 nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo,
 495                       struct nouveau_channel *chan, struct ttm_mem_reg *mem)
 496 {
 497         struct nouveau_bo *nvbo = nouveau_bo(bo);
 498
 499         if (nvbo->no_vm) {
 500                 if (mem->mem_type == TTM_PL_TT)
 501                         return NvDmaGART;
 502                 return NvDmaVRAM;
 503         }
 504
 505         if (mem->mem_type == TTM_PL_TT)
 506                 return chan->gart_handle;
 507         return chan->vram_handle;
 508 }
 509
 510 static int
 511 nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
 512                   struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
 513 {
 514         struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
 515         struct nouveau_bo *nvbo = nouveau_bo(bo);
 516         u64 length = (new_mem->num_pages << PAGE_SHIFT);
 517         u64 src_offset, dst_offset;
 518         int ret;
 519
 520         src_offset = old_mem->start << PAGE_SHIFT;
 521         dst_offset = new_mem->start << PAGE_SHIFT;
 522         if (!nvbo->no_vm) {
 523                 if (old_mem->mem_type == TTM_PL_VRAM)
 524                         src_offset += dev_priv->vm_vram_base;
 525                 else
 526                         src_offset += dev_priv->vm_gart_base;
 527
 528                 if (new_mem->mem_type == TTM_PL_VRAM)
 529                         dst_offset += dev_priv->vm_vram_base;
 530                 else
 531                         dst_offset += dev_priv->vm_gart_base;
 532         }
 533
 534         ret = RING_SPACE(chan, 3);
 535         if (ret)
 536                 return ret;
 537
 538         BEGIN_RING(chan, NvSubM2MF, 0x0184, 2);
 539         OUT_RING  (chan, nouveau_bo_mem_ctxdma(bo, chan, old_mem));
 540         OUT_RING  (chan, nouveau_bo_mem_ctxdma(bo, chan, new_mem));
 541
 542         while (length) {
 543                 u32 amount, stride, height;
 544
 545                 amount  = min(length, (u64)(4 * 1024 * 1024));
 546                 stride  = 16 * 4;
 547                 height  = amount / stride;
 548
 549                 if (new_mem->mem_type == TTM_PL_VRAM &&
 550                     nouveau_bo_tile_layout(nvbo)) {
 551                         ret = RING_SPACE(chan, 8);
 552                         if (ret)
 553                                 return ret;
 554
 555                         BEGIN_RING(chan, NvSubM2MF, 0x0200, 7);
 556                         OUT_RING  (chan, 0);
 557                         OUT_RING  (chan, 0);
 558                         OUT_RING  (chan, stride);
 559                         OUT_RING  (chan, height);
 560                         OUT_RING  (chan, 1);
 561                         OUT_RING  (chan, 0);
 562                         OUT_RING  (chan, 0);
 563                 } else {
 564                         ret = RING_SPACE(chan, 2);
 565                         if (ret)
 566                                 return ret;
 567
 568                         BEGIN_RING(chan, NvSubM2MF, 0x0200, 1);
 569                         OUT_RING  (chan, 1);
 570                 }
 571                 if (old_mem->mem_type == TTM_PL_VRAM &&
 572                     nouveau_bo_tile_layout(nvbo)) {
 573                         ret = RING_SPACE(chan, 8);
 574                         if (ret)
 575                                 return ret;
 576
 577                         BEGIN_RING(chan, NvSubM2MF, 0x021c, 7);
 578                         OUT_RING  (chan, 0);
 579                         OUT_RING  (chan, 0);
 580                         OUT_RING  (chan, stride);
 581                         OUT_RING  (chan, height);
 582                         OUT_RING  (chan, 1);
 583                         OUT_RING  (chan, 0);
 584                         OUT_RING  (chan, 0);
 585                 } else {
 586                         ret = RING_SPACE(chan, 2);
 587                         if (ret)
 588                                 return ret;
 589
 590                         BEGIN_RING(chan, NvSubM2MF, 0x021c, 1);
 591                         OUT_RING  (chan, 1);
 592                 }
 593
 594                 ret = RING_SPACE(chan, 14);
 595                 if (ret)
 596                         return ret;
 597
 598                 BEGIN_RING(chan, NvSubM2MF, 0x0238, 2);
 599                 OUT_RING  (chan, upper_32_bits(src_offset));
 600                 OUT_RING  (chan, upper_32_bits(dst_offset));
 601                 BEGIN_RING(chan, NvSubM2MF, 0x030c, 8);
 602                 OUT_RING  (chan, lower_32_bits(src_offset));
 603                 OUT_RING  (chan, lower_32_bits(dst_offset));
 604                 OUT_RING  (chan, stride);
 605                 OUT_RING  (chan, stride);
 606                 OUT_RING  (chan, stride);
 607                 OUT_RING  (chan, height);
 608                 OUT_RING  (chan, 0x00000101);
 609                 OUT_RING  (chan, 0x00000000);
 610                 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
 611                 OUT_RING  (chan, 0);
 612
 613                 length -= amount;
 614                 src_offset += amount;
 615                 dst_offset += amount;
 616         }
 617
 618         return 0;
 619 }
 620
 621 static int
 622 nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
 623                   struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
 624 {
 625         u32 src_offset = old_mem->start << PAGE_SHIFT;
 626         u32 dst_offset = new_mem->start << PAGE_SHIFT;
 627         u32 page_count = new_mem->num_pages;
 628         int ret;
 629
 630         ret = RING_SPACE(chan, 3);
 631         if (ret)
 632                 return ret;
 633
 634         BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2);
 635         OUT_RING  (chan, nouveau_bo_mem_ctxdma(bo, chan, old_mem));
 636         OUT_RING  (chan, nouveau_bo_mem_ctxdma(bo, chan, new_mem));
 637
 638         page_count = new_mem->num_pages;
 639         while (page_count) {
 640                 int line_count = (page_count > 2047) ? 2047 : page_count;
 641
 642                 ret = RING_SPACE(chan, 11);
 643                 if (ret)
 644                         return ret;
 645
 646                 BEGIN_RING(chan, NvSubM2MF,
 647                                  NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
 648                 OUT_RING  (chan, src_offset);
 649                 OUT_RING  (chan, dst_offset);
 650                 OUT_RING  (chan, PAGE_SIZE); /* src_pitch */
 651                 OUT_RING  (chan, PAGE_SIZE); /* dst_pitch */
 652                 OUT_RING  (chan, PAGE_SIZE); /* line_length */
 653                 OUT_RING  (chan, line_count);
 654                 OUT_RING  (chan, 0x00000101);
 655                 OUT_RING  (chan, 0x00000000);
 656                 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
 657                 OUT_RING  (chan, 0);
 658
 659                 page_count -= line_count;
 660                 src_offset += (PAGE_SIZE * line_count);
 661                 dst_offset += (PAGE_SIZE * line_count);
 662         }
 663
 664         return 0;
 665 }
 666
 667 static int
 668 nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr,
 669                      bool no_wait_reserve, bool no_wait_gpu,
 670                      struct ttm_mem_reg *new_mem)
 671 {
 672         struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
 673         struct nouveau_bo *nvbo = nouveau_bo(bo);
 674         struct nouveau_channel *chan;
 675         int ret;
 676
 677         chan = nvbo->channel;
 678         if (!chan || nvbo->no_vm) {
 679                 chan = dev_priv->channel;
 680                 mutex_lock_nested(&chan->mutex, NOUVEAU_KCHANNEL_MUTEX);
 681         }
 682
 683         if (dev_priv->card_type < NV_50)
 684                 ret = nv04_bo_move_m2mf(chan, bo, &bo->mem, new_mem);
 685         else
 686                 ret = nv50_bo_move_m2mf(chan, bo, &bo->mem, new_mem);
 687         if (ret == 0) {
 688                 ret = nouveau_bo_move_accel_cleanup(chan, nvbo, evict,
 689                                                     no_wait_reserve,
 690                                                     no_wait_gpu, new_mem);
 691         }
 692
 693         if (chan == dev_priv->channel)
 694                 mutex_unlock(&chan->mutex);
 695         return ret;
 696 }
 697
 698 static int
 699 nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
 700                       bool no_wait_reserve, bool no_wait_gpu,
 701                       struct ttm_mem_reg *new_mem)
 702 {
 703         u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
 704         struct ttm_placement placement;
 705         struct ttm_mem_reg tmp_mem;
 706         int ret;
 707
 708         placement.fpfn = placement.lpfn = 0;
 709         placement.num_placement = placement.num_busy_placement = 1;
 710         placement.placement = placement.busy_placement = &placement_memtype;
 711
 712         tmp_mem = *new_mem;
 713         tmp_mem.mm_node = NULL;
 714         ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_reserve, no_wait_gpu);
 715         if (ret)
 716                 return ret;
 717
 718         ret = ttm_tt_bind(bo->ttm, &tmp_mem);
 719         if (ret)
 720                 goto out;
 721
 722         ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_reserve, no_wait_gpu, &tmp_mem);
 723         if (ret)
 724                 goto out;
 725
 726         ret = ttm_bo_move_ttm(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
 727 out:
 728         ttm_bo_mem_put(bo, &tmp_mem);
 729         return ret;
 730 }
 731
 732 static int
 733 nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
 734                       bool no_wait_reserve, bool no_wait_gpu,
 735                       struct ttm_mem_reg *new_mem)
 736 {
 737         u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
 738         struct ttm_placement placement;
 739         struct ttm_mem_reg tmp_mem;
 740         int ret;
 741
 742         placement.fpfn = placement.lpfn = 0;
 743         placement.num_placement = placement.num_busy_placement = 1;
 744         placement.placement = placement.busy_placement = &placement_memtype;
 745
 746         tmp_mem = *new_mem;
 747         tmp_mem.mm_node = NULL;
 748         ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_reserve, no_wait_gpu);
 749         if (ret)
 750                 return ret;
 751
 752         ret = ttm_bo_move_ttm(bo, evict, no_wait_reserve, no_wait_gpu, &tmp_mem);
 753         if (ret)
 754                 goto out;
 755
 756         ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
 757         if (ret)
 758                 goto out;
 759
 760 out:
 761         ttm_bo_mem_put(bo, &tmp_mem);
 762         return ret;
 763 }
 764
 765 static int
 766 nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem,
 767                    struct nouveau_tile_reg **new_tile)
 768 {
 769         struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
 770         struct drm_device *dev = dev_priv->dev;
 771         struct nouveau_bo *nvbo = nouveau_bo(bo);
 772         uint64_t offset;
 773         int ret;
 774
 775         if (nvbo->no_vm || new_mem->mem_type != TTM_PL_VRAM) {
 776                 /* Nothing to do. */
 777                 *new_tile = NULL;
 778                 return 0;
 779         }
 780
 781         offset = new_mem->start << PAGE_SHIFT;
 782
 783         if (dev_priv->card_type == NV_50) {
 784                 ret = nv50_mem_vm_bind_linear(dev,
 785                                               offset + dev_priv->vm_vram_base,
 786                                               new_mem->size,
 787                                               nouveau_bo_tile_layout(nvbo),
 788                                               offset);
 789                 if (ret)
 790                         return ret;
 791
 792         } else if (dev_priv->card_type >= NV_10) {
 793                 *new_tile = nv10_mem_set_tiling(dev, offset, new_mem->size,
 794                                                 nvbo->tile_mode,
 795                                                 nvbo->tile_flags);
 796         }
 797
 798         return 0;
 799 }
 800
 801 static void
 802 nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
 803                       struct nouveau_tile_reg *new_tile,
 804                       struct nouveau_tile_reg **old_tile)
 805 {
 806         struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
 807         struct drm_device *dev = dev_priv->dev;
 808
 809         if (dev_priv->card_type >= NV_10 &&
 810             dev_priv->card_type < NV_50) {
 811                 nv10_mem_put_tile_region(dev, *old_tile, bo->sync_obj);
 812                 *old_tile = new_tile;
 813         }
 814 }
 815
 816 static int
 817 nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr,
 818                 bool no_wait_reserve, bool no_wait_gpu,
 819                 struct ttm_mem_reg *new_mem)
 820 {
 821         struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
 822         struct nouveau_bo *nvbo = nouveau_bo(bo);
 823         struct ttm_mem_reg *old_mem = &bo->mem;
 824         struct nouveau_tile_reg *new_tile = NULL;
 825         int ret = 0;
 826
 827         ret = nouveau_bo_vm_bind(bo, new_mem, &new_tile);
 828         if (ret)
 829                 return ret;
 830
 831         /* Fake bo copy. */
 832         if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
 833                 BUG_ON(bo->mem.mm_node != NULL);
 834                 bo->mem = *new_mem;
 835                 new_mem->mm_node = NULL;
 836                 goto out;
 837         }
 838
 839         /* Software copy if the card isn't up and running yet. */
 840         if (!dev_priv->channel) {
 841                 ret = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
 842                 goto out;
 843         }
 844
 845         /* Hardware assisted copy. */
 846         if (new_mem->mem_type == TTM_PL_SYSTEM)
 847                 ret = nouveau_bo_move_flipd(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
 848         else if (old_mem->mem_type == TTM_PL_SYSTEM)
 849                 ret = nouveau_bo_move_flips(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
 850         else
 851                 ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
 852
 853         if (!ret)
 854                 goto out;
 855
 856         /* Fallback to software copy. */
 857         ret = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
 858
 859 out:
 860         if (ret)
 861                 nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
 862         else
 863                 nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
 864
 865         return ret;
 866 }
 867
 868 static int
 869 nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 870 {
 871         return 0;
 872 }
 873
 874 static int
 875 nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 876 {
 877         struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
 878         struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
 879         struct drm_device *dev = dev_priv->dev;
 880
 881         mem->bus.addr = NULL;
 882         mem->bus.offset = 0;
 883         mem->bus.size = mem->num_pages << PAGE_SHIFT;
 884         mem->bus.base = 0;
 885         mem->bus.is_iomem = false;
 886         if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
 887                 return -EINVAL;
 888         switch (mem->mem_type) {
 889         case TTM_PL_SYSTEM:
 890                 /* System memory */
 891                 return 0;
 892         case TTM_PL_TT:
 893 #if __OS_HAS_AGP
 894                 if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) {
 895                         mem->bus.offset = mem->start << PAGE_SHIFT;
 896                         mem->bus.base = dev_priv->gart_info.aper_base;
 897                         mem->bus.is_iomem = true;
 898                 }
 899 #endif
 900                 break;
 901         case TTM_PL_VRAM:
 902                 mem->bus.offset = mem->start << PAGE_SHIFT;
 903                 mem->bus.base = pci_resource_start(dev->pdev, 1);
 904                 mem->bus.is_iomem = true;
 905                 break;
 906         default:
 907                 return -EINVAL;
 908         }
 909         return 0;
 910 }
 911
 912 static void
 913 nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 914 {
 915 }
 916
 917 static int
 918 nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
 919 {
 920         struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
 921         struct nouveau_bo *nvbo = nouveau_bo(bo);
 922
 923         /* as long as the bo isn't in vram, and isn't tiled, we've got
 924          * nothing to do here.
 925          */
 926         if (bo->mem.mem_type != TTM_PL_VRAM) {
 927                 if (dev_priv->card_type < NV_50 ||
 928                     !nouveau_bo_tile_layout(nvbo))
 929                         return 0;
 930         }
 931
 932         /* make sure bo is in mappable vram */
 933         if (bo->mem.start + bo->mem.num_pages < dev_priv->fb_mappable_pages)
 934                 return 0;
 935
 936
 937         nvbo->placement.fpfn = 0;
 938         nvbo->placement.lpfn = dev_priv->fb_mappable_pages;
 939         nouveau_bo_placement_set(nvbo, TTM_PL_VRAM, 0);
 940         return ttm_bo_validate(bo, &nvbo->placement, false, true, false);
 941 }
 942
 943 void
 944 nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence)
 945 {
 946         struct nouveau_fence *old_fence;
 947
 948         if (likely(fence))
 949                 nouveau_fence_ref(fence);
 950
 951         spin_lock(&nvbo->bo.bdev->fence_lock);
 952         old_fence = nvbo->bo.sync_obj;
 953         nvbo->bo.sync_obj = fence;
 954         spin_unlock(&nvbo->bo.bdev->fence_lock);
 955
 956         nouveau_fence_unref(&old_fence);
 957 }
 958
 959 struct ttm_bo_driver nouveau_bo_driver = {
 960         .create_ttm_backend_entry = nouveau_bo_create_ttm_backend_entry,
 961         .invalidate_caches = nouveau_bo_invalidate_caches,
 962         .init_mem_type = nouveau_bo_init_mem_type,
 963         .evict_flags = nouveau_bo_evict_flags,
 964         .move = nouveau_bo_move,
 965         .verify_access = nouveau_bo_verify_access,
 966         .sync_obj_signaled = __nouveau_fence_signalled,
 967         .sync_obj_wait = __nouveau_fence_wait,
 968         .sync_obj_flush = __nouveau_fence_flush,
 969         .sync_obj_unref = __nouveau_fence_unref,
 970         .sync_obj_ref = __nouveau_fence_ref,
 971         .fault_reserve_notify = &nouveau_ttm_fault_reserve_notify,
 972         .io_mem_reserve = &nouveau_ttm_io_mem_reserve,
 973         .io_mem_free = &nouveau_ttm_io_mem_free,
 974 };
 975