drivers/gpu/drm/nouveau/nouveau_bo.c

   1 /*
   2  * Copyright 2007 Dave Airlied
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24 /*
  25  * Authors: Dave Airlied <airlied@linux.ie>
  26  *          Ben Skeggs   <darktama@iinet.net.au>
  27  *          Jeremy Kolb  <jkolb@brandeis.edu>
  28  */
  29
  30 #include "drmP.h"
  31
  32 #include "nouveau_drm.h"
  33 #include "nouveau_drv.h"
  34 #include "nouveau_dma.h"
  35 #include "nouveau_mm.h"
  36 #include "nouveau_vm.h"
  37
  38 #include <linux/log2.h>
  39 #include <linux/slab.h>
  40
  41 static void
  42 nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
  43 {
  44         struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
  45         struct drm_device *dev = dev_priv->dev;
  46         struct nouveau_bo *nvbo = nouveau_bo(bo);
  47
  48         if (unlikely(nvbo->gem))
  49                 DRM_ERROR("bo %p still attached to GEM object\n", bo);
  50
  51         nv10_mem_put_tile_region(dev, nvbo->tile, NULL);
  52         nouveau_vm_put(&nvbo->vma);
  53         kfree(nvbo);
  54 }
  55
  56 static void
  57 nouveau_bo_fixup_align(struct nouveau_bo *nvbo, int *align, int *size,
  58                        int *page_shift)
  59 {
  60         struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
  61
  62         if (dev_priv->card_type < NV_50) {
  63                 if (nvbo->tile_mode) {
  64                         if (dev_priv->chipset >= 0x40) {
  65                                 *align = 65536;
  66                                 *size = roundup(*size, 64 * nvbo->tile_mode);
  67
  68                         } else if (dev_priv->chipset >= 0x30) {
  69                                 *align = 32768;
  70                                 *size = roundup(*size, 64 * nvbo->tile_mode);
  71
  72                         } else if (dev_priv->chipset >= 0x20) {
  73                                 *align = 16384;
  74                                 *size = roundup(*size, 64 * nvbo->tile_mode);
  75
  76                         } else if (dev_priv->chipset >= 0x10) {
  77                                 *align = 16384;
  78                                 *size = roundup(*size, 32 * nvbo->tile_mode);
  79                         }
  80                 }
  81         } else {
  82                 if (likely(dev_priv->chan_vm)) {
  83                         if (*size > 256 * 1024)
  84                                 *page_shift = dev_priv->chan_vm->lpg_shift;
  85                         else
  86                                 *page_shift = dev_priv->chan_vm->spg_shift;
  87                 } else {
  88                         *page_shift = 12;
  89                 }
  90
  91                 *size = roundup(*size, (1 << *page_shift));
  92                 *align = max((1 << *page_shift), *align);
  93         }
  94
  95         *size = roundup(*size, PAGE_SIZE);
  96 }
  97
  98 int
  99 nouveau_bo_new(struct drm_device *dev, struct nouveau_channel *chan,
 100                int size, int align, uint32_t flags, uint32_t tile_mode,
 101                uint32_t tile_flags, bool no_vm, bool mappable,
 102                struct nouveau_bo **pnvbo)
 103 {
 104         struct drm_nouveau_private *dev_priv = dev->dev_private;
 105         struct nouveau_bo *nvbo;
 106         int ret = 0, page_shift = 0;
 107
 108         nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
 109         if (!nvbo)
 110                 return -ENOMEM;
 111         INIT_LIST_HEAD(&nvbo->head);
 112         INIT_LIST_HEAD(&nvbo->entry);
 113         nvbo->mappable = mappable;
 114         nvbo->no_vm = no_vm;
 115         nvbo->tile_mode = tile_mode;
 116         nvbo->tile_flags = tile_flags;
 117         nvbo->bo.bdev = &dev_priv->ttm.bdev;
 118
 119         nouveau_bo_fixup_align(nvbo, &align, &size, &page_shift);
 120         align >>= PAGE_SHIFT;
 121
 122         if (!nvbo->no_vm && dev_priv->chan_vm) {
 123                 ret = nouveau_vm_get(dev_priv->chan_vm, size, page_shift,
 124                                      NV_MEM_ACCESS_RW, &nvbo->vma);
 125                 if (ret) {
 126                         kfree(nvbo);
 127                         return ret;
 128                 }
 129         }
 130
 131         nouveau_bo_placement_set(nvbo, flags, 0);
 132
 133         nvbo->channel = chan;
 134         ret = ttm_bo_init(&dev_priv->ttm.bdev, &nvbo->bo, size,
 135                           ttm_bo_type_device, &nvbo->placement, align, 0,
 136                           false, NULL, size, nouveau_bo_del_ttm);
 137         if (ret) {
 138                 /* ttm will call nouveau_bo_del_ttm if it fails.. */
 139                 return ret;
 140         }
 141         nvbo->channel = NULL;
 142
 143         if (nvbo->vma.node) {
 144                 if (nvbo->bo.mem.mem_type == TTM_PL_VRAM)
 145                         nvbo->bo.offset = nvbo->vma.offset;
 146         }
 147
 148         *pnvbo = nvbo;
 149         return 0;
 150 }
 151
 152 static void
 153 set_placement_list(uint32_t *pl, unsigned *n, uint32_t type, uint32_t flags)
 154 {
 155         *n = 0;
 156
 157         if (type & TTM_PL_FLAG_VRAM)
 158                 pl[(*n)++] = TTM_PL_FLAG_VRAM | flags;
 159         if (type & TTM_PL_FLAG_TT)
 160                 pl[(*n)++] = TTM_PL_FLAG_TT | flags;
 161         if (type & TTM_PL_FLAG_SYSTEM)
 162                 pl[(*n)++] = TTM_PL_FLAG_SYSTEM | flags;
 163 }
 164
 165 static void
 166 set_placement_range(struct nouveau_bo *nvbo, uint32_t type)
 167 {
 168         struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
 169
 170         if (dev_priv->card_type == NV_10 &&
 171             nvbo->tile_mode && (type & TTM_PL_FLAG_VRAM)) {
 172                 /*
 173                  * Make sure that the color and depth buffers are handled
 174                  * by independent memory controller units. Up to a 9x
 175                  * speed up when alpha-blending and depth-test are enabled
 176                  * at the same time.
 177                  */
 178                 int vram_pages = dev_priv->vram_size >> PAGE_SHIFT;
 179
 180                 if (nvbo->tile_flags & NOUVEAU_GEM_TILE_ZETA) {
 181                         nvbo->placement.fpfn = vram_pages / 2;
 182                         nvbo->placement.lpfn = ~0;
 183                 } else {
 184                         nvbo->placement.fpfn = 0;
 185                         nvbo->placement.lpfn = vram_pages / 2;
 186                 }
 187         }
 188 }
 189
 190 void
 191 nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy)
 192 {
 193         struct ttm_placement *pl = &nvbo->placement;
 194         uint32_t flags = TTM_PL_MASK_CACHING |
 195                 (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0);
 196
 197         pl->placement = nvbo->placements;
 198         set_placement_list(nvbo->placements, &pl->num_placement,
 199                            type, flags);
 200
 201         pl->busy_placement = nvbo->busy_placements;
 202         set_placement_list(nvbo->busy_placements, &pl->num_busy_placement,
 203                            type | busy, flags);
 204
 205         set_placement_range(nvbo, type);
 206 }
 207
 208 int
 209 nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype)
 210 {
 211         struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
 212         struct ttm_buffer_object *bo = &nvbo->bo;
 213         int ret;
 214
 215         if (nvbo->pin_refcnt && !(memtype & (1 << bo->mem.mem_type))) {
 216                 NV_ERROR(nouveau_bdev(bo->bdev)->dev,
 217                          "bo %p pinned elsewhere: 0x%08x vs 0x%08x\n", bo,
 218                          1 << bo->mem.mem_type, memtype);
 219                 return -EINVAL;
 220         }
 221
 222         if (nvbo->pin_refcnt++)
 223                 return 0;
 224
 225         ret = ttm_bo_reserve(bo, false, false, false, 0);
 226         if (ret)
 227                 goto out;
 228
 229         nouveau_bo_placement_set(nvbo, memtype, 0);
 230
 231         ret = nouveau_bo_validate(nvbo, false, false, false);
 232         if (ret == 0) {
 233                 switch (bo->mem.mem_type) {
 234                 case TTM_PL_VRAM:
 235                         dev_priv->fb_aper_free -= bo->mem.size;
 236                         break;
 237                 case TTM_PL_TT:
 238                         dev_priv->gart_info.aper_free -= bo->mem.size;
 239                         break;
 240                 default:
 241                         break;
 242                 }
 243         }
 244         ttm_bo_unreserve(bo);
 245 out:
 246         if (unlikely(ret))
 247                 nvbo->pin_refcnt--;
 248         return ret;
 249 }
 250
 251 int
 252 nouveau_bo_unpin(struct nouveau_bo *nvbo)
 253 {
 254         struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
 255         struct ttm_buffer_object *bo = &nvbo->bo;
 256         int ret;
 257
 258         if (--nvbo->pin_refcnt)
 259                 return 0;
 260
 261         ret = ttm_bo_reserve(bo, false, false, false, 0);
 262         if (ret)
 263                 return ret;
 264
 265         nouveau_bo_placement_set(nvbo, bo->mem.placement, 0);
 266
 267         ret = nouveau_bo_validate(nvbo, false, false, false);
 268         if (ret == 0) {
 269                 switch (bo->mem.mem_type) {
 270                 case TTM_PL_VRAM:
 271                         dev_priv->fb_aper_free += bo->mem.size;
 272                         break;
 273                 case TTM_PL_TT:
 274                         dev_priv->gart_info.aper_free += bo->mem.size;
 275                         break;
 276                 default:
 277                         break;
 278                 }
 279         }
 280
 281         ttm_bo_unreserve(bo);
 282         return ret;
 283 }
 284
 285 int
 286 nouveau_bo_map(struct nouveau_bo *nvbo)
 287 {
 288         int ret;
 289
 290         ret = ttm_bo_reserve(&nvbo->bo, false, false, false, 0);
 291         if (ret)
 292                 return ret;
 293
 294         ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap);
 295         ttm_bo_unreserve(&nvbo->bo);
 296         return ret;
 297 }
 298
 299 void
 300 nouveau_bo_unmap(struct nouveau_bo *nvbo)
 301 {
 302         if (nvbo)
 303                 ttm_bo_kunmap(&nvbo->kmap);
 304 }
 305
 306 int
 307 nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible,
 308                     bool no_wait_reserve, bool no_wait_gpu)
 309 {
 310         int ret;
 311
 312         ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, interruptible,
 313                               no_wait_reserve, no_wait_gpu);
 314         if (ret)
 315                 return ret;
 316
 317         if (nvbo->vma.node) {
 318                 if (nvbo->bo.mem.mem_type == TTM_PL_VRAM)
 319                         nvbo->bo.offset = nvbo->vma.offset;
 320         }
 321
 322         return 0;
 323 }
 324
 325 u16
 326 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index)
 327 {
 328         bool is_iomem;
 329         u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
 330         mem = &mem[index];
 331         if (is_iomem)
 332                 return ioread16_native((void __force __iomem *)mem);
 333         else
 334                 return *mem;
 335 }
 336
 337 void
 338 nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
 339 {
 340         bool is_iomem;
 341         u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
 342         mem = &mem[index];
 343         if (is_iomem)
 344                 iowrite16_native(val, (void __force __iomem *)mem);
 345         else
 346                 *mem = val;
 347 }
 348
 349 u32
 350 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
 351 {
 352         bool is_iomem;
 353         u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
 354         mem = &mem[index];
 355         if (is_iomem)
 356                 return ioread32_native((void __force __iomem *)mem);
 357         else
 358                 return *mem;
 359 }
 360
 361 void
 362 nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
 363 {
 364         bool is_iomem;
 365         u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
 366         mem = &mem[index];
 367         if (is_iomem)
 368                 iowrite32_native(val, (void __force __iomem *)mem);
 369         else
 370                 *mem = val;
 371 }
 372
 373 static struct ttm_backend *
 374 nouveau_bo_create_ttm_backend_entry(struct ttm_bo_device *bdev)
 375 {
 376         struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
 377         struct drm_device *dev = dev_priv->dev;
 378
 379         switch (dev_priv->gart_info.type) {
 380 #if __OS_HAS_AGP
 381         case NOUVEAU_GART_AGP:
 382                 return ttm_agp_backend_init(bdev, dev->agp->bridge);
 383 #endif
 384         case NOUVEAU_GART_SGDMA:
 385                 return nouveau_sgdma_init_ttm(dev);
 386         default:
 387                 NV_ERROR(dev, "Unknown GART type %d\n",
 388                          dev_priv->gart_info.type);
 389                 break;
 390         }
 391
 392         return NULL;
 393 }
 394
 395 static int
 396 nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
 397 {
 398         /* We'll do this from user space. */
 399         return 0;
 400 }
 401
 402 static int
 403 nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
 404                          struct ttm_mem_type_manager *man)
 405 {
 406         struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
 407         struct drm_device *dev = dev_priv->dev;
 408
 409         switch (type) {
 410         case TTM_PL_SYSTEM:
 411                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
 412                 man->available_caching = TTM_PL_MASK_CACHING;
 413                 man->default_caching = TTM_PL_FLAG_CACHED;
 414                 break;
 415         case TTM_PL_VRAM:
 416                 if (dev_priv->card_type >= NV_50) {
 417                         man->func = &nouveau_vram_manager;
 418                         man->io_reserve_fastpath = false;
 419                         man->use_io_reserve_lru = true;
 420                 } else {
 421                         man->func = &ttm_bo_manager_func;
 422                 }
 423                 man->flags = TTM_MEMTYPE_FLAG_FIXED |
 424                              TTM_MEMTYPE_FLAG_MAPPABLE;
 425                 man->available_caching = TTM_PL_FLAG_UNCACHED |
 426                                          TTM_PL_FLAG_WC;
 427                 man->default_caching = TTM_PL_FLAG_WC;
 428                 break;
 429         case TTM_PL_TT:
 430                 man->func = &ttm_bo_manager_func;
 431                 switch (dev_priv->gart_info.type) {
 432                 case NOUVEAU_GART_AGP:
 433                         man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
 434                         man->available_caching = TTM_PL_FLAG_UNCACHED |
 435                                 TTM_PL_FLAG_WC;
 436                         man->default_caching = TTM_PL_FLAG_WC;
 437                         break;
 438                 case NOUVEAU_GART_SGDMA:
 439                         man->flags = TTM_MEMTYPE_FLAG_MAPPABLE |
 440                                      TTM_MEMTYPE_FLAG_CMA;
 441                         man->available_caching = TTM_PL_MASK_CACHING;
 442                         man->default_caching = TTM_PL_FLAG_CACHED;
 443                         man->gpu_offset = dev_priv->gart_info.aper_base;
 444                         break;
 445                 default:
 446                         NV_ERROR(dev, "Unknown GART type: %d\n",
 447                                  dev_priv->gart_info.type);
 448                         return -EINVAL;
 449                 }
 450                 break;
 451         default:
 452                 NV_ERROR(dev, "Unsupported memory type %u\n", (unsigned)type);
 453                 return -EINVAL;
 454         }
 455         return 0;
 456 }
 457
 458 static void
 459 nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
 460 {
 461         struct nouveau_bo *nvbo = nouveau_bo(bo);
 462
 463         switch (bo->mem.mem_type) {
 464         case TTM_PL_VRAM:
 465                 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT,
 466                                          TTM_PL_FLAG_SYSTEM);
 467                 break;
 468         default:
 469                 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0);
 470                 break;
 471         }
 472
 473         *pl = nvbo->placement;
 474 }
 475
 476
 477 /* GPU-assisted copy using NV_MEMORY_TO_MEMORY_FORMAT, can access
 478  * TTM_PL_{VRAM,TT} directly.
 479  */
 480
 481 static int
 482 nouveau_bo_move_accel_cleanup(struct nouveau_channel *chan,
 483                               struct nouveau_bo *nvbo, bool evict,
 484                               bool no_wait_reserve, bool no_wait_gpu,
 485                               struct ttm_mem_reg *new_mem)
 486 {
 487         struct nouveau_fence *fence = NULL;
 488         int ret;
 489
 490         ret = nouveau_fence_new(chan, &fence, true);
 491         if (ret)
 492                 return ret;
 493
 494         ret = ttm_bo_move_accel_cleanup(&nvbo->bo, fence, NULL, evict,
 495                                         no_wait_reserve, no_wait_gpu, new_mem);
 496         nouveau_fence_unref(&fence);
 497         return ret;
 498 }
 499
 500 static inline uint32_t
 501 nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo,
 502                       struct nouveau_channel *chan, struct ttm_mem_reg *mem)
 503 {
 504         struct nouveau_bo *nvbo = nouveau_bo(bo);
 505
 506         if (nvbo->no_vm) {
 507                 if (mem->mem_type == TTM_PL_TT)
 508                         return NvDmaGART;
 509                 return NvDmaVRAM;
 510         }
 511
 512         if (mem->mem_type == TTM_PL_TT)
 513                 return chan->gart_handle;
 514         return chan->vram_handle;
 515 }
 516
 517 static int
 518 nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
 519                   struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
 520 {
 521         struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
 522         struct nouveau_bo *nvbo = nouveau_bo(bo);
 523         u64 src_offset = old_mem->start << PAGE_SHIFT;
 524         u64 dst_offset = new_mem->start << PAGE_SHIFT;
 525         u32 page_count = new_mem->num_pages;
 526         int ret;
 527
 528         if (!nvbo->no_vm) {
 529                 if (old_mem->mem_type == TTM_PL_VRAM)
 530                         src_offset  = nvbo->vma.offset;
 531                 else
 532                         src_offset += dev_priv->gart_info.aper_base;
 533
 534                 if (new_mem->mem_type == TTM_PL_VRAM)
 535                         dst_offset  = nvbo->vma.offset;
 536                 else
 537                         dst_offset += dev_priv->gart_info.aper_base;
 538         }
 539
 540         page_count = new_mem->num_pages;
 541         while (page_count) {
 542                 int line_count = (page_count > 2047) ? 2047 : page_count;
 543
 544                 ret = RING_SPACE(chan, 12);
 545                 if (ret)
 546                         return ret;
 547
 548                 BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0238, 2);
 549                 OUT_RING  (chan, upper_32_bits(dst_offset));
 550                 OUT_RING  (chan, lower_32_bits(dst_offset));
 551                 BEGIN_NVC0(chan, 2, NvSubM2MF, 0x030c, 6);
 552                 OUT_RING  (chan, upper_32_bits(src_offset));
 553                 OUT_RING  (chan, lower_32_bits(src_offset));
 554                 OUT_RING  (chan, PAGE_SIZE); /* src_pitch */
 555                 OUT_RING  (chan, PAGE_SIZE); /* dst_pitch */
 556                 OUT_RING  (chan, PAGE_SIZE); /* line_length */
 557                 OUT_RING  (chan, line_count);
 558                 BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0300, 1);
 559                 OUT_RING  (chan, 0x00100110);
 560
 561                 page_count -= line_count;
 562                 src_offset += (PAGE_SIZE * line_count);
 563                 dst_offset += (PAGE_SIZE * line_count);
 564         }
 565
 566         return 0;
 567 }
 568
 569 static int
 570 nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
 571                   struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
 572 {
 573         struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
 574         struct nouveau_bo *nvbo = nouveau_bo(bo);
 575         u64 length = (new_mem->num_pages << PAGE_SHIFT);
 576         u64 src_offset, dst_offset;
 577         int ret;
 578
 579         src_offset = old_mem->start << PAGE_SHIFT;
 580         dst_offset = new_mem->start << PAGE_SHIFT;
 581         if (!nvbo->no_vm) {
 582                 if (old_mem->mem_type == TTM_PL_VRAM)
 583                         src_offset  = nvbo->vma.offset;
 584                 else
 585                         src_offset += dev_priv->gart_info.aper_base;
 586
 587                 if (new_mem->mem_type == TTM_PL_VRAM)
 588                         dst_offset  = nvbo->vma.offset;
 589                 else
 590                         dst_offset += dev_priv->gart_info.aper_base;
 591         }
 592
 593         ret = RING_SPACE(chan, 3);
 594         if (ret)
 595                 return ret;
 596
 597         BEGIN_RING(chan, NvSubM2MF, 0x0184, 2);
 598         OUT_RING  (chan, nouveau_bo_mem_ctxdma(bo, chan, old_mem));
 599         OUT_RING  (chan, nouveau_bo_mem_ctxdma(bo, chan, new_mem));
 600
 601         while (length) {
 602                 u32 amount, stride, height;
 603
 604                 amount  = min(length, (u64)(4 * 1024 * 1024));
 605                 stride  = 16 * 4;
 606                 height  = amount / stride;
 607
 608                 if (new_mem->mem_type == TTM_PL_VRAM &&
 609                     nouveau_bo_tile_layout(nvbo)) {
 610                         ret = RING_SPACE(chan, 8);
 611                         if (ret)
 612                                 return ret;
 613
 614                         BEGIN_RING(chan, NvSubM2MF, 0x0200, 7);
 615                         OUT_RING  (chan, 0);
 616                         OUT_RING  (chan, 0);
 617                         OUT_RING  (chan, stride);
 618                         OUT_RING  (chan, height);
 619                         OUT_RING  (chan, 1);
 620                         OUT_RING  (chan, 0);
 621                         OUT_RING  (chan, 0);
 622                 } else {
 623                         ret = RING_SPACE(chan, 2);
 624                         if (ret)
 625                                 return ret;
 626
 627                         BEGIN_RING(chan, NvSubM2MF, 0x0200, 1);
 628                         OUT_RING  (chan, 1);
 629                 }
 630                 if (old_mem->mem_type == TTM_PL_VRAM &&
 631                     nouveau_bo_tile_layout(nvbo)) {
 632                         ret = RING_SPACE(chan, 8);
 633                         if (ret)
 634                                 return ret;
 635
 636                         BEGIN_RING(chan, NvSubM2MF, 0x021c, 7);
 637                         OUT_RING  (chan, 0);
 638                         OUT_RING  (chan, 0);
 639                         OUT_RING  (chan, stride);
 640                         OUT_RING  (chan, height);
 641                         OUT_RING  (chan, 1);
 642                         OUT_RING  (chan, 0);
 643                         OUT_RING  (chan, 0);
 644                 } else {
 645                         ret = RING_SPACE(chan, 2);
 646                         if (ret)
 647                                 return ret;
 648
 649                         BEGIN_RING(chan, NvSubM2MF, 0x021c, 1);
 650                         OUT_RING  (chan, 1);
 651                 }
 652
 653                 ret = RING_SPACE(chan, 14);
 654                 if (ret)
 655                         return ret;
 656
 657                 BEGIN_RING(chan, NvSubM2MF, 0x0238, 2);
 658                 OUT_RING  (chan, upper_32_bits(src_offset));
 659                 OUT_RING  (chan, upper_32_bits(dst_offset));
 660                 BEGIN_RING(chan, NvSubM2MF, 0x030c, 8);
 661                 OUT_RING  (chan, lower_32_bits(src_offset));
 662                 OUT_RING  (chan, lower_32_bits(dst_offset));
 663                 OUT_RING  (chan, stride);
 664                 OUT_RING  (chan, stride);
 665                 OUT_RING  (chan, stride);
 666                 OUT_RING  (chan, height);
 667                 OUT_RING  (chan, 0x00000101);
 668                 OUT_RING  (chan, 0x00000000);
 669                 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
 670                 OUT_RING  (chan, 0);
 671
 672                 length -= amount;
 673                 src_offset += amount;
 674                 dst_offset += amount;
 675         }
 676
 677         return 0;
 678 }
 679
 680 static int
 681 nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
 682                   struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
 683 {
 684         u32 src_offset = old_mem->start << PAGE_SHIFT;
 685         u32 dst_offset = new_mem->start << PAGE_SHIFT;
 686         u32 page_count = new_mem->num_pages;
 687         int ret;
 688
 689         ret = RING_SPACE(chan, 3);
 690         if (ret)
 691                 return ret;
 692
 693         BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2);
 694         OUT_RING  (chan, nouveau_bo_mem_ctxdma(bo, chan, old_mem));
 695         OUT_RING  (chan, nouveau_bo_mem_ctxdma(bo, chan, new_mem));
 696
 697         page_count = new_mem->num_pages;
 698         while (page_count) {
 699                 int line_count = (page_count > 2047) ? 2047 : page_count;
 700
 701                 ret = RING_SPACE(chan, 11);
 702                 if (ret)
 703                         return ret;
 704
 705                 BEGIN_RING(chan, NvSubM2MF,
 706                                  NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
 707                 OUT_RING  (chan, src_offset);
 708                 OUT_RING  (chan, dst_offset);
 709                 OUT_RING  (chan, PAGE_SIZE); /* src_pitch */
 710                 OUT_RING  (chan, PAGE_SIZE); /* dst_pitch */
 711                 OUT_RING  (chan, PAGE_SIZE); /* line_length */
 712                 OUT_RING  (chan, line_count);
 713                 OUT_RING  (chan, 0x00000101);
 714                 OUT_RING  (chan, 0x00000000);
 715                 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
 716                 OUT_RING  (chan, 0);
 717
 718                 page_count -= line_count;
 719                 src_offset += (PAGE_SIZE * line_count);
 720                 dst_offset += (PAGE_SIZE * line_count);
 721         }
 722
 723         return 0;
 724 }
 725
 726 static int
 727 nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr,
 728                      bool no_wait_reserve, bool no_wait_gpu,
 729                      struct ttm_mem_reg *new_mem)
 730 {
 731         struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
 732         struct nouveau_bo *nvbo = nouveau_bo(bo);
 733         struct nouveau_channel *chan;
 734         int ret;
 735
 736         chan = nvbo->channel;
 737         if (!chan || nvbo->no_vm) {
 738                 chan = dev_priv->channel;
 739                 mutex_lock_nested(&chan->mutex, NOUVEAU_KCHANNEL_MUTEX);
 740         }
 741
 742         if (dev_priv->card_type < NV_50)
 743                 ret = nv04_bo_move_m2mf(chan, bo, &bo->mem, new_mem);
 744         else
 745         if (dev_priv->card_type < NV_C0)
 746                 ret = nv50_bo_move_m2mf(chan, bo, &bo->mem, new_mem);
 747         else
 748                 ret = nvc0_bo_move_m2mf(chan, bo, &bo->mem, new_mem);
 749         if (ret == 0) {
 750                 ret = nouveau_bo_move_accel_cleanup(chan, nvbo, evict,
 751                                                     no_wait_reserve,
 752                                                     no_wait_gpu, new_mem);
 753         }
 754
 755         if (chan == dev_priv->channel)
 756                 mutex_unlock(&chan->mutex);
 757         return ret;
 758 }
 759
 760 static int
 761 nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
 762                       bool no_wait_reserve, bool no_wait_gpu,
 763                       struct ttm_mem_reg *new_mem)
 764 {
 765         u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
 766         struct ttm_placement placement;
 767         struct ttm_mem_reg tmp_mem;
 768         int ret;
 769
 770         placement.fpfn = placement.lpfn = 0;
 771         placement.num_placement = placement.num_busy_placement = 1;
 772         placement.placement = placement.busy_placement = &placement_memtype;
 773
 774         tmp_mem = *new_mem;
 775         tmp_mem.mm_node = NULL;
 776         ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_reserve, no_wait_gpu);
 777         if (ret)
 778                 return ret;
 779
 780         ret = ttm_tt_bind(bo->ttm, &tmp_mem);
 781         if (ret)
 782                 goto out;
 783
 784         ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_reserve, no_wait_gpu, &tmp_mem);
 785         if (ret)
 786                 goto out;
 787
 788         ret = ttm_bo_move_ttm(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
 789 out:
 790         ttm_bo_mem_put(bo, &tmp_mem);
 791         return ret;
 792 }
 793
 794 static int
 795 nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
 796                       bool no_wait_reserve, bool no_wait_gpu,
 797                       struct ttm_mem_reg *new_mem)
 798 {
 799         u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
 800         struct ttm_placement placement;
 801         struct ttm_mem_reg tmp_mem;
 802         int ret;
 803
 804         placement.fpfn = placement.lpfn = 0;
 805         placement.num_placement = placement.num_busy_placement = 1;
 806         placement.placement = placement.busy_placement = &placement_memtype;
 807
 808         tmp_mem = *new_mem;
 809         tmp_mem.mm_node = NULL;
 810         ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_reserve, no_wait_gpu);
 811         if (ret)
 812                 return ret;
 813
 814         ret = ttm_bo_move_ttm(bo, evict, no_wait_reserve, no_wait_gpu, &tmp_mem);
 815         if (ret)
 816                 goto out;
 817
 818         ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
 819         if (ret)
 820                 goto out;
 821
 822 out:
 823         ttm_bo_mem_put(bo, &tmp_mem);
 824         return ret;
 825 }
 826
 827 static int
 828 nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem,
 829                    struct nouveau_tile_reg **new_tile)
 830 {
 831         struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
 832         struct drm_device *dev = dev_priv->dev;
 833         struct nouveau_bo *nvbo = nouveau_bo(bo);
 834         uint64_t offset;
 835
 836         if (nvbo->no_vm || new_mem->mem_type != TTM_PL_VRAM) {
 837                 /* Nothing to do. */
 838                 *new_tile = NULL;
 839                 return 0;
 840         }
 841
 842         offset = new_mem->start << PAGE_SHIFT;
 843
 844         if (dev_priv->chan_vm) {
 845                 nouveau_vm_map(&nvbo->vma, new_mem->mm_node);
 846         } else if (dev_priv->card_type >= NV_10) {
 847                 *new_tile = nv10_mem_set_tiling(dev, offset, new_mem->size,
 848                                                 nvbo->tile_mode,
 849                                                 nvbo->tile_flags);
 850         }
 851
 852         return 0;
 853 }
 854
 855 static void
 856 nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
 857                       struct nouveau_tile_reg *new_tile,
 858                       struct nouveau_tile_reg **old_tile)
 859 {
 860         struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
 861         struct drm_device *dev = dev_priv->dev;
 862
 863         if (dev_priv->card_type >= NV_10 &&
 864             dev_priv->card_type < NV_50) {
 865                 nv10_mem_put_tile_region(dev, *old_tile, bo->sync_obj);
 866                 *old_tile = new_tile;
 867         }
 868 }
 869
 870 static int
 871 nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr,
 872                 bool no_wait_reserve, bool no_wait_gpu,
 873                 struct ttm_mem_reg *new_mem)
 874 {
 875         struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
 876         struct nouveau_bo *nvbo = nouveau_bo(bo);
 877         struct ttm_mem_reg *old_mem = &bo->mem;
 878         struct nouveau_tile_reg *new_tile = NULL;
 879         int ret = 0;
 880
 881         ret = nouveau_bo_vm_bind(bo, new_mem, &new_tile);
 882         if (ret)
 883                 return ret;
 884
 885         /* Fake bo copy. */
 886         if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
 887                 BUG_ON(bo->mem.mm_node != NULL);
 888                 bo->mem = *new_mem;
 889                 new_mem->mm_node = NULL;
 890                 goto out;
 891         }
 892
 893         /* Software copy if the card isn't up and running yet. */
 894         if (!dev_priv->channel) {
 895                 ret = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
 896                 goto out;
 897         }
 898
 899         /* Hardware assisted copy. */
 900         if (new_mem->mem_type == TTM_PL_SYSTEM)
 901                 ret = nouveau_bo_move_flipd(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
 902         else if (old_mem->mem_type == TTM_PL_SYSTEM)
 903                 ret = nouveau_bo_move_flips(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
 904         else
 905                 ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
 906
 907         if (!ret)
 908                 goto out;
 909
 910         /* Fallback to software copy. */
 911         ret = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
 912
 913 out:
 914         if (ret)
 915                 nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
 916         else
 917                 nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
 918
 919         return ret;
 920 }
 921
 922 static int
 923 nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 924 {
 925         return 0;
 926 }
 927
 928 static int
 929 nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 930 {
 931         struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
 932         struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
 933         struct drm_device *dev = dev_priv->dev;
 934         int ret;
 935
 936         mem->bus.addr = NULL;
 937         mem->bus.offset = 0;
 938         mem->bus.size = mem->num_pages << PAGE_SHIFT;
 939         mem->bus.base = 0;
 940         mem->bus.is_iomem = false;
 941         if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
 942                 return -EINVAL;
 943         switch (mem->mem_type) {
 944         case TTM_PL_SYSTEM:
 945                 /* System memory */
 946                 return 0;
 947         case TTM_PL_TT:
 948 #if __OS_HAS_AGP
 949                 if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) {
 950                         mem->bus.offset = mem->start << PAGE_SHIFT;
 951                         mem->bus.base = dev_priv->gart_info.aper_base;
 952                         mem->bus.is_iomem = true;
 953                 }
 954 #endif
 955                 break;
 956         case TTM_PL_VRAM:
 957         {
 958                 struct nouveau_vram *vram = mem->mm_node;
 959                 u8 page_shift;
 960
 961                 if (!dev_priv->bar1_vm) {
 962                         mem->bus.offset = mem->start << PAGE_SHIFT;
 963                         mem->bus.base = pci_resource_start(dev->pdev, 1);
 964                         mem->bus.is_iomem = true;
 965                         break;
 966                 }
 967
 968                 if (dev_priv->card_type == NV_C0)
 969                         page_shift = vram->page_shift;
 970                 else
 971                         page_shift = 12;
 972
 973                 ret = nouveau_vm_get(dev_priv->bar1_vm, mem->bus.size,
 974                                      page_shift, NV_MEM_ACCESS_RW,
 975                                      &vram->bar_vma);
 976                 if (ret)
 977                         return ret;
 978
 979                 nouveau_vm_map(&vram->bar_vma, vram);
 980                 if (ret) {
 981                         nouveau_vm_put(&vram->bar_vma);
 982                         return ret;
 983                 }
 984
 985                 mem->bus.offset = vram->bar_vma.offset;
 986                 if (dev_priv->card_type == NV_50) /*XXX*/
 987                         mem->bus.offset -= 0x0020000000ULL;
 988                 mem->bus.base = pci_resource_start(dev->pdev, 1);
 989                 mem->bus.is_iomem = true;
 990         }
 991                 break;
 992         default:
 993                 return -EINVAL;
 994         }
 995         return 0;
 996 }
 997
 998 static void
 999 nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
1000 {
1001         struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
1002         struct nouveau_vram *vram = mem->mm_node;
1003
1004         if (!dev_priv->bar1_vm || mem->mem_type != TTM_PL_VRAM)
1005                 return;
1006
1007         if (!vram->bar_vma.node)
1008                 return;
1009
1010         nouveau_vm_unmap(&vram->bar_vma);
1011         nouveau_vm_put(&vram->bar_vma);
1012 }
1013
1014 static int
1015 nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
1016 {
1017         struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
1018         struct nouveau_bo *nvbo = nouveau_bo(bo);
1019
1020         /* as long as the bo isn't in vram, and isn't tiled, we've got
1021          * nothing to do here.
1022          */
1023         if (bo->mem.mem_type != TTM_PL_VRAM) {
1024                 if (dev_priv->card_type < NV_50 ||
1025                     !nouveau_bo_tile_layout(nvbo))
1026                         return 0;
1027         }
1028
1029         /* make sure bo is in mappable vram */
1030         if (bo->mem.start + bo->mem.num_pages < dev_priv->fb_mappable_pages)
1031                 return 0;
1032
1033
1034         nvbo->placement.fpfn = 0;
1035         nvbo->placement.lpfn = dev_priv->fb_mappable_pages;
1036         nouveau_bo_placement_set(nvbo, TTM_PL_VRAM, 0);
1037         return nouveau_bo_validate(nvbo, false, true, false);
1038 }
1039
1040 void
1041 nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence)
1042 {
1043         struct nouveau_fence *old_fence;
1044
1045         if (likely(fence))
1046                 nouveau_fence_ref(fence);
1047
1048         spin_lock(&nvbo->bo.bdev->fence_lock);
1049         old_fence = nvbo->bo.sync_obj;
1050         nvbo->bo.sync_obj = fence;
1051         spin_unlock(&nvbo->bo.bdev->fence_lock);
1052
1053         nouveau_fence_unref(&old_fence);
1054 }
1055
1056 struct ttm_bo_driver nouveau_bo_driver = {
1057         .create_ttm_backend_entry = nouveau_bo_create_ttm_backend_entry,
1058         .invalidate_caches = nouveau_bo_invalidate_caches,
1059         .init_mem_type = nouveau_bo_init_mem_type,
1060         .evict_flags = nouveau_bo_evict_flags,
1061         .move = nouveau_bo_move,
1062         .verify_access = nouveau_bo_verify_access,
1063         .sync_obj_signaled = __nouveau_fence_signalled,
1064         .sync_obj_wait = __nouveau_fence_wait,
1065         .sync_obj_flush = __nouveau_fence_flush,
1066         .sync_obj_unref = __nouveau_fence_unref,
1067         .sync_obj_ref = __nouveau_fence_ref,
1068         .fault_reserve_notify = &nouveau_ttm_fault_reserve_notify,
1069         .io_mem_reserve = &nouveau_ttm_io_mem_reserve,
1070         .io_mem_free = &nouveau_ttm_io_mem_free,
1071 };
1072