2 * Copyright 2005-2006 Stephane Marchesin
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
27 #include "nouveau_drv.h"
28 #include "nouveau_drm.h"
29 #include "nouveau_dma.h"
32 nouveau_channel_pushbuf_ctxdma_init(struct nouveau_channel *chan)
34 struct drm_device *dev = chan->dev;
35 struct drm_nouveau_private *dev_priv = dev->dev_private;
36 struct nouveau_bo *pb = chan->pushbuf_bo;
37 struct nouveau_gpuobj *pushbuf = NULL;
40 if (dev_priv->card_type >= NV_50) {
41 if (dev_priv->card_type < NV_C0) {
42 ret = nouveau_gpuobj_dma_new(chan,
43 NV_CLASS_DMA_IN_MEMORY, 0,
49 chan->pushbuf_base = pb->bo.offset;
51 if (pb->bo.mem.mem_type == TTM_PL_TT) {
52 ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, 0,
53 dev_priv->gart_info.aper_size,
55 NV_MEM_TARGET_GART, &pushbuf);
56 chan->pushbuf_base = pb->bo.mem.start << PAGE_SHIFT;
58 if (dev_priv->card_type != NV_04) {
59 ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, 0,
60 dev_priv->fb_available_size,
62 NV_MEM_TARGET_VRAM, &pushbuf);
63 chan->pushbuf_base = pb->bo.mem.start << PAGE_SHIFT;
65 /* NV04 cmdbuf hack, from original ddx.. not sure of it's
66 * exact reason for existing :) PCI access to cmdbuf in
69 ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
70 pci_resource_start(dev->pdev, 1),
71 dev_priv->fb_available_size,
73 NV_MEM_TARGET_PCI, &pushbuf);
74 chan->pushbuf_base = pb->bo.mem.start << PAGE_SHIFT;
77 nouveau_gpuobj_ref(pushbuf, &chan->pushbuf);
78 nouveau_gpuobj_ref(NULL, &pushbuf);
82 static struct nouveau_bo *
83 nouveau_channel_user_pushbuf_alloc(struct drm_device *dev)
85 struct nouveau_bo *pushbuf = NULL;
88 if (nouveau_vram_pushbuf)
89 location = TTM_PL_FLAG_VRAM;
91 location = TTM_PL_FLAG_TT;
93 ret = nouveau_bo_new(dev, NULL, 65536, 0, location, 0, 0x0000, false,
96 NV_ERROR(dev, "error allocating DMA push buffer: %d\n", ret);
100 ret = nouveau_bo_pin(pushbuf, location);
102 NV_ERROR(dev, "error pinning DMA push buffer: %d\n", ret);
103 nouveau_bo_ref(NULL, &pushbuf);
107 ret = nouveau_bo_map(pushbuf);
109 nouveau_bo_unpin(pushbuf);
110 nouveau_bo_ref(NULL, &pushbuf);
117 /* allocates and initializes a fifo for user space consumption */
119 nouveau_channel_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret,
120 struct drm_file *file_priv,
121 uint32_t vram_handle, uint32_t gart_handle)
123 struct drm_nouveau_private *dev_priv = dev->dev_private;
124 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
125 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
126 struct nouveau_channel *chan;
130 /* allocate and lock channel structure */
131 chan = kzalloc(sizeof(*chan), GFP_KERNEL);
135 chan->file_priv = file_priv;
136 chan->vram_handle = vram_handle;
137 chan->gart_handle = gart_handle;
139 kref_init(&chan->ref);
140 atomic_set(&chan->users, 1);
141 mutex_init(&chan->mutex);
142 mutex_lock(&chan->mutex);
144 /* allocate hw channel id */
145 spin_lock_irqsave(&dev_priv->channels.lock, flags);
146 for (chan->id = 0; chan->id < pfifo->channels; chan->id++) {
147 if (!dev_priv->channels.ptr[chan->id]) {
148 nouveau_channel_ref(chan, &dev_priv->channels.ptr[chan->id]);
152 spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
154 if (chan->id == pfifo->channels) {
155 mutex_unlock(&chan->mutex);
160 NV_DEBUG(dev, "initialising channel %d\n", chan->id);
161 INIT_LIST_HEAD(&chan->nvsw.vbl_wait);
162 INIT_LIST_HEAD(&chan->nvsw.flip);
163 INIT_LIST_HEAD(&chan->fence.pending);
165 /* Allocate DMA push buffer */
166 chan->pushbuf_bo = nouveau_channel_user_pushbuf_alloc(dev);
167 if (!chan->pushbuf_bo) {
169 NV_ERROR(dev, "pushbuf %d\n", ret);
170 nouveau_channel_put(&chan);
174 nouveau_dma_pre_init(chan);
175 chan->user_put = 0x40;
176 chan->user_get = 0x44;
178 /* Allocate space for per-channel fixed notifier memory */
179 ret = nouveau_notifier_init_channel(chan);
181 NV_ERROR(dev, "ntfy %d\n", ret);
182 nouveau_channel_put(&chan);
186 /* Setup channel's default objects */
187 ret = nouveau_gpuobj_channel_init(chan, vram_handle, gart_handle);
189 NV_ERROR(dev, "gpuobj %d\n", ret);
190 nouveau_channel_put(&chan);
194 /* Create a dma object for the push buffer */
195 ret = nouveau_channel_pushbuf_ctxdma_init(chan);
197 NV_ERROR(dev, "pbctxdma %d\n", ret);
198 nouveau_channel_put(&chan);
202 /* disable the fifo caches */
203 pfifo->reassign(dev, false);
205 /* Create a graphics context for new channel */
206 if (dev_priv->card_type < NV_50) {
207 ret = pgraph->create_context(chan);
209 nouveau_channel_put(&chan);
214 /* Construct inital RAMFC for new channel */
215 ret = pfifo->create_context(chan);
217 nouveau_channel_put(&chan);
221 pfifo->reassign(dev, true);
223 ret = nouveau_dma_init(chan);
225 ret = nouveau_fence_channel_init(chan);
227 nouveau_channel_put(&chan);
231 nouveau_debugfs_channel_init(chan);
233 NV_DEBUG(dev, "channel %d initialised\n", chan->id);
238 struct nouveau_channel *
239 nouveau_channel_get_unlocked(struct nouveau_channel *ref)
241 struct nouveau_channel *chan = NULL;
243 if (likely(ref && atomic_inc_not_zero(&ref->users)))
244 nouveau_channel_ref(ref, &chan);
249 struct nouveau_channel *
250 nouveau_channel_get(struct drm_device *dev, struct drm_file *file_priv, int id)
252 struct drm_nouveau_private *dev_priv = dev->dev_private;
253 struct nouveau_channel *chan;
256 if (unlikely(id < 0 || id >= NOUVEAU_MAX_CHANNEL_NR))
257 return ERR_PTR(-EINVAL);
259 spin_lock_irqsave(&dev_priv->channels.lock, flags);
260 chan = nouveau_channel_get_unlocked(dev_priv->channels.ptr[id]);
261 spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
264 return ERR_PTR(-EINVAL);
266 if (unlikely(file_priv && chan->file_priv != file_priv)) {
267 nouveau_channel_put_unlocked(&chan);
268 return ERR_PTR(-EINVAL);
271 mutex_lock(&chan->mutex);
276 nouveau_channel_put_unlocked(struct nouveau_channel **pchan)
278 struct nouveau_channel *chan = *pchan;
279 struct drm_device *dev = chan->dev;
280 struct drm_nouveau_private *dev_priv = dev->dev_private;
281 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
282 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
283 struct nouveau_crypt_engine *pcrypt = &dev_priv->engine.crypt;
286 /* decrement the refcount, and we're done if there's still refs */
287 if (likely(!atomic_dec_and_test(&chan->users))) {
288 nouveau_channel_ref(NULL, pchan);
292 /* noone wants the channel anymore */
293 NV_DEBUG(dev, "freeing channel %d\n", chan->id);
294 nouveau_debugfs_channel_fini(chan);
296 /* give it chance to idle */
297 nouveau_channel_idle(chan);
299 /* ensure all outstanding fences are signaled. they should be if the
300 * above attempts at idling were OK, but if we failed this'll tell TTM
301 * we're done with the buffers.
303 nouveau_fence_channel_fini(chan);
305 /* boot it off the hardware */
306 pfifo->reassign(dev, false);
308 /* We want to give pgraph a chance to idle and get rid of all
309 * potential errors. We need to do this without the context
310 * switch lock held, otherwise the irq handler is unable to
313 if (pgraph->channel(dev) == chan)
314 nouveau_wait_for_idle(dev);
316 /* destroy the engine specific contexts */
317 pfifo->destroy_context(chan);
318 pgraph->destroy_context(chan);
319 if (pcrypt->destroy_context)
320 pcrypt->destroy_context(chan);
322 pfifo->reassign(dev, true);
324 /* aside from its resources, the channel should now be dead,
325 * remove it from the channel list
327 spin_lock_irqsave(&dev_priv->channels.lock, flags);
328 nouveau_channel_ref(NULL, &dev_priv->channels.ptr[chan->id]);
329 spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
331 /* destroy any resources the channel owned */
332 nouveau_gpuobj_ref(NULL, &chan->pushbuf);
333 if (chan->pushbuf_bo) {
334 nouveau_bo_unmap(chan->pushbuf_bo);
335 nouveau_bo_unpin(chan->pushbuf_bo);
336 nouveau_bo_ref(NULL, &chan->pushbuf_bo);
338 nouveau_gpuobj_channel_takedown(chan);
339 nouveau_notifier_takedown_channel(chan);
341 nouveau_channel_ref(NULL, pchan);
345 nouveau_channel_put(struct nouveau_channel **pchan)
347 mutex_unlock(&(*pchan)->mutex);
348 nouveau_channel_put_unlocked(pchan);
352 nouveau_channel_del(struct kref *ref)
354 struct nouveau_channel *chan =
355 container_of(ref, struct nouveau_channel, ref);
361 nouveau_channel_ref(struct nouveau_channel *chan,
362 struct nouveau_channel **pchan)
365 kref_get(&chan->ref);
368 kref_put(&(*pchan)->ref, nouveau_channel_del);
374 nouveau_channel_idle(struct nouveau_channel *chan)
376 struct drm_device *dev = chan->dev;
377 struct nouveau_fence *fence = NULL;
380 nouveau_fence_update(chan);
382 if (chan->fence.sequence != chan->fence.sequence_ack) {
383 ret = nouveau_fence_new(chan, &fence, true);
385 ret = nouveau_fence_wait(fence, false, false);
386 nouveau_fence_unref(&fence);
390 NV_ERROR(dev, "Failed to idle channel %d.\n", chan->id);
394 /* cleans up all the fifos from file_priv */
396 nouveau_channel_cleanup(struct drm_device *dev, struct drm_file *file_priv)
398 struct drm_nouveau_private *dev_priv = dev->dev_private;
399 struct nouveau_engine *engine = &dev_priv->engine;
400 struct nouveau_channel *chan;
403 NV_DEBUG(dev, "clearing FIFO enables from file_priv\n");
404 for (i = 0; i < engine->fifo.channels; i++) {
405 chan = nouveau_channel_get(dev, file_priv, i);
409 atomic_dec(&chan->users);
410 nouveau_channel_put(&chan);
415 /***********************************
416 * ioctls wrapping the functions
417 ***********************************/
420 nouveau_ioctl_fifo_alloc(struct drm_device *dev, void *data,
421 struct drm_file *file_priv)
423 struct drm_nouveau_private *dev_priv = dev->dev_private;
424 struct drm_nouveau_channel_alloc *init = data;
425 struct nouveau_channel *chan;
428 if (dev_priv->engine.graph.accel_blocked)
431 if (init->fb_ctxdma_handle == ~0 || init->tt_ctxdma_handle == ~0)
434 ret = nouveau_channel_alloc(dev, &chan, file_priv,
435 init->fb_ctxdma_handle,
436 init->tt_ctxdma_handle);
439 init->channel = chan->id;
441 if (chan->dma.ib_max)
442 init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM |
443 NOUVEAU_GEM_DOMAIN_GART;
444 else if (chan->pushbuf_bo->bo.mem.mem_type == TTM_PL_VRAM)
445 init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM;
447 init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_GART;
449 init->subchan[0].handle = NvM2MF;
450 if (dev_priv->card_type < NV_50)
451 init->subchan[0].grclass = 0x0039;
453 init->subchan[0].grclass = 0x5039;
454 init->subchan[1].handle = NvSw;
455 init->subchan[1].grclass = NV_SW;
456 init->nr_subchan = 2;
458 /* Named memory object area */
459 ret = drm_gem_handle_create(file_priv, chan->notifier_bo->gem,
460 &init->notifier_handle);
463 atomic_inc(&chan->users); /* userspace reference */
464 nouveau_channel_put(&chan);
469 nouveau_ioctl_fifo_free(struct drm_device *dev, void *data,
470 struct drm_file *file_priv)
472 struct drm_nouveau_channel_free *req = data;
473 struct nouveau_channel *chan;
475 chan = nouveau_channel_get(dev, file_priv, req->channel);
477 return PTR_ERR(chan);
479 atomic_dec(&chan->users);
480 nouveau_channel_put(&chan);
484 /***********************************
485 * finally, the ioctl table
486 ***********************************/
488 struct drm_ioctl_desc nouveau_ioctls[] = {
489 DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_ioctl_getparam, DRM_UNLOCKED|DRM_AUTH),
490 DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, nouveau_ioctl_setparam, DRM_UNLOCKED|DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
491 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_ioctl_fifo_alloc, DRM_UNLOCKED|DRM_AUTH),
492 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_ioctl_fifo_free, DRM_UNLOCKED|DRM_AUTH),
493 DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_ioctl_grobj_alloc, DRM_UNLOCKED|DRM_AUTH),
494 DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_ioctl_notifier_alloc, DRM_UNLOCKED|DRM_AUTH),
495 DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_ioctl_gpuobj_free, DRM_UNLOCKED|DRM_AUTH),
496 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_UNLOCKED|DRM_AUTH),
497 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_UNLOCKED|DRM_AUTH),
498 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_UNLOCKED|DRM_AUTH),
499 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_UNLOCKED|DRM_AUTH),
500 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_UNLOCKED|DRM_AUTH),
503 int nouveau_max_ioctl = DRM_ARRAY_SIZE(nouveau_ioctls);