2 * Copyright 2005-2006 Stephane Marchesin
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
27 #include "nouveau_drv.h"
28 #include "nouveau_drm.h"
29 #include "nouveau_dma.h"
30 #include "nouveau_ramht.h"
31 #include "nouveau_software.h"
34 nouveau_channel_pushbuf_init(struct nouveau_channel *chan)
36 u32 mem = nouveau_vram_pushbuf ? TTM_PL_FLAG_VRAM : TTM_PL_FLAG_TT;
37 struct drm_device *dev = chan->dev;
38 struct drm_nouveau_private *dev_priv = dev->dev_private;
41 /* allocate buffer object */
42 ret = nouveau_bo_new(dev, 65536, 0, mem, 0, 0, NULL, &chan->pushbuf_bo);
46 ret = nouveau_bo_pin(chan->pushbuf_bo, mem);
50 ret = nouveau_bo_map(chan->pushbuf_bo);
54 /* create DMA object covering the entire memtype where the push
55 * buffer resides, userspace can submit its own push buffers from
56 * anywhere within the same memtype.
58 chan->pushbuf_base = chan->pushbuf_bo->bo.offset;
59 if (dev_priv->card_type >= NV_50) {
60 ret = nouveau_bo_vma_add(chan->pushbuf_bo, chan->vm,
65 if (dev_priv->card_type < NV_C0) {
66 ret = nouveau_gpuobj_dma_new(chan,
67 NV_CLASS_DMA_IN_MEMORY, 0,
73 chan->pushbuf_base = chan->pushbuf_vma.offset;
75 if (chan->pushbuf_bo->bo.mem.mem_type == TTM_PL_TT) {
76 ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, 0,
77 dev_priv->gart_info.aper_size,
82 if (dev_priv->card_type != NV_04) {
83 ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, 0,
84 dev_priv->fb_available_size,
89 /* NV04 cmdbuf hack, from original ddx.. not sure of it's
90 * exact reason for existing :) PCI access to cmdbuf in
93 ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
94 pci_resource_start(dev->pdev, 1),
95 dev_priv->fb_available_size,
103 NV_ERROR(dev, "error initialising pushbuf: %d\n", ret);
104 nouveau_bo_vma_del(chan->pushbuf_bo, &chan->pushbuf_vma);
105 nouveau_gpuobj_ref(NULL, &chan->pushbuf);
106 if (chan->pushbuf_bo) {
107 nouveau_bo_unmap(chan->pushbuf_bo);
108 nouveau_bo_ref(NULL, &chan->pushbuf_bo);
115 /* allocates and initializes a fifo for user space consumption */
117 nouveau_channel_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret,
118 struct drm_file *file_priv,
119 uint32_t vram_handle, uint32_t gart_handle)
121 struct drm_nouveau_private *dev_priv = dev->dev_private;
122 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
123 struct nouveau_fpriv *fpriv = nouveau_fpriv(file_priv);
124 struct nouveau_channel *chan;
128 /* allocate and lock channel structure */
129 chan = kzalloc(sizeof(*chan), GFP_KERNEL);
133 chan->file_priv = file_priv;
134 chan->vram_handle = vram_handle;
135 chan->gart_handle = gart_handle;
137 kref_init(&chan->ref);
138 atomic_set(&chan->users, 1);
139 mutex_init(&chan->mutex);
140 mutex_lock(&chan->mutex);
142 /* allocate hw channel id */
143 spin_lock_irqsave(&dev_priv->channels.lock, flags);
144 for (chan->id = 0; chan->id < pfifo->channels; chan->id++) {
145 if (!dev_priv->channels.ptr[chan->id]) {
146 nouveau_channel_ref(chan, &dev_priv->channels.ptr[chan->id]);
150 spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
152 if (chan->id == pfifo->channels) {
153 mutex_unlock(&chan->mutex);
158 NV_DEBUG(dev, "initialising channel %d\n", chan->id);
159 INIT_LIST_HEAD(&chan->fence.pending);
160 spin_lock_init(&chan->fence.lock);
162 /* setup channel's memory and vm */
163 ret = nouveau_gpuobj_channel_init(chan, vram_handle, gart_handle);
165 NV_ERROR(dev, "gpuobj %d\n", ret);
166 nouveau_channel_put(&chan);
170 /* Allocate space for per-channel fixed notifier memory */
171 ret = nouveau_notifier_init_channel(chan);
173 NV_ERROR(dev, "ntfy %d\n", ret);
174 nouveau_channel_put(&chan);
178 /* Allocate DMA push buffer */
179 ret = nouveau_channel_pushbuf_init(chan);
181 NV_ERROR(dev, "pushbuf %d\n", ret);
182 nouveau_channel_put(&chan);
186 nouveau_dma_init(chan);
187 chan->user_put = 0x40;
188 chan->user_get = 0x44;
189 if (dev_priv->card_type >= NV_50)
190 chan->user_get_hi = 0x60;
192 /* disable the fifo caches */
193 pfifo->reassign(dev, false);
195 /* Construct initial RAMFC for new channel */
196 ret = pfifo->create_context(chan);
198 nouveau_channel_put(&chan);
202 pfifo->reassign(dev, true);
204 /* Insert NOPs for NOUVEAU_DMA_SKIPS */
205 ret = RING_SPACE(chan, NOUVEAU_DMA_SKIPS);
207 nouveau_channel_put(&chan);
211 for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
212 OUT_RING (chan, 0x00000000);
215 ret = nouveau_gpuobj_gr_new(chan, NvSw, nouveau_software_class(dev));
217 nouveau_channel_put(&chan);
221 ret = nouveau_fence_channel_init(chan);
223 nouveau_channel_put(&chan);
227 nouveau_debugfs_channel_init(chan);
229 NV_DEBUG(dev, "channel %d initialised\n", chan->id);
231 spin_lock(&fpriv->lock);
232 list_add(&chan->list, &fpriv->channels);
233 spin_unlock(&fpriv->lock);
239 struct nouveau_channel *
240 nouveau_channel_get_unlocked(struct nouveau_channel *ref)
242 struct nouveau_channel *chan = NULL;
244 if (likely(ref && atomic_inc_not_zero(&ref->users)))
245 nouveau_channel_ref(ref, &chan);
250 struct nouveau_channel *
251 nouveau_channel_get(struct drm_file *file_priv, int id)
253 struct nouveau_fpriv *fpriv = nouveau_fpriv(file_priv);
254 struct nouveau_channel *chan;
256 spin_lock(&fpriv->lock);
257 list_for_each_entry(chan, &fpriv->channels, list) {
258 if (chan->id == id) {
259 chan = nouveau_channel_get_unlocked(chan);
260 spin_unlock(&fpriv->lock);
261 mutex_lock(&chan->mutex);
265 spin_unlock(&fpriv->lock);
267 return ERR_PTR(-EINVAL);
271 nouveau_channel_put_unlocked(struct nouveau_channel **pchan)
273 struct nouveau_channel *chan = *pchan;
274 struct drm_device *dev = chan->dev;
275 struct drm_nouveau_private *dev_priv = dev->dev_private;
276 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
280 /* decrement the refcount, and we're done if there's still refs */
281 if (likely(!atomic_dec_and_test(&chan->users))) {
282 nouveau_channel_ref(NULL, pchan);
286 /* no one wants the channel anymore */
287 NV_DEBUG(dev, "freeing channel %d\n", chan->id);
288 nouveau_debugfs_channel_fini(chan);
290 /* give it chance to idle */
291 nouveau_channel_idle(chan);
293 /* ensure all outstanding fences are signaled. they should be if the
294 * above attempts at idling were OK, but if we failed this'll tell TTM
295 * we're done with the buffers.
297 nouveau_fence_channel_fini(chan);
299 /* boot it off the hardware */
300 pfifo->reassign(dev, false);
302 /* destroy the engine specific contexts */
303 pfifo->destroy_context(chan);
304 for (i = 0; i < NVOBJ_ENGINE_NR; i++) {
306 dev_priv->eng[i]->context_del(chan, i);
309 pfifo->reassign(dev, true);
311 /* aside from its resources, the channel should now be dead,
312 * remove it from the channel list
314 spin_lock_irqsave(&dev_priv->channels.lock, flags);
315 nouveau_channel_ref(NULL, &dev_priv->channels.ptr[chan->id]);
316 spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
318 /* destroy any resources the channel owned */
319 nouveau_gpuobj_ref(NULL, &chan->pushbuf);
320 if (chan->pushbuf_bo) {
321 nouveau_bo_vma_del(chan->pushbuf_bo, &chan->pushbuf_vma);
322 nouveau_bo_unmap(chan->pushbuf_bo);
323 nouveau_bo_unpin(chan->pushbuf_bo);
324 nouveau_bo_ref(NULL, &chan->pushbuf_bo);
326 nouveau_ramht_ref(NULL, &chan->ramht, chan);
327 nouveau_notifier_takedown_channel(chan);
328 nouveau_gpuobj_channel_takedown(chan);
330 nouveau_channel_ref(NULL, pchan);
334 nouveau_channel_put(struct nouveau_channel **pchan)
336 mutex_unlock(&(*pchan)->mutex);
337 nouveau_channel_put_unlocked(pchan);
341 nouveau_channel_del(struct kref *ref)
343 struct nouveau_channel *chan =
344 container_of(ref, struct nouveau_channel, ref);
350 nouveau_channel_ref(struct nouveau_channel *chan,
351 struct nouveau_channel **pchan)
354 kref_get(&chan->ref);
357 kref_put(&(*pchan)->ref, nouveau_channel_del);
363 nouveau_channel_idle(struct nouveau_channel *chan)
365 struct drm_device *dev = chan->dev;
366 struct nouveau_fence *fence = NULL;
369 nouveau_fence_update(chan);
371 if (chan->fence.sequence != chan->fence.sequence_ack) {
372 ret = nouveau_fence_new(chan, &fence, true);
374 ret = nouveau_fence_wait(fence, false, false);
375 nouveau_fence_unref(&fence);
379 NV_ERROR(dev, "Failed to idle channel %d.\n", chan->id);
383 /* cleans up all the fifos from file_priv */
385 nouveau_channel_cleanup(struct drm_device *dev, struct drm_file *file_priv)
387 struct drm_nouveau_private *dev_priv = dev->dev_private;
388 struct nouveau_engine *engine = &dev_priv->engine;
389 struct nouveau_channel *chan;
392 NV_DEBUG(dev, "clearing FIFO enables from file_priv\n");
393 for (i = 0; i < engine->fifo.channels; i++) {
394 chan = nouveau_channel_get(file_priv, i);
398 list_del(&chan->list);
399 atomic_dec(&chan->users);
400 nouveau_channel_put(&chan);
405 /***********************************
406 * ioctls wrapping the functions
407 ***********************************/
410 nouveau_ioctl_fifo_alloc(struct drm_device *dev, void *data,
411 struct drm_file *file_priv)
413 struct drm_nouveau_private *dev_priv = dev->dev_private;
414 struct drm_nouveau_channel_alloc *init = data;
415 struct nouveau_channel *chan;
418 if (!dev_priv->eng[NVOBJ_ENGINE_GR])
421 if (init->fb_ctxdma_handle == ~0 || init->tt_ctxdma_handle == ~0)
424 ret = nouveau_channel_alloc(dev, &chan, file_priv,
425 init->fb_ctxdma_handle,
426 init->tt_ctxdma_handle);
429 init->channel = chan->id;
431 if (nouveau_vram_pushbuf == 0) {
432 if (chan->dma.ib_max)
433 init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM |
434 NOUVEAU_GEM_DOMAIN_GART;
435 else if (chan->pushbuf_bo->bo.mem.mem_type == TTM_PL_VRAM)
436 init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM;
438 init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_GART;
440 init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM;
443 if (dev_priv->card_type < NV_C0) {
444 init->subchan[0].handle = 0x00000000;
445 init->subchan[0].grclass = 0x0000;
446 init->subchan[1].handle = NvSw;
447 init->subchan[1].grclass = NV_SW;
448 init->nr_subchan = 2;
451 /* Named memory object area */
452 ret = drm_gem_handle_create(file_priv, chan->notifier_bo->gem,
453 &init->notifier_handle);
456 atomic_inc(&chan->users); /* userspace reference */
457 nouveau_channel_put(&chan);
462 nouveau_ioctl_fifo_free(struct drm_device *dev, void *data,
463 struct drm_file *file_priv)
465 struct drm_nouveau_channel_free *req = data;
466 struct nouveau_channel *chan;
468 chan = nouveau_channel_get(file_priv, req->channel);
470 return PTR_ERR(chan);
472 list_del(&chan->list);
473 atomic_dec(&chan->users);
474 nouveau_channel_put(&chan);
478 /***********************************
479 * finally, the ioctl table
480 ***********************************/
482 struct drm_ioctl_desc nouveau_ioctls[] = {
483 DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_ioctl_getparam, DRM_UNLOCKED|DRM_AUTH),
484 DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, nouveau_ioctl_setparam, DRM_UNLOCKED|DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
485 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_ioctl_fifo_alloc, DRM_UNLOCKED|DRM_AUTH),
486 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_ioctl_fifo_free, DRM_UNLOCKED|DRM_AUTH),
487 DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_ioctl_grobj_alloc, DRM_UNLOCKED|DRM_AUTH),
488 DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_ioctl_notifier_alloc, DRM_UNLOCKED|DRM_AUTH),
489 DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_ioctl_gpuobj_free, DRM_UNLOCKED|DRM_AUTH),
490 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_UNLOCKED|DRM_AUTH),
491 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_UNLOCKED|DRM_AUTH),
492 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_UNLOCKED|DRM_AUTH),
493 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_UNLOCKED|DRM_AUTH),
494 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_UNLOCKED|DRM_AUTH),
497 int nouveau_max_ioctl = DRM_ARRAY_SIZE(nouveau_ioctls);