2 * Copyright 2005-2006 Stephane Marchesin
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
27 #include "nouveau_drv.h"
28 #include "nouveau_drm.h"
29 #include "nouveau_dma.h"
32 nouveau_channel_pushbuf_ctxdma_init(struct nouveau_channel *chan)
34 struct drm_device *dev = chan->dev;
35 struct drm_nouveau_private *dev_priv = dev->dev_private;
36 struct nouveau_bo *pb = chan->pushbuf_bo;
37 struct nouveau_gpuobj *pushbuf = NULL;
40 if (dev_priv->card_type >= NV_50) {
41 ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, 0,
42 (1ULL << 40), NV_MEM_ACCESS_RO,
43 NV_MEM_TARGET_VM, &pushbuf);
44 chan->pushbuf_base = pb->bo.offset;
46 if (pb->bo.mem.mem_type == TTM_PL_TT) {
47 ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, 0,
48 dev_priv->gart_info.aper_size,
50 NV_MEM_TARGET_GART, &pushbuf);
51 chan->pushbuf_base = pb->bo.mem.start << PAGE_SHIFT;
53 if (dev_priv->card_type != NV_04) {
54 ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, 0,
55 dev_priv->fb_available_size,
57 NV_MEM_TARGET_VRAM, &pushbuf);
58 chan->pushbuf_base = pb->bo.mem.start << PAGE_SHIFT;
60 /* NV04 cmdbuf hack, from original ddx.. not sure of it's
61 * exact reason for existing :) PCI access to cmdbuf in
64 ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
65 pci_resource_start(dev->pdev, 1),
66 dev_priv->fb_available_size,
68 NV_MEM_TARGET_PCI, &pushbuf);
69 chan->pushbuf_base = pb->bo.mem.start << PAGE_SHIFT;
72 nouveau_gpuobj_ref(pushbuf, &chan->pushbuf);
73 nouveau_gpuobj_ref(NULL, &pushbuf);
77 static struct nouveau_bo *
78 nouveau_channel_user_pushbuf_alloc(struct drm_device *dev)
80 struct nouveau_bo *pushbuf = NULL;
83 if (nouveau_vram_pushbuf)
84 location = TTM_PL_FLAG_VRAM;
86 location = TTM_PL_FLAG_TT;
88 ret = nouveau_bo_new(dev, NULL, 65536, 0, location, 0, 0x0000, false,
91 NV_ERROR(dev, "error allocating DMA push buffer: %d\n", ret);
95 ret = nouveau_bo_pin(pushbuf, location);
97 NV_ERROR(dev, "error pinning DMA push buffer: %d\n", ret);
98 nouveau_bo_ref(NULL, &pushbuf);
105 /* allocates and initializes a fifo for user space consumption */
107 nouveau_channel_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret,
108 struct drm_file *file_priv,
109 uint32_t vram_handle, uint32_t gart_handle)
111 struct drm_nouveau_private *dev_priv = dev->dev_private;
112 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
113 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
114 struct nouveau_channel *chan;
118 /* allocate and lock channel structure */
119 chan = kzalloc(sizeof(*chan), GFP_KERNEL);
123 chan->file_priv = file_priv;
124 chan->vram_handle = vram_handle;
125 chan->gart_handle = gart_handle;
127 kref_init(&chan->ref);
128 atomic_set(&chan->users, 1);
129 mutex_init(&chan->mutex);
130 mutex_lock(&chan->mutex);
132 /* allocate hw channel id */
133 spin_lock_irqsave(&dev_priv->channels.lock, flags);
134 for (chan->id = 0; chan->id < pfifo->channels; chan->id++) {
135 if (!dev_priv->channels.ptr[chan->id]) {
136 nouveau_channel_ref(chan, &dev_priv->channels.ptr[chan->id]);
140 spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
142 if (chan->id == pfifo->channels) {
143 mutex_unlock(&chan->mutex);
148 NV_DEBUG(dev, "initialising channel %d\n", chan->id);
149 INIT_LIST_HEAD(&chan->nvsw.vbl_wait);
150 INIT_LIST_HEAD(&chan->nvsw.flip);
151 INIT_LIST_HEAD(&chan->fence.pending);
153 /* Allocate DMA push buffer */
154 chan->pushbuf_bo = nouveau_channel_user_pushbuf_alloc(dev);
155 if (!chan->pushbuf_bo) {
157 NV_ERROR(dev, "pushbuf %d\n", ret);
158 nouveau_channel_put(&chan);
162 nouveau_dma_pre_init(chan);
163 chan->user_put = 0x40;
164 chan->user_get = 0x44;
166 /* Allocate space for per-channel fixed notifier memory */
167 ret = nouveau_notifier_init_channel(chan);
169 NV_ERROR(dev, "ntfy %d\n", ret);
170 nouveau_channel_put(&chan);
174 /* Setup channel's default objects */
175 ret = nouveau_gpuobj_channel_init(chan, vram_handle, gart_handle);
177 NV_ERROR(dev, "gpuobj %d\n", ret);
178 nouveau_channel_put(&chan);
182 /* Create a dma object for the push buffer */
183 ret = nouveau_channel_pushbuf_ctxdma_init(chan);
185 NV_ERROR(dev, "pbctxdma %d\n", ret);
186 nouveau_channel_put(&chan);
190 /* disable the fifo caches */
191 pfifo->reassign(dev, false);
193 /* Create a graphics context for new channel */
194 if (dev_priv->card_type < NV_50) {
195 ret = pgraph->create_context(chan);
197 nouveau_channel_put(&chan);
202 /* Construct inital RAMFC for new channel */
203 ret = pfifo->create_context(chan);
205 nouveau_channel_put(&chan);
209 pfifo->reassign(dev, true);
211 ret = nouveau_dma_init(chan);
213 ret = nouveau_fence_channel_init(chan);
215 nouveau_channel_put(&chan);
219 nouveau_debugfs_channel_init(chan);
221 NV_DEBUG(dev, "channel %d initialised\n", chan->id);
226 struct nouveau_channel *
227 nouveau_channel_get_unlocked(struct nouveau_channel *ref)
229 struct nouveau_channel *chan = NULL;
231 if (likely(ref && atomic_inc_not_zero(&ref->users)))
232 nouveau_channel_ref(ref, &chan);
237 struct nouveau_channel *
238 nouveau_channel_get(struct drm_device *dev, struct drm_file *file_priv, int id)
240 struct drm_nouveau_private *dev_priv = dev->dev_private;
241 struct nouveau_channel *chan;
244 spin_lock_irqsave(&dev_priv->channels.lock, flags);
245 chan = nouveau_channel_get_unlocked(dev_priv->channels.ptr[id]);
246 spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
249 return ERR_PTR(-EINVAL);
251 if (unlikely(file_priv && chan->file_priv != file_priv)) {
252 nouveau_channel_put_unlocked(&chan);
253 return ERR_PTR(-EINVAL);
256 mutex_lock(&chan->mutex);
261 nouveau_channel_put_unlocked(struct nouveau_channel **pchan)
263 struct nouveau_channel *chan = *pchan;
264 struct drm_device *dev = chan->dev;
265 struct drm_nouveau_private *dev_priv = dev->dev_private;
266 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
267 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
268 struct nouveau_crypt_engine *pcrypt = &dev_priv->engine.crypt;
271 /* decrement the refcount, and we're done if there's still refs */
272 if (likely(!atomic_dec_and_test(&chan->users))) {
273 nouveau_channel_ref(NULL, pchan);
277 /* noone wants the channel anymore */
278 NV_DEBUG(dev, "freeing channel %d\n", chan->id);
279 nouveau_debugfs_channel_fini(chan);
281 /* give it chance to idle */
282 nouveau_channel_idle(chan);
284 /* ensure all outstanding fences are signaled. they should be if the
285 * above attempts at idling were OK, but if we failed this'll tell TTM
286 * we're done with the buffers.
288 nouveau_fence_channel_fini(chan);
290 /* boot it off the hardware */
291 pfifo->reassign(dev, false);
293 /* We want to give pgraph a chance to idle and get rid of all
294 * potential errors. We need to do this without the context
295 * switch lock held, otherwise the irq handler is unable to
298 if (pgraph->channel(dev) == chan)
299 nouveau_wait_for_idle(dev);
301 /* destroy the engine specific contexts */
302 pfifo->destroy_context(chan);
303 pgraph->destroy_context(chan);
304 if (pcrypt->destroy_context)
305 pcrypt->destroy_context(chan);
307 pfifo->reassign(dev, true);
309 /* aside from its resources, the channel should now be dead,
310 * remove it from the channel list
312 spin_lock_irqsave(&dev_priv->channels.lock, flags);
313 nouveau_channel_ref(NULL, &dev_priv->channels.ptr[chan->id]);
314 spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
316 /* destroy any resources the channel owned */
317 nouveau_gpuobj_ref(NULL, &chan->pushbuf);
318 if (chan->pushbuf_bo) {
319 nouveau_bo_unmap(chan->pushbuf_bo);
320 nouveau_bo_unpin(chan->pushbuf_bo);
321 nouveau_bo_ref(NULL, &chan->pushbuf_bo);
323 nouveau_gpuobj_channel_takedown(chan);
324 nouveau_notifier_takedown_channel(chan);
326 nouveau_channel_ref(NULL, pchan);
330 nouveau_channel_put(struct nouveau_channel **pchan)
332 mutex_unlock(&(*pchan)->mutex);
333 nouveau_channel_put_unlocked(pchan);
337 nouveau_channel_del(struct kref *ref)
339 struct nouveau_channel *chan =
340 container_of(ref, struct nouveau_channel, ref);
346 nouveau_channel_ref(struct nouveau_channel *chan,
347 struct nouveau_channel **pchan)
350 kref_get(&chan->ref);
353 kref_put(&(*pchan)->ref, nouveau_channel_del);
359 nouveau_channel_idle(struct nouveau_channel *chan)
361 struct drm_device *dev = chan->dev;
362 struct nouveau_fence *fence = NULL;
365 nouveau_fence_update(chan);
367 if (chan->fence.sequence != chan->fence.sequence_ack) {
368 ret = nouveau_fence_new(chan, &fence, true);
370 ret = nouveau_fence_wait(fence, false, false);
371 nouveau_fence_unref(&fence);
375 NV_ERROR(dev, "Failed to idle channel %d.\n", chan->id);
379 /* cleans up all the fifos from file_priv */
381 nouveau_channel_cleanup(struct drm_device *dev, struct drm_file *file_priv)
383 struct drm_nouveau_private *dev_priv = dev->dev_private;
384 struct nouveau_engine *engine = &dev_priv->engine;
385 struct nouveau_channel *chan;
388 NV_DEBUG(dev, "clearing FIFO enables from file_priv\n");
389 for (i = 0; i < engine->fifo.channels; i++) {
390 chan = nouveau_channel_get(dev, file_priv, i);
394 atomic_dec(&chan->users);
395 nouveau_channel_put(&chan);
400 /***********************************
401 * ioctls wrapping the functions
402 ***********************************/
405 nouveau_ioctl_fifo_alloc(struct drm_device *dev, void *data,
406 struct drm_file *file_priv)
408 struct drm_nouveau_private *dev_priv = dev->dev_private;
409 struct drm_nouveau_channel_alloc *init = data;
410 struct nouveau_channel *chan;
413 if (dev_priv->engine.graph.accel_blocked)
416 if (init->fb_ctxdma_handle == ~0 || init->tt_ctxdma_handle == ~0)
419 ret = nouveau_channel_alloc(dev, &chan, file_priv,
420 init->fb_ctxdma_handle,
421 init->tt_ctxdma_handle);
424 init->channel = chan->id;
426 if (chan->dma.ib_max)
427 init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM |
428 NOUVEAU_GEM_DOMAIN_GART;
429 else if (chan->pushbuf_bo->bo.mem.mem_type == TTM_PL_VRAM)
430 init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM;
432 init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_GART;
434 init->subchan[0].handle = NvM2MF;
435 if (dev_priv->card_type < NV_50)
436 init->subchan[0].grclass = 0x0039;
438 init->subchan[0].grclass = 0x5039;
439 init->subchan[1].handle = NvSw;
440 init->subchan[1].grclass = NV_SW;
441 init->nr_subchan = 2;
443 /* Named memory object area */
444 ret = drm_gem_handle_create(file_priv, chan->notifier_bo->gem,
445 &init->notifier_handle);
448 atomic_inc(&chan->users); /* userspace reference */
449 nouveau_channel_put(&chan);
454 nouveau_ioctl_fifo_free(struct drm_device *dev, void *data,
455 struct drm_file *file_priv)
457 struct drm_nouveau_channel_free *req = data;
458 struct nouveau_channel *chan;
460 chan = nouveau_channel_get(dev, file_priv, req->channel);
462 return PTR_ERR(chan);
464 atomic_dec(&chan->users);
465 nouveau_channel_put(&chan);
469 /***********************************
470 * finally, the ioctl table
471 ***********************************/
473 struct drm_ioctl_desc nouveau_ioctls[] = {
474 DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_ioctl_getparam, DRM_UNLOCKED|DRM_AUTH),
475 DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, nouveau_ioctl_setparam, DRM_UNLOCKED|DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
476 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_ioctl_fifo_alloc, DRM_UNLOCKED|DRM_AUTH),
477 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_ioctl_fifo_free, DRM_UNLOCKED|DRM_AUTH),
478 DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_ioctl_grobj_alloc, DRM_UNLOCKED|DRM_AUTH),
479 DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_ioctl_notifier_alloc, DRM_UNLOCKED|DRM_AUTH),
480 DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_ioctl_gpuobj_free, DRM_UNLOCKED|DRM_AUTH),
481 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_UNLOCKED|DRM_AUTH),
482 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_UNLOCKED|DRM_AUTH),
483 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_UNLOCKED|DRM_AUTH),
484 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_UNLOCKED|DRM_AUTH),
485 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_UNLOCKED|DRM_AUTH),
488 int nouveau_max_ioctl = DRM_ARRAY_SIZE(nouveau_ioctls);