2 * Copyright 2005-2006 Stephane Marchesin
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
27 #include "nouveau_drv.h"
28 #include "nouveau_drm.h"
29 #include "nouveau_dma.h"
30 #include "nouveau_ramht.h"
31 #include "nouveau_fence.h"
32 #include "nouveau_software.h"
35 nouveau_channel_pushbuf_init(struct nouveau_channel *chan)
37 u32 mem = nouveau_vram_pushbuf ? TTM_PL_FLAG_VRAM : TTM_PL_FLAG_TT;
38 struct drm_device *dev = chan->dev;
39 struct drm_nouveau_private *dev_priv = dev->dev_private;
42 /* allocate buffer object */
43 ret = nouveau_bo_new(dev, 65536, 0, mem, 0, 0, NULL, &chan->pushbuf_bo);
47 ret = nouveau_bo_pin(chan->pushbuf_bo, mem);
51 ret = nouveau_bo_map(chan->pushbuf_bo);
55 /* create DMA object covering the entire memtype where the push
56 * buffer resides, userspace can submit its own push buffers from
57 * anywhere within the same memtype.
59 chan->pushbuf_base = chan->pushbuf_bo->bo.offset;
60 if (dev_priv->card_type >= NV_50) {
61 ret = nouveau_bo_vma_add(chan->pushbuf_bo, chan->vm,
66 if (dev_priv->card_type < NV_C0) {
67 ret = nouveau_gpuobj_dma_new(chan,
68 NV_CLASS_DMA_IN_MEMORY, 0,
74 chan->pushbuf_base = chan->pushbuf_vma.offset;
76 if (chan->pushbuf_bo->bo.mem.mem_type == TTM_PL_TT) {
77 ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, 0,
78 dev_priv->gart_info.aper_size,
83 if (dev_priv->card_type != NV_04) {
84 ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, 0,
85 dev_priv->fb_available_size,
90 /* NV04 cmdbuf hack, from original ddx.. not sure of it's
91 * exact reason for existing :) PCI access to cmdbuf in
94 ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
95 pci_resource_start(dev->pdev, 1),
96 dev_priv->fb_available_size,
104 NV_ERROR(dev, "error initialising pushbuf: %d\n", ret);
105 nouveau_bo_vma_del(chan->pushbuf_bo, &chan->pushbuf_vma);
106 nouveau_gpuobj_ref(NULL, &chan->pushbuf);
107 if (chan->pushbuf_bo) {
108 nouveau_bo_unmap(chan->pushbuf_bo);
109 nouveau_bo_ref(NULL, &chan->pushbuf_bo);
116 /* allocates and initializes a fifo for user space consumption */
118 nouveau_channel_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret,
119 struct drm_file *file_priv,
120 uint32_t vram_handle, uint32_t gart_handle)
122 struct nouveau_exec_engine *fence = nv_engine(dev, NVOBJ_ENGINE_FENCE);
123 struct drm_nouveau_private *dev_priv = dev->dev_private;
124 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
125 struct nouveau_fpriv *fpriv = nouveau_fpriv(file_priv);
126 struct nouveau_channel *chan;
130 /* allocate and lock channel structure */
131 chan = kzalloc(sizeof(*chan), GFP_KERNEL);
135 chan->file_priv = file_priv;
136 chan->vram_handle = vram_handle;
137 chan->gart_handle = gart_handle;
139 kref_init(&chan->ref);
140 atomic_set(&chan->users, 1);
141 mutex_init(&chan->mutex);
142 mutex_lock(&chan->mutex);
144 /* allocate hw channel id */
145 spin_lock_irqsave(&dev_priv->channels.lock, flags);
146 for (chan->id = 0; chan->id < pfifo->channels; chan->id++) {
147 if (!dev_priv->channels.ptr[chan->id]) {
148 nouveau_channel_ref(chan, &dev_priv->channels.ptr[chan->id]);
152 spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
154 if (chan->id == pfifo->channels) {
155 mutex_unlock(&chan->mutex);
160 NV_DEBUG(dev, "initialising channel %d\n", chan->id);
162 /* setup channel's memory and vm */
163 ret = nouveau_gpuobj_channel_init(chan, vram_handle, gart_handle);
165 NV_ERROR(dev, "gpuobj %d\n", ret);
166 nouveau_channel_put(&chan);
170 /* Allocate space for per-channel fixed notifier memory */
171 ret = nouveau_notifier_init_channel(chan);
173 NV_ERROR(dev, "ntfy %d\n", ret);
174 nouveau_channel_put(&chan);
178 /* Allocate DMA push buffer */
179 ret = nouveau_channel_pushbuf_init(chan);
181 NV_ERROR(dev, "pushbuf %d\n", ret);
182 nouveau_channel_put(&chan);
186 nouveau_dma_init(chan);
187 chan->user_put = 0x40;
188 chan->user_get = 0x44;
189 if (dev_priv->card_type >= NV_50)
190 chan->user_get_hi = 0x60;
192 /* disable the fifo caches */
193 if (dev_priv->card_type < NV_C0)
194 nv_wr32(dev, NV03_PFIFO_CACHES, 0);
196 /* Construct initial RAMFC for new channel */
197 ret = pfifo->create_context(chan);
199 nouveau_channel_put(&chan);
203 if (dev_priv->card_type < NV_C0)
204 nv_wr32(dev, NV03_PFIFO_CACHES, 1);
206 /* Insert NOPs for NOUVEAU_DMA_SKIPS */
207 ret = RING_SPACE(chan, NOUVEAU_DMA_SKIPS);
209 nouveau_channel_put(&chan);
213 for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
214 OUT_RING (chan, 0x00000000);
216 ret = nouveau_gpuobj_gr_new(chan, NvSw, nouveau_software_class(dev));
218 nouveau_channel_put(&chan);
222 if (dev_priv->card_type < NV_C0) {
223 ret = RING_SPACE(chan, 2);
225 nouveau_channel_put(&chan);
229 BEGIN_NV04(chan, NvSubSw, NV01_SUBCHAN_OBJECT, 1);
230 OUT_RING (chan, NvSw);
236 ret = fence->context_new(chan, NVOBJ_ENGINE_FENCE);
238 nouveau_channel_put(&chan);
242 nouveau_debugfs_channel_init(chan);
244 NV_DEBUG(dev, "channel %d initialised\n", chan->id);
246 spin_lock(&fpriv->lock);
247 list_add(&chan->list, &fpriv->channels);
248 spin_unlock(&fpriv->lock);
254 struct nouveau_channel *
255 nouveau_channel_get_unlocked(struct nouveau_channel *ref)
257 struct nouveau_channel *chan = NULL;
259 if (likely(ref && atomic_inc_not_zero(&ref->users)))
260 nouveau_channel_ref(ref, &chan);
265 struct nouveau_channel *
266 nouveau_channel_get(struct drm_file *file_priv, int id)
268 struct nouveau_fpriv *fpriv = nouveau_fpriv(file_priv);
269 struct nouveau_channel *chan;
271 spin_lock(&fpriv->lock);
272 list_for_each_entry(chan, &fpriv->channels, list) {
273 if (chan->id == id) {
274 chan = nouveau_channel_get_unlocked(chan);
275 spin_unlock(&fpriv->lock);
276 mutex_lock(&chan->mutex);
280 spin_unlock(&fpriv->lock);
282 return ERR_PTR(-EINVAL);
286 nouveau_channel_put_unlocked(struct nouveau_channel **pchan)
288 struct nouveau_channel *chan = *pchan;
289 struct drm_device *dev = chan->dev;
290 struct drm_nouveau_private *dev_priv = dev->dev_private;
291 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
295 /* decrement the refcount, and we're done if there's still refs */
296 if (likely(!atomic_dec_and_test(&chan->users))) {
297 nouveau_channel_ref(NULL, pchan);
301 /* no one wants the channel anymore */
302 NV_DEBUG(dev, "freeing channel %d\n", chan->id);
303 nouveau_debugfs_channel_fini(chan);
305 /* give it chance to idle */
306 nouveau_channel_idle(chan);
308 /* boot it off the hardware */
309 if (dev_priv->card_type < NV_C0)
310 nv_wr32(dev, NV03_PFIFO_CACHES, 0);
312 /* destroy the engine specific contexts */
313 for (i = NVOBJ_ENGINE_NR - 1; i >= 0; i--) {
315 dev_priv->eng[i]->context_del(chan, i);
316 /*XXX: clean this up later, order is important */
317 if (i == NVOBJ_ENGINE_FENCE)
318 pfifo->destroy_context(chan);
321 if (dev_priv->card_type < NV_C0)
322 nv_wr32(dev, NV03_PFIFO_CACHES, 1);
324 /* aside from its resources, the channel should now be dead,
325 * remove it from the channel list
327 spin_lock_irqsave(&dev_priv->channels.lock, flags);
328 nouveau_channel_ref(NULL, &dev_priv->channels.ptr[chan->id]);
329 spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
331 /* destroy any resources the channel owned */
332 nouveau_gpuobj_ref(NULL, &chan->pushbuf);
333 if (chan->pushbuf_bo) {
334 nouveau_bo_vma_del(chan->pushbuf_bo, &chan->pushbuf_vma);
335 nouveau_bo_unmap(chan->pushbuf_bo);
336 nouveau_bo_unpin(chan->pushbuf_bo);
337 nouveau_bo_ref(NULL, &chan->pushbuf_bo);
339 nouveau_ramht_ref(NULL, &chan->ramht, chan);
340 nouveau_notifier_takedown_channel(chan);
341 nouveau_gpuobj_channel_takedown(chan);
343 nouveau_channel_ref(NULL, pchan);
347 nouveau_channel_put(struct nouveau_channel **pchan)
349 mutex_unlock(&(*pchan)->mutex);
350 nouveau_channel_put_unlocked(pchan);
354 nouveau_channel_del(struct kref *ref)
356 struct nouveau_channel *chan =
357 container_of(ref, struct nouveau_channel, ref);
363 nouveau_channel_ref(struct nouveau_channel *chan,
364 struct nouveau_channel **pchan)
367 kref_get(&chan->ref);
370 kref_put(&(*pchan)->ref, nouveau_channel_del);
376 nouveau_channel_idle(struct nouveau_channel *chan)
378 struct drm_device *dev = chan->dev;
379 struct nouveau_fence *fence = NULL;
382 ret = nouveau_fence_new(chan, &fence);
384 ret = nouveau_fence_wait(fence, false, false);
385 nouveau_fence_unref(&fence);
389 NV_ERROR(dev, "Failed to idle channel %d.\n", chan->id);
392 /* cleans up all the fifos from file_priv */
394 nouveau_channel_cleanup(struct drm_device *dev, struct drm_file *file_priv)
396 struct drm_nouveau_private *dev_priv = dev->dev_private;
397 struct nouveau_engine *engine = &dev_priv->engine;
398 struct nouveau_channel *chan;
401 NV_DEBUG(dev, "clearing FIFO enables from file_priv\n");
402 for (i = 0; i < engine->fifo.channels; i++) {
403 chan = nouveau_channel_get(file_priv, i);
407 list_del(&chan->list);
408 atomic_dec(&chan->users);
409 nouveau_channel_put(&chan);
414 /***********************************
415 * ioctls wrapping the functions
416 ***********************************/
419 nouveau_ioctl_fifo_alloc(struct drm_device *dev, void *data,
420 struct drm_file *file_priv)
422 struct drm_nouveau_private *dev_priv = dev->dev_private;
423 struct drm_nouveau_channel_alloc *init = data;
424 struct nouveau_channel *chan;
427 if (!dev_priv->eng[NVOBJ_ENGINE_GR])
430 if (init->fb_ctxdma_handle == ~0 || init->tt_ctxdma_handle == ~0)
433 ret = nouveau_channel_alloc(dev, &chan, file_priv,
434 init->fb_ctxdma_handle,
435 init->tt_ctxdma_handle);
438 init->channel = chan->id;
440 if (nouveau_vram_pushbuf == 0) {
441 if (chan->dma.ib_max)
442 init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM |
443 NOUVEAU_GEM_DOMAIN_GART;
444 else if (chan->pushbuf_bo->bo.mem.mem_type == TTM_PL_VRAM)
445 init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM;
447 init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_GART;
449 init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM;
452 if (dev_priv->card_type < NV_C0) {
453 init->subchan[0].handle = 0x00000000;
454 init->subchan[0].grclass = 0x0000;
455 init->subchan[1].handle = NvSw;
456 init->subchan[1].grclass = NV_SW;
457 init->nr_subchan = 2;
460 /* Named memory object area */
461 ret = drm_gem_handle_create(file_priv, chan->notifier_bo->gem,
462 &init->notifier_handle);
465 atomic_inc(&chan->users); /* userspace reference */
466 nouveau_channel_put(&chan);
471 nouveau_ioctl_fifo_free(struct drm_device *dev, void *data,
472 struct drm_file *file_priv)
474 struct drm_nouveau_channel_free *req = data;
475 struct nouveau_channel *chan;
477 chan = nouveau_channel_get(file_priv, req->channel);
479 return PTR_ERR(chan);
481 list_del(&chan->list);
482 atomic_dec(&chan->users);
483 nouveau_channel_put(&chan);
487 /***********************************
488 * finally, the ioctl table
489 ***********************************/
491 struct drm_ioctl_desc nouveau_ioctls[] = {
492 DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_ioctl_getparam, DRM_UNLOCKED|DRM_AUTH),
493 DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, nouveau_ioctl_setparam, DRM_UNLOCKED|DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
494 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_ioctl_fifo_alloc, DRM_UNLOCKED|DRM_AUTH),
495 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_ioctl_fifo_free, DRM_UNLOCKED|DRM_AUTH),
496 DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_ioctl_grobj_alloc, DRM_UNLOCKED|DRM_AUTH),
497 DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_ioctl_notifier_alloc, DRM_UNLOCKED|DRM_AUTH),
498 DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_ioctl_gpuobj_free, DRM_UNLOCKED|DRM_AUTH),
499 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_UNLOCKED|DRM_AUTH),
500 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_UNLOCKED|DRM_AUTH),
501 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_UNLOCKED|DRM_AUTH),
502 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_UNLOCKED|DRM_AUTH),
503 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_UNLOCKED|DRM_AUTH),
506 int nouveau_max_ioctl = DRM_ARRAY_SIZE(nouveau_ioctls);