2 * Copyright 2005-2006 Stephane Marchesin
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
27 #include "nouveau_drv.h"
28 #include "nouveau_drm.h"
29 #include "nouveau_dma.h"
30 #include "nouveau_ramht.h"
31 #include "nouveau_fence.h"
32 #include "nouveau_software.h"
35 nouveau_channel_pushbuf_init(struct nouveau_channel *chan)
37 u32 mem = nouveau_vram_pushbuf ? TTM_PL_FLAG_VRAM : TTM_PL_FLAG_TT;
38 struct drm_device *dev = chan->dev;
39 struct drm_nouveau_private *dev_priv = dev->dev_private;
42 /* allocate buffer object */
43 ret = nouveau_bo_new(dev, 65536, 0, mem, 0, 0, NULL, &chan->pushbuf_bo);
47 ret = nouveau_bo_pin(chan->pushbuf_bo, mem);
51 ret = nouveau_bo_map(chan->pushbuf_bo);
55 /* create DMA object covering the entire memtype where the push
56 * buffer resides, userspace can submit its own push buffers from
57 * anywhere within the same memtype.
59 chan->pushbuf_base = chan->pushbuf_bo->bo.offset;
60 if (dev_priv->card_type >= NV_50) {
61 ret = nouveau_bo_vma_add(chan->pushbuf_bo, chan->vm,
66 if (dev_priv->card_type < NV_C0) {
67 ret = nouveau_gpuobj_dma_new(chan,
68 NV_CLASS_DMA_IN_MEMORY, 0,
74 chan->pushbuf_base = chan->pushbuf_vma.offset;
76 if (chan->pushbuf_bo->bo.mem.mem_type == TTM_PL_TT) {
77 ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, 0,
78 dev_priv->gart_info.aper_size,
83 if (dev_priv->card_type != NV_04) {
84 ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, 0,
85 dev_priv->fb_available_size,
90 /* NV04 cmdbuf hack, from original ddx.. not sure of it's
91 * exact reason for existing :) PCI access to cmdbuf in
94 ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
95 pci_resource_start(dev->pdev, 1),
96 dev_priv->fb_available_size,
104 NV_ERROR(dev, "error initialising pushbuf: %d\n", ret);
105 nouveau_bo_vma_del(chan->pushbuf_bo, &chan->pushbuf_vma);
106 nouveau_gpuobj_ref(NULL, &chan->pushbuf);
107 if (chan->pushbuf_bo) {
108 nouveau_bo_unmap(chan->pushbuf_bo);
109 nouveau_bo_ref(NULL, &chan->pushbuf_bo);
116 /* allocates and initializes a fifo for user space consumption */
118 nouveau_channel_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret,
119 struct drm_file *file_priv,
120 uint32_t vram_handle, uint32_t gart_handle)
122 struct nouveau_exec_engine *fence = nv_engine(dev, NVOBJ_ENGINE_FENCE);
123 struct drm_nouveau_private *dev_priv = dev->dev_private;
124 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
125 struct nouveau_fpriv *fpriv = nouveau_fpriv(file_priv);
126 struct nouveau_channel *chan;
130 /* allocate and lock channel structure */
131 chan = kzalloc(sizeof(*chan), GFP_KERNEL);
135 chan->file_priv = file_priv;
136 chan->vram_handle = vram_handle;
137 chan->gart_handle = gart_handle;
139 kref_init(&chan->ref);
140 atomic_set(&chan->users, 1);
141 mutex_init(&chan->mutex);
142 mutex_lock(&chan->mutex);
144 /* allocate hw channel id */
145 spin_lock_irqsave(&dev_priv->channels.lock, flags);
146 for (chan->id = 0; chan->id < pfifo->channels; chan->id++) {
147 if (!dev_priv->channels.ptr[chan->id]) {
148 nouveau_channel_ref(chan, &dev_priv->channels.ptr[chan->id]);
152 spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
154 if (chan->id == pfifo->channels) {
155 mutex_unlock(&chan->mutex);
160 NV_DEBUG(dev, "initialising channel %d\n", chan->id);
162 /* setup channel's memory and vm */
163 ret = nouveau_gpuobj_channel_init(chan, vram_handle, gart_handle);
165 NV_ERROR(dev, "gpuobj %d\n", ret);
166 nouveau_channel_put(&chan);
170 /* Allocate space for per-channel fixed notifier memory */
171 ret = nouveau_notifier_init_channel(chan);
173 NV_ERROR(dev, "ntfy %d\n", ret);
174 nouveau_channel_put(&chan);
178 /* Allocate DMA push buffer */
179 ret = nouveau_channel_pushbuf_init(chan);
181 NV_ERROR(dev, "pushbuf %d\n", ret);
182 nouveau_channel_put(&chan);
186 nouveau_dma_init(chan);
187 chan->user_put = 0x40;
188 chan->user_get = 0x44;
189 if (dev_priv->card_type >= NV_50)
190 chan->user_get_hi = 0x60;
192 /* disable the fifo caches */
193 pfifo->reassign(dev, false);
195 /* Construct initial RAMFC for new channel */
196 ret = pfifo->create_context(chan);
198 nouveau_channel_put(&chan);
202 pfifo->reassign(dev, true);
204 /* Insert NOPs for NOUVEAU_DMA_SKIPS */
205 ret = RING_SPACE(chan, NOUVEAU_DMA_SKIPS);
207 nouveau_channel_put(&chan);
211 for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
212 OUT_RING (chan, 0x00000000);
214 ret = nouveau_gpuobj_gr_new(chan, NvSw, nouveau_software_class(dev));
216 nouveau_channel_put(&chan);
220 if (dev_priv->card_type < NV_C0) {
221 ret = RING_SPACE(chan, 2);
223 nouveau_channel_put(&chan);
227 BEGIN_NV04(chan, NvSubSw, NV01_SUBCHAN_OBJECT, 1);
228 OUT_RING (chan, NvSw);
234 ret = fence->context_new(chan, NVOBJ_ENGINE_FENCE);
236 nouveau_channel_put(&chan);
240 nouveau_debugfs_channel_init(chan);
242 NV_DEBUG(dev, "channel %d initialised\n", chan->id);
244 spin_lock(&fpriv->lock);
245 list_add(&chan->list, &fpriv->channels);
246 spin_unlock(&fpriv->lock);
252 struct nouveau_channel *
253 nouveau_channel_get_unlocked(struct nouveau_channel *ref)
255 struct nouveau_channel *chan = NULL;
257 if (likely(ref && atomic_inc_not_zero(&ref->users)))
258 nouveau_channel_ref(ref, &chan);
263 struct nouveau_channel *
264 nouveau_channel_get(struct drm_file *file_priv, int id)
266 struct nouveau_fpriv *fpriv = nouveau_fpriv(file_priv);
267 struct nouveau_channel *chan;
269 spin_lock(&fpriv->lock);
270 list_for_each_entry(chan, &fpriv->channels, list) {
271 if (chan->id == id) {
272 chan = nouveau_channel_get_unlocked(chan);
273 spin_unlock(&fpriv->lock);
274 mutex_lock(&chan->mutex);
278 spin_unlock(&fpriv->lock);
280 return ERR_PTR(-EINVAL);
284 nouveau_channel_put_unlocked(struct nouveau_channel **pchan)
286 struct nouveau_channel *chan = *pchan;
287 struct drm_device *dev = chan->dev;
288 struct drm_nouveau_private *dev_priv = dev->dev_private;
289 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
293 /* decrement the refcount, and we're done if there's still refs */
294 if (likely(!atomic_dec_and_test(&chan->users))) {
295 nouveau_channel_ref(NULL, pchan);
299 /* no one wants the channel anymore */
300 NV_DEBUG(dev, "freeing channel %d\n", chan->id);
301 nouveau_debugfs_channel_fini(chan);
303 /* give it chance to idle */
304 nouveau_channel_idle(chan);
306 /* boot it off the hardware */
307 pfifo->reassign(dev, false);
309 /* destroy the engine specific contexts */
310 for (i = NVOBJ_ENGINE_NR - 1; i >= 0; i--) {
312 dev_priv->eng[i]->context_del(chan, i);
313 /*XXX: clean this up later, order is important */
314 if (i == NVOBJ_ENGINE_FENCE)
315 pfifo->destroy_context(chan);
318 pfifo->reassign(dev, true);
320 /* aside from its resources, the channel should now be dead,
321 * remove it from the channel list
323 spin_lock_irqsave(&dev_priv->channels.lock, flags);
324 nouveau_channel_ref(NULL, &dev_priv->channels.ptr[chan->id]);
325 spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
327 /* destroy any resources the channel owned */
328 nouveau_gpuobj_ref(NULL, &chan->pushbuf);
329 if (chan->pushbuf_bo) {
330 nouveau_bo_vma_del(chan->pushbuf_bo, &chan->pushbuf_vma);
331 nouveau_bo_unmap(chan->pushbuf_bo);
332 nouveau_bo_unpin(chan->pushbuf_bo);
333 nouveau_bo_ref(NULL, &chan->pushbuf_bo);
335 nouveau_ramht_ref(NULL, &chan->ramht, chan);
336 nouveau_notifier_takedown_channel(chan);
337 nouveau_gpuobj_channel_takedown(chan);
339 nouveau_channel_ref(NULL, pchan);
343 nouveau_channel_put(struct nouveau_channel **pchan)
345 mutex_unlock(&(*pchan)->mutex);
346 nouveau_channel_put_unlocked(pchan);
350 nouveau_channel_del(struct kref *ref)
352 struct nouveau_channel *chan =
353 container_of(ref, struct nouveau_channel, ref);
359 nouveau_channel_ref(struct nouveau_channel *chan,
360 struct nouveau_channel **pchan)
363 kref_get(&chan->ref);
366 kref_put(&(*pchan)->ref, nouveau_channel_del);
372 nouveau_channel_idle(struct nouveau_channel *chan)
374 struct drm_device *dev = chan->dev;
375 struct nouveau_fence *fence = NULL;
378 ret = nouveau_fence_new(chan, &fence);
380 ret = nouveau_fence_wait(fence, false, false);
381 nouveau_fence_unref(&fence);
385 NV_ERROR(dev, "Failed to idle channel %d.\n", chan->id);
388 /* cleans up all the fifos from file_priv */
390 nouveau_channel_cleanup(struct drm_device *dev, struct drm_file *file_priv)
392 struct drm_nouveau_private *dev_priv = dev->dev_private;
393 struct nouveau_engine *engine = &dev_priv->engine;
394 struct nouveau_channel *chan;
397 NV_DEBUG(dev, "clearing FIFO enables from file_priv\n");
398 for (i = 0; i < engine->fifo.channels; i++) {
399 chan = nouveau_channel_get(file_priv, i);
403 list_del(&chan->list);
404 atomic_dec(&chan->users);
405 nouveau_channel_put(&chan);
410 /***********************************
411 * ioctls wrapping the functions
412 ***********************************/
415 nouveau_ioctl_fifo_alloc(struct drm_device *dev, void *data,
416 struct drm_file *file_priv)
418 struct drm_nouveau_private *dev_priv = dev->dev_private;
419 struct drm_nouveau_channel_alloc *init = data;
420 struct nouveau_channel *chan;
423 if (!dev_priv->eng[NVOBJ_ENGINE_GR])
426 if (init->fb_ctxdma_handle == ~0 || init->tt_ctxdma_handle == ~0)
429 ret = nouveau_channel_alloc(dev, &chan, file_priv,
430 init->fb_ctxdma_handle,
431 init->tt_ctxdma_handle);
434 init->channel = chan->id;
436 if (nouveau_vram_pushbuf == 0) {
437 if (chan->dma.ib_max)
438 init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM |
439 NOUVEAU_GEM_DOMAIN_GART;
440 else if (chan->pushbuf_bo->bo.mem.mem_type == TTM_PL_VRAM)
441 init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM;
443 init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_GART;
445 init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM;
448 if (dev_priv->card_type < NV_C0) {
449 init->subchan[0].handle = 0x00000000;
450 init->subchan[0].grclass = 0x0000;
451 init->subchan[1].handle = NvSw;
452 init->subchan[1].grclass = NV_SW;
453 init->nr_subchan = 2;
456 /* Named memory object area */
457 ret = drm_gem_handle_create(file_priv, chan->notifier_bo->gem,
458 &init->notifier_handle);
461 atomic_inc(&chan->users); /* userspace reference */
462 nouveau_channel_put(&chan);
467 nouveau_ioctl_fifo_free(struct drm_device *dev, void *data,
468 struct drm_file *file_priv)
470 struct drm_nouveau_channel_free *req = data;
471 struct nouveau_channel *chan;
473 chan = nouveau_channel_get(file_priv, req->channel);
475 return PTR_ERR(chan);
477 list_del(&chan->list);
478 atomic_dec(&chan->users);
479 nouveau_channel_put(&chan);
483 /***********************************
484 * finally, the ioctl table
485 ***********************************/
487 struct drm_ioctl_desc nouveau_ioctls[] = {
488 DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_ioctl_getparam, DRM_UNLOCKED|DRM_AUTH),
489 DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, nouveau_ioctl_setparam, DRM_UNLOCKED|DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
490 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_ioctl_fifo_alloc, DRM_UNLOCKED|DRM_AUTH),
491 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_ioctl_fifo_free, DRM_UNLOCKED|DRM_AUTH),
492 DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_ioctl_grobj_alloc, DRM_UNLOCKED|DRM_AUTH),
493 DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_ioctl_notifier_alloc, DRM_UNLOCKED|DRM_AUTH),
494 DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_ioctl_gpuobj_free, DRM_UNLOCKED|DRM_AUTH),
495 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_UNLOCKED|DRM_AUTH),
496 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_UNLOCKED|DRM_AUTH),
497 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_UNLOCKED|DRM_AUTH),
498 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_UNLOCKED|DRM_AUTH),
499 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_UNLOCKED|DRM_AUTH),
502 int nouveau_max_ioctl = DRM_ARRAY_SIZE(nouveau_ioctls);