2 * Copyright (C) 2007 Ben Skeggs.
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "nouveau_drv.h"
30 #include "nouveau_dma.h"
31 #include "nouveau_ramht.h"
34 nouveau_dma_init(struct nouveau_channel *chan)
36 struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
37 struct nouveau_bo *pushbuf = chan->pushbuf_bo;
39 if (dev_priv->card_type >= NV_50) {
40 const int ib_size = pushbuf->bo.mem.size / 2;
42 chan->dma.ib_base = (pushbuf->bo.mem.size - ib_size) >> 2;
43 chan->dma.ib_max = (ib_size / 8) - 1;
45 chan->dma.ib_free = chan->dma.ib_max - chan->dma.ib_put;
47 chan->dma.max = (pushbuf->bo.mem.size - ib_size) >> 2;
49 chan->dma.max = (pushbuf->bo.mem.size >> 2) - 2;
53 chan->dma.cur = chan->dma.put;
54 chan->dma.free = chan->dma.max - chan->dma.cur;
58 OUT_RINGp(struct nouveau_channel *chan, const void *data, unsigned nr_dwords)
61 u32 *mem = ttm_kmap_obj_virtual(&chan->pushbuf_bo->kmap, &is_iomem);
62 mem = &mem[chan->dma.cur];
64 memcpy_toio((void __force __iomem *)mem, data, nr_dwords * 4);
66 memcpy(mem, data, nr_dwords * 4);
67 chan->dma.cur += nr_dwords;
70 /* Fetch and adjust GPU GET pointer
73 * value >= 0, the adjusted GET pointer
74 * -EINVAL if GET pointer currently outside main push buffer
75 * -EBUSY if timeout exceeded
78 READ_GET(struct nouveau_channel *chan, uint64_t *prev_get, int *timeout)
82 val = nvchan_rd32(chan, chan->user_get);
83 if (chan->user_get_hi)
84 val |= (uint64_t)nvchan_rd32(chan, chan->user_get_hi) << 32;
86 /* reset counter as long as GET is still advancing, this is
87 * to avoid misdetecting a GPU lockup if the GPU happens to
88 * just be processing an operation that takes a long time
90 if (val != *prev_get) {
95 if ((++*timeout & 0xff) == 0) {
97 if (*timeout > 100000)
101 if (val < chan->pushbuf_base ||
102 val > chan->pushbuf_base + (chan->dma.max << 2))
105 return (val - chan->pushbuf_base) >> 2;
109 nv50_dma_push(struct nouveau_channel *chan, struct nouveau_bo *bo,
110 int delta, int length)
112 struct nouveau_bo *pb = chan->pushbuf_bo;
113 struct nouveau_vma *vma;
114 int ip = (chan->dma.ib_put * 2) + chan->dma.ib_base;
117 vma = nouveau_bo_vma_find(bo, chan->vm);
119 offset = vma->offset + delta;
121 BUG_ON(chan->dma.ib_free < 1);
122 nouveau_bo_wr32(pb, ip++, lower_32_bits(offset));
123 nouveau_bo_wr32(pb, ip++, upper_32_bits(offset) | length << 8);
125 chan->dma.ib_put = (chan->dma.ib_put + 1) & chan->dma.ib_max;
129 nouveau_bo_rd32(pb, 0);
131 nvchan_wr32(chan, 0x8c, chan->dma.ib_put);
136 nv50_dma_push_wait(struct nouveau_channel *chan, int count)
138 uint32_t cnt = 0, prev_get = 0;
140 while (chan->dma.ib_free < count) {
141 uint32_t get = nvchan_rd32(chan, 0x88);
142 if (get != prev_get) {
147 if ((++cnt & 0xff) == 0) {
153 chan->dma.ib_free = get - chan->dma.ib_put;
154 if (chan->dma.ib_free <= 0)
155 chan->dma.ib_free += chan->dma.ib_max;
162 nv50_dma_wait(struct nouveau_channel *chan, int slots, int count)
164 uint64_t prev_get = 0;
167 ret = nv50_dma_push_wait(chan, slots + 1);
171 while (chan->dma.free < count) {
172 int get = READ_GET(chan, &prev_get, &cnt);
173 if (unlikely(get < 0)) {
180 if (get <= chan->dma.cur) {
181 chan->dma.free = chan->dma.max - chan->dma.cur;
182 if (chan->dma.free >= count)
187 get = READ_GET(chan, &prev_get, &cnt);
188 if (unlikely(get < 0)) {
198 chan->dma.free = get - chan->dma.cur - 1;
205 nouveau_dma_wait(struct nouveau_channel *chan, int slots, int size)
207 uint64_t prev_get = 0;
210 if (chan->dma.ib_max)
211 return nv50_dma_wait(chan, slots, size);
213 while (chan->dma.free < size) {
214 get = READ_GET(chan, &prev_get, &cnt);
215 if (unlikely(get == -EBUSY))
218 /* loop until we have a usable GET pointer. the value
219 * we read from the GPU may be outside the main ring if
220 * PFIFO is processing a buffer called from the main ring,
221 * discard these values until something sensible is seen.
223 * the other case we discard GET is while the GPU is fetching
224 * from the SKIPS area, so the code below doesn't have to deal
225 * with some fun corner cases.
227 if (unlikely(get == -EINVAL) || get < NOUVEAU_DMA_SKIPS)
230 if (get <= chan->dma.cur) {
231 /* engine is fetching behind us, or is completely
232 * idle (GET == PUT) so we have free space up until
233 * the end of the push buffer
235 * we can only hit that path once per call due to
236 * looping back to the beginning of the push buffer,
237 * we'll hit the fetching-ahead-of-us path from that
240 * the *one* exception to that rule is if we read
241 * GET==PUT, in which case the below conditional will
242 * always succeed and break us out of the wait loop.
244 chan->dma.free = chan->dma.max - chan->dma.cur;
245 if (chan->dma.free >= size)
248 /* not enough space left at the end of the push buffer,
249 * instruct the GPU to jump back to the start right
250 * after processing the currently pending commands.
252 OUT_RING(chan, chan->pushbuf_base | 0x20000000);
254 /* wait for GET to depart from the skips area.
255 * prevents writing GET==PUT and causing a race
256 * condition that causes us to think the GPU is
257 * idle when it's not.
260 get = READ_GET(chan, &prev_get, &cnt);
261 if (unlikely(get == -EBUSY))
263 if (unlikely(get == -EINVAL))
265 } while (get <= NOUVEAU_DMA_SKIPS);
266 WRITE_PUT(NOUVEAU_DMA_SKIPS);
268 /* we're now submitting commands at the start of
272 chan->dma.put = NOUVEAU_DMA_SKIPS;
275 /* engine fetching ahead of us, we have space up until the
276 * current GET pointer. the "- 1" is to ensure there's
277 * space left to emit a jump back to the beginning of the
278 * push buffer if we require it. we can never get GET == PUT
279 * here, so this is safe.
281 chan->dma.free = get - chan->dma.cur - 1;