2 * Copyright (C) 2007 Ben Skeggs.
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "nouveau_drv.h"
30 #include "nouveau_dma.h"
31 #include "nouveau_ramht.h"
34 nouveau_dma_pre_init(struct nouveau_channel *chan)
36 struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
37 struct nouveau_bo *pushbuf = chan->pushbuf_bo;
39 if (dev_priv->card_type == NV_50) {
40 const int ib_size = pushbuf->bo.mem.size / 2;
42 chan->dma.ib_base = (pushbuf->bo.mem.size - ib_size) >> 2;
43 chan->dma.ib_max = (ib_size / 8) - 1;
45 chan->dma.ib_free = chan->dma.ib_max - chan->dma.ib_put;
47 chan->dma.max = (pushbuf->bo.mem.size - ib_size) >> 2;
49 chan->dma.max = (pushbuf->bo.mem.size >> 2) - 2;
53 chan->dma.cur = chan->dma.put;
54 chan->dma.free = chan->dma.max - chan->dma.cur;
58 nouveau_dma_init(struct nouveau_channel *chan)
60 struct drm_device *dev = chan->dev;
61 struct drm_nouveau_private *dev_priv = dev->dev_private;
64 /* Create NV_MEMORY_TO_MEMORY_FORMAT for buffer moves */
65 ret = nouveau_gpuobj_gr_new(chan, NvM2MF, dev_priv->card_type < NV_50 ?
70 /* NV_MEMORY_TO_MEMORY_FORMAT requires a notifier object */
71 ret = nouveau_notifier_alloc(chan, NvNotify0, 32, &chan->m2mf_ntfy);
76 ret = nouveau_bo_map(chan->pushbuf_bo);
80 /* Insert NOPS for NOUVEAU_DMA_SKIPS */
81 ret = RING_SPACE(chan, NOUVEAU_DMA_SKIPS);
85 for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
88 /* Initialise NV_MEMORY_TO_MEMORY_FORMAT */
89 ret = RING_SPACE(chan, 4);
92 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NAME, 1);
93 OUT_RING(chan, NvM2MF);
94 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY, 1);
95 OUT_RING(chan, NvNotify0);
97 /* Sit back and pray the channel works.. */
104 OUT_RINGp(struct nouveau_channel *chan, const void *data, unsigned nr_dwords)
107 u32 *mem = ttm_kmap_obj_virtual(&chan->pushbuf_bo->kmap, &is_iomem);
108 mem = &mem[chan->dma.cur];
110 memcpy_toio((void __force __iomem *)mem, data, nr_dwords * 4);
112 memcpy(mem, data, nr_dwords * 4);
113 chan->dma.cur += nr_dwords;
116 /* Fetch and adjust GPU GET pointer
119 * value >= 0, the adjusted GET pointer
120 * -EINVAL if GET pointer currently outside main push buffer
121 * -EBUSY if timeout exceeded
124 READ_GET(struct nouveau_channel *chan, uint32_t *prev_get, uint32_t *timeout)
128 val = nvchan_rd32(chan, chan->user_get);
130 /* reset counter as long as GET is still advancing, this is
131 * to avoid misdetecting a GPU lockup if the GPU happens to
132 * just be processing an operation that takes a long time
134 if (val != *prev_get) {
139 if ((++*timeout & 0xff) == 0) {
141 if (*timeout > 100000)
145 if (val < chan->pushbuf_base ||
146 val > chan->pushbuf_base + (chan->dma.max << 2))
149 return (val - chan->pushbuf_base) >> 2;
153 nv50_dma_push(struct nouveau_channel *chan, struct nouveau_bo *bo,
154 int delta, int length)
156 struct nouveau_bo *pb = chan->pushbuf_bo;
157 uint64_t offset = bo->bo.offset + delta;
158 int ip = (chan->dma.ib_put * 2) + chan->dma.ib_base;
160 BUG_ON(chan->dma.ib_free < 1);
161 nouveau_bo_wr32(pb, ip++, lower_32_bits(offset));
162 nouveau_bo_wr32(pb, ip++, upper_32_bits(offset) | length << 8);
164 chan->dma.ib_put = (chan->dma.ib_put + 1) & chan->dma.ib_max;
168 nouveau_bo_rd32(pb, 0);
170 nvchan_wr32(chan, 0x8c, chan->dma.ib_put);
175 nv50_dma_push_wait(struct nouveau_channel *chan, int count)
177 uint32_t cnt = 0, prev_get = 0;
179 while (chan->dma.ib_free < count) {
180 uint32_t get = nvchan_rd32(chan, 0x88);
181 if (get != prev_get) {
186 if ((++cnt & 0xff) == 0) {
192 chan->dma.ib_free = get - chan->dma.ib_put;
193 if (chan->dma.ib_free <= 0)
194 chan->dma.ib_free += chan->dma.ib_max;
201 nv50_dma_wait(struct nouveau_channel *chan, int slots, int count)
203 uint32_t cnt = 0, prev_get = 0;
206 ret = nv50_dma_push_wait(chan, slots + 1);
210 while (chan->dma.free < count) {
211 int get = READ_GET(chan, &prev_get, &cnt);
212 if (unlikely(get < 0)) {
219 if (get <= chan->dma.cur) {
220 chan->dma.free = chan->dma.max - chan->dma.cur;
221 if (chan->dma.free >= count)
226 get = READ_GET(chan, &prev_get, &cnt);
227 if (unlikely(get < 0)) {
237 chan->dma.free = get - chan->dma.cur - 1;
244 nouveau_dma_wait(struct nouveau_channel *chan, int slots, int size)
246 uint32_t prev_get = 0, cnt = 0;
249 if (chan->dma.ib_max)
250 return nv50_dma_wait(chan, slots, size);
252 while (chan->dma.free < size) {
253 get = READ_GET(chan, &prev_get, &cnt);
254 if (unlikely(get == -EBUSY))
257 /* loop until we have a usable GET pointer. the value
258 * we read from the GPU may be outside the main ring if
259 * PFIFO is processing a buffer called from the main ring,
260 * discard these values until something sensible is seen.
262 * the other case we discard GET is while the GPU is fetching
263 * from the SKIPS area, so the code below doesn't have to deal
264 * with some fun corner cases.
266 if (unlikely(get == -EINVAL) || get < NOUVEAU_DMA_SKIPS)
269 if (get <= chan->dma.cur) {
270 /* engine is fetching behind us, or is completely
271 * idle (GET == PUT) so we have free space up until
272 * the end of the push buffer
274 * we can only hit that path once per call due to
275 * looping back to the beginning of the push buffer,
276 * we'll hit the fetching-ahead-of-us path from that
279 * the *one* exception to that rule is if we read
280 * GET==PUT, in which case the below conditional will
281 * always succeed and break us out of the wait loop.
283 chan->dma.free = chan->dma.max - chan->dma.cur;
284 if (chan->dma.free >= size)
287 /* not enough space left at the end of the push buffer,
288 * instruct the GPU to jump back to the start right
289 * after processing the currently pending commands.
291 OUT_RING(chan, chan->pushbuf_base | 0x20000000);
293 /* wait for GET to depart from the skips area.
294 * prevents writing GET==PUT and causing a race
295 * condition that causes us to think the GPU is
296 * idle when it's not.
299 get = READ_GET(chan, &prev_get, &cnt);
300 if (unlikely(get == -EBUSY))
302 if (unlikely(get == -EINVAL))
304 } while (get <= NOUVEAU_DMA_SKIPS);
305 WRITE_PUT(NOUVEAU_DMA_SKIPS);
307 /* we're now submitting commands at the start of
311 chan->dma.put = NOUVEAU_DMA_SKIPS;
314 /* engine fetching ahead of us, we have space up until the
315 * current GET pointer. the "- 1" is to ensure there's
316 * space left to emit a jump back to the beginning of the
317 * push buffer if we require it. we can never get GET == PUT
318 * here, so this is safe.
320 chan->dma.free = get - chan->dma.cur - 1;