2 * Copyright 2009 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <drm/drm_dp_helper.h>
28 #include "nouveau_drm.h"
29 #include "nouveau_connector.h"
30 #include "nouveau_encoder.h"
31 #include "nouveau_crtc.h"
33 #include <subdev/gpio.h>
34 #include <subdev/i2c.h>
37 nouveau_dp_bios_data(struct drm_device *dev, struct dcb_output *dcb, u8 **entry)
39 struct nouveau_drm *drm = nouveau_drm(dev);
44 if (bit_table(dev, 'd', &d)) {
45 NV_ERROR(drm, "BIT 'd' table not found\n");
50 NV_ERROR(drm, "BIT 'd' table version %d unknown\n", d.version);
54 table = ROMPTR(dev, d.data[0]);
56 NV_ERROR(drm, "displayport table pointer invalid\n");
67 NV_ERROR(drm, "displayport table 0x%02x unknown\n", table[0]);
71 for (i = 0; i < table[3]; i++) {
72 *entry = ROMPTR(dev, table[table[1] + (i * table[2])]);
73 if (*entry && bios_encoder_match(dcb, ROM32((*entry)[0])))
77 NV_ERROR(drm, "displayport encoder table not found\n");
81 /******************************************************************************
83 *****************************************************************************/
85 struct nouveau_i2c_port *auxch;
86 struct dp_train_func *func;
87 struct dcb_output *dcb;
97 dp_set_link_config(struct drm_device *dev, struct dp_state *dp)
99 struct nouveau_drm *drm = nouveau_drm(dev);
102 NV_DEBUG(drm, "%d lanes at %d KB/s\n", dp->link_nr, dp->link_bw);
104 /* set desired link configuration on the source */
105 dp->func->link_set(dev, dp->dcb, dp->crtc, dp->link_nr, dp->link_bw,
106 dp->dpcd[2] & DP_ENHANCED_FRAME_CAP);
108 /* inform the sink of the new configuration */
109 sink[0] = dp->link_bw / 27000;
110 sink[1] = dp->link_nr;
111 if (dp->dpcd[2] & DP_ENHANCED_FRAME_CAP)
112 sink[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
114 nv_wraux(dp->auxch, DP_LINK_BW_SET, sink, 2);
118 dp_set_training_pattern(struct drm_device *dev, struct dp_state *dp, u8 pattern)
120 struct nouveau_drm *drm = nouveau_drm(dev);
123 NV_DEBUG(drm, "training pattern %d\n", pattern);
125 dp->func->train_set(dev, dp->dcb, pattern);
127 nv_rdaux(dp->auxch, DP_TRAINING_PATTERN_SET, &sink_tp, 1);
128 sink_tp &= ~DP_TRAINING_PATTERN_MASK;
130 nv_wraux(dp->auxch, DP_TRAINING_PATTERN_SET, &sink_tp, 1);
134 dp_link_train_commit(struct drm_device *dev, struct dp_state *dp)
136 struct nouveau_drm *drm = nouveau_drm(dev);
139 for (i = 0; i < dp->link_nr; i++) {
140 u8 lane = (dp->stat[4 + (i >> 1)] >> ((i & 1) * 4)) & 0xf;
141 u8 lpre = (lane & 0x0c) >> 2;
142 u8 lvsw = (lane & 0x03) >> 0;
144 dp->conf[i] = (lpre << 3) | lvsw;
145 if (lvsw == DP_TRAIN_VOLTAGE_SWING_1200)
146 dp->conf[i] |= DP_TRAIN_MAX_SWING_REACHED;
147 if ((lpre << 3) == DP_TRAIN_PRE_EMPHASIS_9_5)
148 dp->conf[i] |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
150 NV_DEBUG(drm, "config lane %d %02x\n", i, dp->conf[i]);
151 dp->func->train_adj(dev, dp->dcb, i, lvsw, lpre);
154 return nv_wraux(dp->auxch, DP_TRAINING_LANE0_SET, dp->conf, 4);
158 dp_link_train_update(struct drm_device *dev, struct dp_state *dp, u32 delay)
160 struct nouveau_drm *drm = nouveau_drm(dev);
165 ret = nv_rdaux(dp->auxch, DP_LANE0_1_STATUS, dp->stat, 6);
169 NV_DEBUG(drm, "status %*ph\n", 6, dp->stat);
174 dp_link_train_cr(struct drm_device *dev, struct dp_state *dp)
176 bool cr_done = false, abort = false;
177 int voltage = dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
180 dp_set_training_pattern(dev, dp, DP_TRAINING_PATTERN_1);
183 if (dp_link_train_commit(dev, dp) ||
184 dp_link_train_update(dev, dp, 100))
188 for (i = 0; i < dp->link_nr; i++) {
189 u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
190 if (!(lane & DP_LANE_CR_DONE)) {
192 if (dp->conf[i] & DP_TRAIN_MAX_SWING_REACHED)
198 if ((dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK) != voltage) {
199 voltage = dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
202 } while (!cr_done && !abort && ++tries < 5);
204 return cr_done ? 0 : -1;
208 dp_link_train_eq(struct drm_device *dev, struct dp_state *dp)
210 bool eq_done, cr_done = true;
213 dp_set_training_pattern(dev, dp, DP_TRAINING_PATTERN_2);
216 if (dp_link_train_update(dev, dp, 400))
219 eq_done = !!(dp->stat[2] & DP_INTERLANE_ALIGN_DONE);
220 for (i = 0; i < dp->link_nr && eq_done; i++) {
221 u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
222 if (!(lane & DP_LANE_CR_DONE))
224 if (!(lane & DP_LANE_CHANNEL_EQ_DONE) ||
225 !(lane & DP_LANE_SYMBOL_LOCKED))
229 if (dp_link_train_commit(dev, dp))
231 } while (!eq_done && cr_done && ++tries <= 5);
233 return eq_done ? 0 : -1;
237 dp_set_downspread(struct drm_device *dev, struct dp_state *dp, bool enable)
240 u8 *entry, *table = nouveau_dp_bios_data(dev, dp->dcb, &entry);
242 if (table[0] >= 0x20 && table[0] <= 0x30) {
243 if (enable) script = ROM16(entry[12]);
244 else script = ROM16(entry[14]);
246 if (table[0] == 0x40) {
247 if (enable) script = ROM16(entry[11]);
248 else script = ROM16(entry[13]);
252 nouveau_bios_run_init_table(dev, script, dp->dcb, dp->crtc);
256 dp_link_train_init(struct drm_device *dev, struct dp_state *dp)
259 u8 *entry, *table = nouveau_dp_bios_data(dev, dp->dcb, &entry);
261 if (table[0] >= 0x20 && table[0] <= 0x30)
262 script = ROM16(entry[6]);
264 if (table[0] == 0x40)
265 script = ROM16(entry[5]);
268 nouveau_bios_run_init_table(dev, script, dp->dcb, dp->crtc);
272 dp_link_train_fini(struct drm_device *dev, struct dp_state *dp)
275 u8 *entry, *table = nouveau_dp_bios_data(dev, dp->dcb, &entry);
277 if (table[0] >= 0x20 && table[0] <= 0x30)
278 script = ROM16(entry[8]);
280 if (table[0] == 0x40)
281 script = ROM16(entry[7]);
284 nouveau_bios_run_init_table(dev, script, dp->dcb, dp->crtc);
288 nouveau_dp_link_train(struct drm_encoder *encoder, u32 datarate,
289 struct dp_train_func *func)
291 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
292 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
293 struct nouveau_connector *nv_connector =
294 nouveau_encoder_connector_get(nv_encoder);
295 struct drm_device *dev = encoder->dev;
296 struct nouveau_drm *drm = nouveau_drm(dev);
297 struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
298 struct nouveau_gpio *gpio = nouveau_gpio(drm->device);
299 const u32 bw_list[] = { 270000, 162000, 0 };
300 const u32 *link_bw = bw_list;
303 dp.auxch = i2c->find(i2c, nv_encoder->dcb->i2c_index);
308 dp.dcb = nv_encoder->dcb;
309 dp.crtc = nv_crtc->index;
310 dp.dpcd = nv_encoder->dp.dpcd;
312 /* adjust required bandwidth for 8B/10B coding overhead */
313 datarate = (datarate / 8) * 10;
315 /* some sinks toggle hotplug in response to some of the actions
316 * we take during link training (DP_SET_POWER is one), we need
317 * to ignore them for the moment to avoid races.
319 gpio->irq(gpio, 0, nv_connector->hpd, 0xff, false);
321 /* enable down-spreading, if possible */
322 dp_set_downspread(dev, &dp, nv_encoder->dp.dpcd[3] & 1);
324 /* execute pre-train script from vbios */
325 dp_link_train_init(dev, &dp);
327 /* start off at highest link rate supported by encoder and display */
328 while (*link_bw > nv_encoder->dp.link_bw)
332 /* find minimum required lane count at this link rate */
333 dp.link_nr = nv_encoder->dp.link_nr;
334 while ((dp.link_nr >> 1) * link_bw[0] > datarate)
337 /* drop link rate to minimum with this lane count */
338 while ((link_bw[1] * dp.link_nr) > datarate)
340 dp.link_bw = link_bw[0];
342 /* program selected link configuration */
343 dp_set_link_config(dev, &dp);
345 /* attempt to train the link at this configuration */
346 memset(dp.stat, 0x00, sizeof(dp.stat));
347 if (!dp_link_train_cr(dev, &dp) &&
348 !dp_link_train_eq(dev, &dp))
351 /* retry at lower rate */
355 /* finish link training */
356 dp_set_training_pattern(dev, &dp, DP_TRAINING_PATTERN_DISABLE);
358 /* execute post-train script from vbios */
359 dp_link_train_fini(dev, &dp);
361 /* re-enable hotplug detect */
362 gpio->irq(gpio, 0, nv_connector->hpd, 0xff, true);
367 nouveau_dp_dpms(struct drm_encoder *encoder, int mode, u32 datarate,
368 struct dp_train_func *func)
370 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
371 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
372 struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
373 struct nouveau_i2c_port *auxch;
376 auxch = i2c->find(i2c, nv_encoder->dcb->i2c_index);
380 if (mode == DRM_MODE_DPMS_ON)
381 status = DP_SET_POWER_D0;
383 status = DP_SET_POWER_D3;
385 nv_wraux(auxch, DP_SET_POWER, &status, 1);
387 if (mode == DRM_MODE_DPMS_ON)
388 nouveau_dp_link_train(encoder, datarate, func);
392 nouveau_dp_probe_oui(struct drm_device *dev, struct nouveau_i2c_port *auxch,
395 struct nouveau_drm *drm = nouveau_drm(dev);
398 if (!(dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
401 if (!nv_rdaux(auxch, DP_SINK_OUI, buf, 3))
402 NV_DEBUG(drm, "Sink OUI: %02hx%02hx%02hx\n",
403 buf[0], buf[1], buf[2]);
405 if (!nv_rdaux(auxch, DP_BRANCH_OUI, buf, 3))
406 NV_DEBUG(drm, "Branch OUI: %02hx%02hx%02hx\n",
407 buf[0], buf[1], buf[2]);
412 nouveau_dp_detect(struct drm_encoder *encoder)
414 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
415 struct drm_device *dev = encoder->dev;
416 struct nouveau_drm *drm = nouveau_drm(dev);
417 struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
418 struct nouveau_i2c_port *auxch;
419 u8 *dpcd = nv_encoder->dp.dpcd;
422 auxch = i2c->find(i2c, nv_encoder->dcb->i2c_index);
426 ret = nv_rdaux(auxch, DP_DPCD_REV, dpcd, 8);
430 nv_encoder->dp.link_bw = 27000 * dpcd[1];
431 nv_encoder->dp.link_nr = dpcd[2] & DP_MAX_LANE_COUNT_MASK;
433 NV_DEBUG(drm, "display: %dx%d dpcd 0x%02x\n",
434 nv_encoder->dp.link_nr, nv_encoder->dp.link_bw, dpcd[0]);
435 NV_DEBUG(drm, "encoder: %dx%d\n",
436 nv_encoder->dcb->dpconf.link_nr,
437 nv_encoder->dcb->dpconf.link_bw);
439 if (nv_encoder->dcb->dpconf.link_nr < nv_encoder->dp.link_nr)
440 nv_encoder->dp.link_nr = nv_encoder->dcb->dpconf.link_nr;
441 if (nv_encoder->dcb->dpconf.link_bw < nv_encoder->dp.link_bw)
442 nv_encoder->dp.link_bw = nv_encoder->dcb->dpconf.link_bw;
444 NV_DEBUG(drm, "maximum: %dx%d\n",
445 nv_encoder->dp.link_nr, nv_encoder->dp.link_bw);
447 nouveau_dp_probe_oui(dev, auxch, dpcd);