2 * Copyright 2005 Stephane Marchesin.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 #ifndef __NOUVEAU_DRV_H__
26 #define __NOUVEAU_DRV_H__
28 #define DRIVER_AUTHOR "Stephane Marchesin"
29 #define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
31 #define DRIVER_NAME "nouveau"
32 #define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33 #define DRIVER_DATE "20090420"
35 #define DRIVER_MAJOR 0
36 #define DRIVER_MINOR 0
37 #define DRIVER_PATCHLEVEL 16
39 #define NOUVEAU_FAMILY 0x0000FFFF
40 #define NOUVEAU_FLAGS 0xFFFF0000
42 #include "ttm/ttm_bo_api.h"
43 #include "ttm/ttm_bo_driver.h"
44 #include "ttm/ttm_placement.h"
45 #include "ttm/ttm_memory.h"
46 #include "ttm/ttm_module.h"
48 struct nouveau_fpriv {
50 struct list_head channels;
51 struct nouveau_vm *vm;
54 static inline struct nouveau_fpriv *
55 nouveau_fpriv(struct drm_file *file_priv)
57 return file_priv ? file_priv->driver_priv : NULL;
60 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
62 #include "nouveau_drm.h"
63 #include "nouveau_reg.h"
64 #include "nouveau_bios.h"
65 #include "nouveau_util.h"
69 #include "nouveau_vm.h"
71 #define MAX_NUM_DCB_ENTRIES 16
73 #define NOUVEAU_MAX_CHANNEL_NR 128
74 #define NOUVEAU_MAX_TILE_NR 15
77 struct drm_device *dev;
79 struct nouveau_vma bar_vma;
80 struct nouveau_vma vma[2];
83 struct drm_mm_node *tag;
84 struct list_head regions;
91 struct nouveau_tile_reg {
97 struct drm_mm_node *tag_mem;
98 struct nouveau_fence *fence;
102 struct ttm_buffer_object bo;
103 struct ttm_placement placement;
106 u32 busy_placements[3];
107 struct ttm_bo_kmap_obj kmap;
108 struct list_head head;
110 /* protected by ttm_bo_reserve() */
111 struct drm_file *reserved_by;
112 struct list_head entry;
114 bool validate_mapped;
116 struct nouveau_channel *channel;
118 struct list_head vma_list;
123 struct nouveau_tile_reg *tile;
125 struct drm_gem_object *gem;
129 #define nouveau_bo_tile_layout(nvbo) \
130 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK)
132 static inline struct nouveau_bo *
133 nouveau_bo(struct ttm_buffer_object *bo)
135 return container_of(bo, struct nouveau_bo, bo);
138 static inline struct nouveau_bo *
139 nouveau_gem_object(struct drm_gem_object *gem)
141 return gem ? gem->driver_private : NULL;
144 /* TODO: submit equivalent to TTM generic API upstream? */
145 static inline void __iomem *
146 nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
149 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual(
150 &nvbo->kmap, &is_iomem);
151 WARN_ON_ONCE(ioptr && !is_iomem);
156 NV_NFORCE = 0x10000000,
157 NV_NFORCE2 = 0x20000000
160 #define NVOBJ_ENGINE_SW 0
161 #define NVOBJ_ENGINE_GR 1
162 #define NVOBJ_ENGINE_CRYPT 2
163 #define NVOBJ_ENGINE_COPY0 3
164 #define NVOBJ_ENGINE_COPY1 4
165 #define NVOBJ_ENGINE_MPEG 5
166 #define NVOBJ_ENGINE_PPP NVOBJ_ENGINE_MPEG
167 #define NVOBJ_ENGINE_BSP 6
168 #define NVOBJ_ENGINE_VP 7
169 #define NVOBJ_ENGINE_DISPLAY 15
170 #define NVOBJ_ENGINE_NR 16
172 #define NVOBJ_FLAG_DONT_MAP (1 << 0)
173 #define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
174 #define NVOBJ_FLAG_ZERO_FREE (1 << 2)
175 #define NVOBJ_FLAG_VM (1 << 3)
176 #define NVOBJ_FLAG_VM_USER (1 << 4)
178 #define NVOBJ_CINST_GLOBAL 0xdeadbeef
180 struct nouveau_gpuobj {
181 struct drm_device *dev;
182 struct kref refcount;
183 struct list_head list;
191 u32 pinst; /* PRAMIN BAR offset */
192 u32 cinst; /* Channel offset */
193 u64 vinst; /* VRAM address */
194 u64 linst; /* VM address */
199 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
203 struct nouveau_page_flip_state {
204 struct list_head head;
205 struct drm_pending_vblank_event *event;
206 int crtc, bpp, pitch, x, y;
210 enum nouveau_channel_mutex_class {
211 NOUVEAU_UCHANNEL_MUTEX,
212 NOUVEAU_KCHANNEL_MUTEX
215 struct nouveau_channel {
216 struct drm_device *dev;
217 struct list_head list;
220 /* references to the channel data structure */
222 /* users of the hardware channel resources, the hardware
223 * context will be kicked off when it reaches zero. */
227 /* owner of this fifo */
228 struct drm_file *file_priv;
229 /* mapping of the fifo itself */
230 struct drm_local_map *map;
232 /* mapping of the regs controlling the fifo */
235 uint32_t user_get_hi;
240 /* lock protects the pending list only */
242 struct list_head pending;
244 uint32_t sequence_ack;
245 atomic_t last_sequence_irq;
246 struct nouveau_vma vma;
249 /* DMA push buffer */
250 struct nouveau_gpuobj *pushbuf;
251 struct nouveau_bo *pushbuf_bo;
252 struct nouveau_vma pushbuf_vma;
253 uint64_t pushbuf_base;
255 /* Notifier memory */
256 struct nouveau_bo *notifier_bo;
257 struct nouveau_vma notifier_vma;
258 struct drm_mm notifier_heap;
261 struct nouveau_gpuobj *ramfc;
262 struct nouveau_gpuobj *cache;
265 /* Execution engine contexts */
266 void *engctx[NVOBJ_ENGINE_NR];
269 struct nouveau_vm *vm;
270 struct nouveau_gpuobj *vm_pd;
273 struct nouveau_gpuobj *ramin; /* Private instmem */
274 struct drm_mm ramin_heap; /* Private PRAMIN heap */
275 struct nouveau_ramht *ramht; /* Hash table */
277 /* GPU object info for stuff used in-kernel (mm_enabled) */
279 uint32_t vram_handle;
280 uint32_t gart_handle;
283 /* Push buffer state (only for drm's channel on !mm_enabled) */
289 /* access via pushbuf_bo */
297 uint32_t sw_subchannel[8];
299 struct nouveau_vma dispc_vma[2];
301 struct nouveau_gpuobj *vblsem;
302 uint32_t vblsem_head;
303 uint32_t vblsem_offset;
304 uint32_t vblsem_rval;
305 struct list_head vbl_wait;
306 struct list_head flip;
312 struct drm_info_list info;
316 struct nouveau_exec_engine {
317 void (*destroy)(struct drm_device *, int engine);
318 int (*init)(struct drm_device *, int engine);
319 int (*fini)(struct drm_device *, int engine, bool suspend);
320 int (*context_new)(struct nouveau_channel *, int engine);
321 void (*context_del)(struct nouveau_channel *, int engine);
322 int (*object_new)(struct nouveau_channel *, int engine,
323 u32 handle, u16 class);
324 void (*set_tile_region)(struct drm_device *dev, int i);
325 void (*tlb_flush)(struct drm_device *, int engine);
328 struct nouveau_instmem_engine {
331 int (*init)(struct drm_device *dev);
332 void (*takedown)(struct drm_device *dev);
333 int (*suspend)(struct drm_device *dev);
334 void (*resume)(struct drm_device *dev);
336 int (*get)(struct nouveau_gpuobj *, struct nouveau_channel *,
337 u32 size, u32 align);
338 void (*put)(struct nouveau_gpuobj *);
339 int (*map)(struct nouveau_gpuobj *);
340 void (*unmap)(struct nouveau_gpuobj *);
342 void (*flush)(struct drm_device *);
345 struct nouveau_mc_engine {
346 int (*init)(struct drm_device *dev);
347 void (*takedown)(struct drm_device *dev);
350 struct nouveau_timer_engine {
351 int (*init)(struct drm_device *dev);
352 void (*takedown)(struct drm_device *dev);
353 uint64_t (*read)(struct drm_device *dev);
356 struct nouveau_fb_engine {
358 struct drm_mm tag_heap;
361 int (*init)(struct drm_device *dev);
362 void (*takedown)(struct drm_device *dev);
364 void (*init_tile_region)(struct drm_device *dev, int i,
365 uint32_t addr, uint32_t size,
366 uint32_t pitch, uint32_t flags);
367 void (*set_tile_region)(struct drm_device *dev, int i);
368 void (*free_tile_region)(struct drm_device *dev, int i);
371 struct nouveau_fifo_engine {
375 struct nouveau_gpuobj *playlist[2];
378 int (*init)(struct drm_device *);
379 void (*takedown)(struct drm_device *);
381 void (*disable)(struct drm_device *);
382 void (*enable)(struct drm_device *);
383 bool (*reassign)(struct drm_device *, bool enable);
384 bool (*cache_pull)(struct drm_device *dev, bool enable);
386 int (*channel_id)(struct drm_device *);
388 int (*create_context)(struct nouveau_channel *);
389 void (*destroy_context)(struct nouveau_channel *);
390 int (*load_context)(struct nouveau_channel *);
391 int (*unload_context)(struct drm_device *);
392 void (*tlb_flush)(struct drm_device *dev);
395 struct nouveau_display_engine {
397 int (*early_init)(struct drm_device *);
398 void (*late_takedown)(struct drm_device *);
399 int (*create)(struct drm_device *);
400 void (*destroy)(struct drm_device *);
401 int (*init)(struct drm_device *);
402 void (*fini)(struct drm_device *);
404 struct drm_property *dithering_mode;
405 struct drm_property *dithering_depth;
406 struct drm_property *underscan_property;
407 struct drm_property *underscan_hborder_property;
408 struct drm_property *underscan_vborder_property;
411 struct nouveau_gpio_engine {
413 struct list_head isr;
414 int (*init)(struct drm_device *);
415 void (*fini)(struct drm_device *);
416 int (*drive)(struct drm_device *, int line, int dir, int out);
417 int (*sense)(struct drm_device *, int line);
418 void (*irq_enable)(struct drm_device *, int line, bool);
421 struct nouveau_pm_voltage_level {
422 u32 voltage; /* microvolts */
426 struct nouveau_pm_voltage {
431 struct nouveau_pm_voltage_level *level;
435 struct nouveau_pm_memtiming {
437 u32 reg_0; /* 0x10f290 on Fermi, 0x100220 for older */
446 /* To be written to 0x1002c0 */
451 struct nouveau_pm_tbl_header{
458 struct nouveau_pm_tbl_entry{
464 u8 tRAS; /* Byte 5 */
466 u8 tRFC; /* Byte 7 */
469 u8 tUNK_10, tUNK_11, tUNK_12, tUNK_13, tUNK_14;
470 u8 empty_15,empty_16,empty_17;
471 u8 tUNK_18, tUNK_19, tUNK_20, tUNK_21;
475 void nv30_mem_timing_entry(struct drm_device *dev, struct nouveau_pm_tbl_header *hdr,
476 struct nouveau_pm_tbl_entry *e, uint8_t magic_number,
477 struct nouveau_pm_memtiming *timing);
479 #define NOUVEAU_PM_MAX_LEVEL 8
480 struct nouveau_pm_level {
481 struct device_attribute dev_attr;
493 u32 unka0; /* nva3:nvc0 */
494 u32 hub01; /* nvc0- */
495 u32 hub06; /* nvc0- */
496 u32 hub07; /* nvc0- */
498 u32 volt_min; /* microvolts */
503 struct nouveau_pm_memtiming *timing;
506 struct nouveau_pm_temp_sensor_constants {
514 struct nouveau_pm_threshold_temp {
520 struct nouveau_pm_memtimings {
522 struct nouveau_pm_memtiming *timing;
526 struct nouveau_pm_fan {
532 struct nouveau_pm_engine {
533 struct nouveau_pm_voltage voltage;
534 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL];
536 struct nouveau_pm_memtimings memtimings;
537 struct nouveau_pm_temp_sensor_constants sensor_constants;
538 struct nouveau_pm_threshold_temp threshold_temp;
539 struct nouveau_pm_fan fan;
542 struct nouveau_pm_level boot;
543 struct nouveau_pm_level *cur;
545 struct device *hwmon;
546 struct notifier_block acpi_nb;
548 int (*clocks_get)(struct drm_device *, struct nouveau_pm_level *);
549 void *(*clocks_pre)(struct drm_device *, struct nouveau_pm_level *);
550 int (*clocks_set)(struct drm_device *, void *);
552 int (*voltage_get)(struct drm_device *);
553 int (*voltage_set)(struct drm_device *, int voltage);
554 int (*pwm_get)(struct drm_device *, int line, u32*, u32*);
555 int (*pwm_set)(struct drm_device *, int line, u32, u32);
556 int (*temp_get)(struct drm_device *);
559 struct nouveau_vram_engine {
560 struct nouveau_mm mm;
562 int (*init)(struct drm_device *);
563 void (*takedown)(struct drm_device *dev);
564 int (*get)(struct drm_device *, u64, u32 align, u32 size_nc,
565 u32 type, struct nouveau_mem **);
566 void (*put)(struct drm_device *, struct nouveau_mem **);
568 bool (*flags_valid)(struct drm_device *, u32 tile_flags);
571 struct nouveau_engine {
572 struct nouveau_instmem_engine instmem;
573 struct nouveau_mc_engine mc;
574 struct nouveau_timer_engine timer;
575 struct nouveau_fb_engine fb;
576 struct nouveau_fifo_engine fifo;
577 struct nouveau_display_engine display;
578 struct nouveau_gpio_engine gpio;
579 struct nouveau_pm_engine pm;
580 struct nouveau_vram_engine vram;
583 struct nouveau_pll_vals {
587 uint8_t N1, M1, N2, M2;
589 uint8_t M1, N1, M2, N2;
594 } __attribute__((packed));
601 enum nv04_fp_display_regs {
611 struct nv04_crtc_reg {
612 unsigned char MiscOutReg;
615 uint8_t Sequencer[5];
617 uint8_t Attribute[21];
618 unsigned char DAC[768];
628 uint32_t crtc_eng_ctrl;
631 uint32_t nv10_cursync;
632 struct nouveau_pll_vals pllvals;
633 uint32_t ramdac_gen_ctrl;
639 uint32_t tv_vsync_delay;
642 uint32_t tv_hsync_delay;
643 uint32_t tv_hsync_delay2;
644 uint32_t fp_horiz_regs[7];
645 uint32_t fp_vert_regs[7];
648 uint32_t dither_regs[6];
652 uint32_t fp_margin_color;
657 uint32_t ctv_regs[38];
660 struct nv04_output_reg {
665 struct nv04_mode_state {
666 struct nv04_crtc_reg crtc_reg[2];
671 enum nouveau_card_type {
682 struct drm_nouveau_private {
683 struct drm_device *dev;
686 /* the card type, takes NV_* as values */
687 enum nouveau_card_type card_type;
688 /* exact chipset, derived from NV_PMC_BOOT_0 */
695 spinlock_t ramin_lock;
699 bool ramin_available;
700 struct drm_mm ramin_heap;
701 struct nouveau_exec_engine *eng[NVOBJ_ENGINE_NR];
702 struct list_head gpuobj_list;
703 struct list_head classes;
705 struct nouveau_bo *vga_ram;
707 /* interrupt handling */
708 void (*irq_handler[32])(struct drm_device *);
711 struct list_head vbl_waiting;
714 struct drm_global_reference mem_global_ref;
715 struct ttm_bo_global_ref bo_global_ref;
716 struct ttm_bo_device bdev;
717 atomic_t validate_sequence;
723 struct nouveau_bo *bo;
728 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR];
731 struct nouveau_engine engine;
732 struct nouveau_channel *channel;
734 /* For PFIFO and PGRAPH. */
735 spinlock_t context_switch_lock;
737 /* VM/PRAMIN flush, legacy PRAMIN aperture */
740 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
741 struct nouveau_ramht *ramht;
742 struct nouveau_gpuobj *ramfc;
743 struct nouveau_gpuobj *ramro;
745 uint32_t ramin_rsvd_vram;
749 NOUVEAU_GART_NONE = 0,
750 NOUVEAU_GART_AGP, /* AGP */
751 NOUVEAU_GART_PDMA, /* paged dma object */
752 NOUVEAU_GART_HW /* on-chip gart/vm */
758 struct ttm_backend_func *func;
765 struct nouveau_gpuobj *sg_ctxdma;
768 /* nv10-nv40 tiling regions */
770 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR];
774 /* VRAM/fb configuration */
776 uint64_t vram_sys_base;
778 uint64_t fb_available_size;
779 uint64_t fb_mappable_pages;
780 uint64_t fb_aper_free;
783 /* BAR control (NV50-) */
784 struct nouveau_vm *bar1_vm;
785 struct nouveau_vm *bar3_vm;
787 /* G8x/G9x virtual address space */
788 struct nouveau_vm *chan_vm;
792 struct list_head i2c_ports;
794 struct nv04_mode_state mode_reg;
795 struct nv04_mode_state saved_reg;
796 uint32_t saved_vga_font[4][16384];
798 uint32_t dac_users[4];
800 struct backlight_device *backlight;
803 struct dentry *channel_root;
806 struct nouveau_fbdev *nfbdev;
807 struct apertures_struct *apertures;
810 static inline struct drm_nouveau_private *
811 nouveau_private(struct drm_device *dev)
813 return dev->dev_private;
816 static inline struct drm_nouveau_private *
817 nouveau_bdev(struct ttm_bo_device *bd)
819 return container_of(bd, struct drm_nouveau_private, ttm.bdev);
823 nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo)
825 struct nouveau_bo *prev;
831 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL;
833 struct ttm_buffer_object *bo = &prev->bo;
842 extern int nouveau_modeset;
843 extern int nouveau_agpmode;
844 extern int nouveau_duallink;
845 extern int nouveau_uscript_lvds;
846 extern int nouveau_uscript_tmds;
847 extern int nouveau_vram_pushbuf;
848 extern int nouveau_vram_notify;
849 extern int nouveau_fbpercrtc;
850 extern int nouveau_tv_disable;
851 extern char *nouveau_tv_norm;
852 extern int nouveau_reg_debug;
853 extern char *nouveau_vbios;
854 extern int nouveau_ignorelid;
855 extern int nouveau_nofbaccel;
856 extern int nouveau_noaccel;
857 extern int nouveau_force_post;
858 extern int nouveau_override_conntype;
859 extern char *nouveau_perflvl;
860 extern int nouveau_perflvl_wr;
861 extern int nouveau_msi;
862 extern int nouveau_ctxfw;
863 extern int nouveau_mxmdcb;
865 extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state);
866 extern int nouveau_pci_resume(struct pci_dev *pdev);
868 /* nouveau_state.c */
869 extern int nouveau_open(struct drm_device *, struct drm_file *);
870 extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
871 extern void nouveau_postclose(struct drm_device *, struct drm_file *);
872 extern int nouveau_load(struct drm_device *, unsigned long flags);
873 extern int nouveau_firstopen(struct drm_device *);
874 extern void nouveau_lastclose(struct drm_device *);
875 extern int nouveau_unload(struct drm_device *);
876 extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
878 extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
880 extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout,
881 uint32_t reg, uint32_t mask, uint32_t val);
882 extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout,
883 uint32_t reg, uint32_t mask, uint32_t val);
884 extern bool nouveau_wait_cb(struct drm_device *, u64 timeout,
885 bool (*cond)(void *), void *);
886 extern bool nouveau_wait_for_idle(struct drm_device *);
887 extern int nouveau_card_init(struct drm_device *);
890 extern int nouveau_mem_vram_init(struct drm_device *);
891 extern void nouveau_mem_vram_fini(struct drm_device *);
892 extern int nouveau_mem_gart_init(struct drm_device *);
893 extern void nouveau_mem_gart_fini(struct drm_device *);
894 extern int nouveau_mem_init_agp(struct drm_device *);
895 extern int nouveau_mem_reset_agp(struct drm_device *);
896 extern void nouveau_mem_close(struct drm_device *);
897 extern int nouveau_mem_detect(struct drm_device *);
898 extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags);
899 extern struct nouveau_tile_reg *nv10_mem_set_tiling(
900 struct drm_device *dev, uint32_t addr, uint32_t size,
901 uint32_t pitch, uint32_t flags);
902 extern void nv10_mem_put_tile_region(struct drm_device *dev,
903 struct nouveau_tile_reg *tile,
904 struct nouveau_fence *fence);
905 extern const struct ttm_mem_type_manager_func nouveau_vram_manager;
906 extern const struct ttm_mem_type_manager_func nouveau_gart_manager;
908 /* nouveau_notifier.c */
909 extern int nouveau_notifier_init_channel(struct nouveau_channel *);
910 extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
911 extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
912 int cout, uint32_t start, uint32_t end,
914 extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
915 extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
917 extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
920 /* nouveau_channel.c */
921 extern struct drm_ioctl_desc nouveau_ioctls[];
922 extern int nouveau_max_ioctl;
923 extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
924 extern int nouveau_channel_alloc(struct drm_device *dev,
925 struct nouveau_channel **chan,
926 struct drm_file *file_priv,
927 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
928 extern struct nouveau_channel *
929 nouveau_channel_get_unlocked(struct nouveau_channel *);
930 extern struct nouveau_channel *
931 nouveau_channel_get(struct drm_file *, int id);
932 extern void nouveau_channel_put_unlocked(struct nouveau_channel **);
933 extern void nouveau_channel_put(struct nouveau_channel **);
934 extern void nouveau_channel_ref(struct nouveau_channel *chan,
935 struct nouveau_channel **pchan);
936 extern void nouveau_channel_idle(struct nouveau_channel *chan);
938 /* nouveau_object.c */
939 #define NVOBJ_ENGINE_ADD(d, e, p) do { \
940 struct drm_nouveau_private *dev_priv = (d)->dev_private; \
941 dev_priv->eng[NVOBJ_ENGINE_##e] = (p); \
944 #define NVOBJ_ENGINE_DEL(d, e) do { \
945 struct drm_nouveau_private *dev_priv = (d)->dev_private; \
946 dev_priv->eng[NVOBJ_ENGINE_##e] = NULL; \
949 #define NVOBJ_CLASS(d, c, e) do { \
950 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \
955 #define NVOBJ_MTHD(d, c, m, e) do { \
956 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \
961 extern int nouveau_gpuobj_early_init(struct drm_device *);
962 extern int nouveau_gpuobj_init(struct drm_device *);
963 extern void nouveau_gpuobj_takedown(struct drm_device *);
964 extern int nouveau_gpuobj_suspend(struct drm_device *dev);
965 extern void nouveau_gpuobj_resume(struct drm_device *dev);
966 extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng);
967 extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd,
968 int (*exec)(struct nouveau_channel *,
969 u32 class, u32 mthd, u32 data));
970 extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32);
971 extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32);
972 extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
973 uint32_t vram_h, uint32_t tt_h);
974 extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
975 extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
976 uint32_t size, int align, uint32_t flags,
977 struct nouveau_gpuobj **);
978 extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *,
979 struct nouveau_gpuobj **);
980 extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst,
982 struct nouveau_gpuobj **);
983 extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
984 uint64_t offset, uint64_t size, int access,
985 int target, struct nouveau_gpuobj **);
986 extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class);
987 extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base,
988 u64 size, int target, int access, u32 type,
989 u32 comp, struct nouveau_gpuobj **pobj);
990 extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset,
991 int class, u64 base, u64 size, int target,
992 int access, u32 type, u32 comp);
993 extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
995 extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
999 extern int nouveau_irq_init(struct drm_device *);
1000 extern void nouveau_irq_fini(struct drm_device *);
1001 extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
1002 extern void nouveau_irq_register(struct drm_device *, int status_bit,
1003 void (*)(struct drm_device *));
1004 extern void nouveau_irq_unregister(struct drm_device *, int status_bit);
1005 extern void nouveau_irq_preinstall(struct drm_device *);
1006 extern int nouveau_irq_postinstall(struct drm_device *);
1007 extern void nouveau_irq_uninstall(struct drm_device *);
1009 /* nouveau_sgdma.c */
1010 extern int nouveau_sgdma_init(struct drm_device *);
1011 extern void nouveau_sgdma_takedown(struct drm_device *);
1012 extern uint32_t nouveau_sgdma_get_physical(struct drm_device *,
1014 extern struct ttm_tt *nouveau_sgdma_create_ttm(struct ttm_bo_device *bdev,
1016 uint32_t page_flags,
1017 struct page *dummy_read_page);
1019 /* nouveau_debugfs.c */
1020 #if defined(CONFIG_DRM_NOUVEAU_DEBUG)
1021 extern int nouveau_debugfs_init(struct drm_minor *);
1022 extern void nouveau_debugfs_takedown(struct drm_minor *);
1023 extern int nouveau_debugfs_channel_init(struct nouveau_channel *);
1024 extern void nouveau_debugfs_channel_fini(struct nouveau_channel *);
1027 nouveau_debugfs_init(struct drm_minor *minor)
1032 static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
1037 nouveau_debugfs_channel_init(struct nouveau_channel *chan)
1043 nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
1049 extern void nouveau_dma_pre_init(struct nouveau_channel *);
1050 extern int nouveau_dma_init(struct nouveau_channel *);
1051 extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
1053 /* nouveau_acpi.c */
1054 #define ROM_BIOS_PAGE 4096
1055 #if defined(CONFIG_ACPI)
1056 void nouveau_register_dsm_handler(void);
1057 void nouveau_unregister_dsm_handler(void);
1058 int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len);
1059 bool nouveau_acpi_rom_supported(struct pci_dev *pdev);
1060 int nouveau_acpi_edid(struct drm_device *, struct drm_connector *);
1062 static inline void nouveau_register_dsm_handler(void) {}
1063 static inline void nouveau_unregister_dsm_handler(void) {}
1064 static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; }
1065 static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; }
1066 static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; }
1069 /* nouveau_backlight.c */
1070 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
1071 extern int nouveau_backlight_init(struct drm_device *);
1072 extern void nouveau_backlight_exit(struct drm_device *);
1074 static inline int nouveau_backlight_init(struct drm_device *dev)
1079 static inline void nouveau_backlight_exit(struct drm_device *dev) { }
1082 /* nouveau_bios.c */
1083 extern int nouveau_bios_init(struct drm_device *);
1084 extern void nouveau_bios_takedown(struct drm_device *dev);
1085 extern int nouveau_run_vbios_init(struct drm_device *);
1086 extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table,
1087 struct dcb_entry *, int crtc);
1088 extern void nouveau_bios_init_exec(struct drm_device *, uint16_t table);
1089 extern struct dcb_connector_table_entry *
1090 nouveau_bios_connector_entry(struct drm_device *, int index);
1091 extern u32 get_pll_register(struct drm_device *, enum pll_types);
1092 extern int get_pll_limits(struct drm_device *, uint32_t limit_match,
1094 extern int nouveau_bios_run_display_table(struct drm_device *, u16 id, int clk,
1095 struct dcb_entry *, int crtc);
1096 extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
1097 extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
1098 extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
1099 bool *dl, bool *if_is_24bit);
1100 extern int run_tmds_table(struct drm_device *, struct dcb_entry *,
1101 int head, int pxclk);
1102 extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head,
1103 enum LVDS_script, int pxclk);
1104 bool bios_encoder_match(struct dcb_entry *, u32 hash);
1107 int nouveau_mxm_init(struct drm_device *dev);
1108 void nouveau_mxm_fini(struct drm_device *dev);
1111 int nouveau_ttm_global_init(struct drm_nouveau_private *);
1112 void nouveau_ttm_global_release(struct drm_nouveau_private *);
1113 int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
1115 /* nouveau_hdmi.c */
1116 void nouveau_hdmi_mode_set(struct drm_encoder *, struct drm_display_mode *);
1119 int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
1120 uint8_t *data, int data_nr);
1121 bool nouveau_dp_detect(struct drm_encoder *);
1122 bool nouveau_dp_link_train(struct drm_encoder *, u32 datarate);
1123 void nouveau_dp_tu_update(struct drm_device *, int, int, u32, u32);
1124 u8 *nouveau_dp_bios_data(struct drm_device *, struct dcb_entry *, u8 **);
1127 extern int nv04_fb_init(struct drm_device *);
1128 extern void nv04_fb_takedown(struct drm_device *);
1131 extern int nv10_fb_init(struct drm_device *);
1132 extern void nv10_fb_takedown(struct drm_device *);
1133 extern void nv10_fb_init_tile_region(struct drm_device *dev, int i,
1134 uint32_t addr, uint32_t size,
1135 uint32_t pitch, uint32_t flags);
1136 extern void nv10_fb_set_tile_region(struct drm_device *dev, int i);
1137 extern void nv10_fb_free_tile_region(struct drm_device *dev, int i);
1140 extern int nv30_fb_init(struct drm_device *);
1141 extern void nv30_fb_takedown(struct drm_device *);
1142 extern void nv30_fb_init_tile_region(struct drm_device *dev, int i,
1143 uint32_t addr, uint32_t size,
1144 uint32_t pitch, uint32_t flags);
1145 extern void nv30_fb_free_tile_region(struct drm_device *dev, int i);
1148 extern int nv40_fb_init(struct drm_device *);
1149 extern void nv40_fb_takedown(struct drm_device *);
1150 extern void nv40_fb_set_tile_region(struct drm_device *dev, int i);
1153 extern int nv50_fb_init(struct drm_device *);
1154 extern void nv50_fb_takedown(struct drm_device *);
1155 extern void nv50_fb_vm_trap(struct drm_device *, int display);
1158 extern int nvc0_fb_init(struct drm_device *);
1159 extern void nvc0_fb_takedown(struct drm_device *);
1162 extern int nv04_fifo_init(struct drm_device *);
1163 extern void nv04_fifo_fini(struct drm_device *);
1164 extern void nv04_fifo_disable(struct drm_device *);
1165 extern void nv04_fifo_enable(struct drm_device *);
1166 extern bool nv04_fifo_reassign(struct drm_device *, bool);
1167 extern bool nv04_fifo_cache_pull(struct drm_device *, bool);
1168 extern int nv04_fifo_channel_id(struct drm_device *);
1169 extern int nv04_fifo_create_context(struct nouveau_channel *);
1170 extern void nv04_fifo_destroy_context(struct nouveau_channel *);
1171 extern int nv04_fifo_load_context(struct nouveau_channel *);
1172 extern int nv04_fifo_unload_context(struct drm_device *);
1173 extern void nv04_fifo_isr(struct drm_device *);
1176 extern int nv10_fifo_init(struct drm_device *);
1177 extern int nv10_fifo_channel_id(struct drm_device *);
1178 extern int nv10_fifo_create_context(struct nouveau_channel *);
1179 extern int nv10_fifo_load_context(struct nouveau_channel *);
1180 extern int nv10_fifo_unload_context(struct drm_device *);
1183 extern int nv40_fifo_init(struct drm_device *);
1184 extern int nv40_fifo_create_context(struct nouveau_channel *);
1185 extern int nv40_fifo_load_context(struct nouveau_channel *);
1186 extern int nv40_fifo_unload_context(struct drm_device *);
1189 extern int nv50_fifo_init(struct drm_device *);
1190 extern void nv50_fifo_takedown(struct drm_device *);
1191 extern int nv50_fifo_channel_id(struct drm_device *);
1192 extern int nv50_fifo_create_context(struct nouveau_channel *);
1193 extern void nv50_fifo_destroy_context(struct nouveau_channel *);
1194 extern int nv50_fifo_load_context(struct nouveau_channel *);
1195 extern int nv50_fifo_unload_context(struct drm_device *);
1196 extern void nv50_fifo_tlb_flush(struct drm_device *dev);
1199 extern int nvc0_fifo_init(struct drm_device *);
1200 extern void nvc0_fifo_takedown(struct drm_device *);
1201 extern void nvc0_fifo_disable(struct drm_device *);
1202 extern void nvc0_fifo_enable(struct drm_device *);
1203 extern bool nvc0_fifo_reassign(struct drm_device *, bool);
1204 extern bool nvc0_fifo_cache_pull(struct drm_device *, bool);
1205 extern int nvc0_fifo_channel_id(struct drm_device *);
1206 extern int nvc0_fifo_create_context(struct nouveau_channel *);
1207 extern void nvc0_fifo_destroy_context(struct nouveau_channel *);
1208 extern int nvc0_fifo_load_context(struct nouveau_channel *);
1209 extern int nvc0_fifo_unload_context(struct drm_device *);
1212 extern int nv04_graph_create(struct drm_device *);
1213 extern int nv04_graph_object_new(struct nouveau_channel *, int, u32, u16);
1214 extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan,
1215 u32 class, u32 mthd, u32 data);
1216 extern struct nouveau_bitfield nv04_graph_nsource[];
1219 extern int nv10_graph_create(struct drm_device *);
1220 extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
1221 extern struct nouveau_bitfield nv10_graph_intr[];
1222 extern struct nouveau_bitfield nv10_graph_nstatus[];
1225 extern int nv20_graph_create(struct drm_device *);
1228 extern int nv40_graph_create(struct drm_device *);
1229 extern void nv40_grctx_init(struct nouveau_grctx *);
1232 extern int nv50_graph_create(struct drm_device *);
1233 extern int nv50_grctx_init(struct nouveau_grctx *);
1234 extern struct nouveau_enum nv50_data_error_names[];
1235 extern int nv50_graph_isr_chid(struct drm_device *dev, u64 inst);
1238 extern int nvc0_graph_create(struct drm_device *);
1239 extern int nvc0_graph_isr_chid(struct drm_device *dev, u64 inst);
1242 extern int nv84_crypt_create(struct drm_device *);
1245 extern int nv98_crypt_create(struct drm_device *dev);
1248 extern int nva3_copy_create(struct drm_device *dev);
1251 extern int nvc0_copy_create(struct drm_device *dev, int engine);
1254 extern int nv31_mpeg_create(struct drm_device *dev);
1257 extern int nv50_mpeg_create(struct drm_device *dev);
1261 extern int nv84_bsp_create(struct drm_device *dev);
1265 extern int nv84_vp_create(struct drm_device *dev);
1268 extern int nv98_ppp_create(struct drm_device *dev);
1270 /* nv04_instmem.c */
1271 extern int nv04_instmem_init(struct drm_device *);
1272 extern void nv04_instmem_takedown(struct drm_device *);
1273 extern int nv04_instmem_suspend(struct drm_device *);
1274 extern void nv04_instmem_resume(struct drm_device *);
1275 extern int nv04_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *,
1276 u32 size, u32 align);
1277 extern void nv04_instmem_put(struct nouveau_gpuobj *);
1278 extern int nv04_instmem_map(struct nouveau_gpuobj *);
1279 extern void nv04_instmem_unmap(struct nouveau_gpuobj *);
1280 extern void nv04_instmem_flush(struct drm_device *);
1282 /* nv50_instmem.c */
1283 extern int nv50_instmem_init(struct drm_device *);
1284 extern void nv50_instmem_takedown(struct drm_device *);
1285 extern int nv50_instmem_suspend(struct drm_device *);
1286 extern void nv50_instmem_resume(struct drm_device *);
1287 extern int nv50_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *,
1288 u32 size, u32 align);
1289 extern void nv50_instmem_put(struct nouveau_gpuobj *);
1290 extern int nv50_instmem_map(struct nouveau_gpuobj *);
1291 extern void nv50_instmem_unmap(struct nouveau_gpuobj *);
1292 extern void nv50_instmem_flush(struct drm_device *);
1293 extern void nv84_instmem_flush(struct drm_device *);
1295 /* nvc0_instmem.c */
1296 extern int nvc0_instmem_init(struct drm_device *);
1297 extern void nvc0_instmem_takedown(struct drm_device *);
1298 extern int nvc0_instmem_suspend(struct drm_device *);
1299 extern void nvc0_instmem_resume(struct drm_device *);
1302 extern int nv04_mc_init(struct drm_device *);
1303 extern void nv04_mc_takedown(struct drm_device *);
1306 extern int nv40_mc_init(struct drm_device *);
1307 extern void nv40_mc_takedown(struct drm_device *);
1310 extern int nv50_mc_init(struct drm_device *);
1311 extern void nv50_mc_takedown(struct drm_device *);
1314 extern int nv04_timer_init(struct drm_device *);
1315 extern uint64_t nv04_timer_read(struct drm_device *);
1316 extern void nv04_timer_takedown(struct drm_device *);
1318 extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1322 extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *);
1323 extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
1324 extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1325 extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
1326 extern bool nv04_dac_in_use(struct drm_encoder *encoder);
1329 extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *);
1330 extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent);
1331 extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
1333 extern void nv04_dfp_disable(struct drm_device *dev, int head);
1334 extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
1337 extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
1338 extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *);
1341 extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *);
1343 /* nv04_display.c */
1344 extern int nv04_display_early_init(struct drm_device *);
1345 extern void nv04_display_late_takedown(struct drm_device *);
1346 extern int nv04_display_create(struct drm_device *);
1347 extern void nv04_display_destroy(struct drm_device *);
1348 extern int nv04_display_init(struct drm_device *);
1349 extern void nv04_display_fini(struct drm_device *);
1351 /* nvd0_display.c */
1352 extern int nvd0_display_create(struct drm_device *);
1353 extern void nvd0_display_destroy(struct drm_device *);
1354 extern int nvd0_display_init(struct drm_device *);
1355 extern void nvd0_display_fini(struct drm_device *);
1356 struct nouveau_bo *nvd0_display_crtc_sema(struct drm_device *, int crtc);
1357 void nvd0_display_flip_stop(struct drm_crtc *);
1358 int nvd0_display_flip_next(struct drm_crtc *, struct drm_framebuffer *,
1359 struct nouveau_channel *, u32 swap_interval);
1362 extern int nv04_crtc_create(struct drm_device *, int index);
1365 extern struct ttm_bo_driver nouveau_bo_driver;
1366 extern int nouveau_bo_new(struct drm_device *, int size, int align,
1367 uint32_t flags, uint32_t tile_mode,
1368 uint32_t tile_flags, struct nouveau_bo **);
1369 extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
1370 extern int nouveau_bo_unpin(struct nouveau_bo *);
1371 extern int nouveau_bo_map(struct nouveau_bo *);
1372 extern void nouveau_bo_unmap(struct nouveau_bo *);
1373 extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type,
1375 extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1376 extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1377 extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
1378 extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
1379 extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *);
1380 extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible,
1381 bool no_wait_reserve, bool no_wait_gpu);
1383 extern struct nouveau_vma *
1384 nouveau_bo_vma_find(struct nouveau_bo *, struct nouveau_vm *);
1385 extern int nouveau_bo_vma_add(struct nouveau_bo *, struct nouveau_vm *,
1386 struct nouveau_vma *);
1387 extern void nouveau_bo_vma_del(struct nouveau_bo *, struct nouveau_vma *);
1389 /* nouveau_fence.c */
1390 struct nouveau_fence;
1391 extern int nouveau_fence_init(struct drm_device *);
1392 extern void nouveau_fence_fini(struct drm_device *);
1393 extern int nouveau_fence_channel_init(struct nouveau_channel *);
1394 extern void nouveau_fence_channel_fini(struct nouveau_channel *);
1395 extern void nouveau_fence_update(struct nouveau_channel *);
1396 extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **,
1398 extern int nouveau_fence_emit(struct nouveau_fence *);
1399 extern void nouveau_fence_work(struct nouveau_fence *fence,
1400 void (*work)(void *priv, bool signalled),
1402 struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *);
1404 extern bool __nouveau_fence_signalled(void *obj, void *arg);
1405 extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr);
1406 extern int __nouveau_fence_flush(void *obj, void *arg);
1407 extern void __nouveau_fence_unref(void **obj);
1408 extern void *__nouveau_fence_ref(void *obj);
1410 static inline bool nouveau_fence_signalled(struct nouveau_fence *obj)
1412 return __nouveau_fence_signalled(obj, NULL);
1415 nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr)
1417 return __nouveau_fence_wait(obj, NULL, lazy, intr);
1419 extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *);
1420 static inline int nouveau_fence_flush(struct nouveau_fence *obj)
1422 return __nouveau_fence_flush(obj, NULL);
1424 static inline void nouveau_fence_unref(struct nouveau_fence **obj)
1426 __nouveau_fence_unref((void **)obj);
1428 static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj)
1430 return __nouveau_fence_ref(obj);
1434 extern int nouveau_gem_new(struct drm_device *, int size, int align,
1435 uint32_t domain, uint32_t tile_mode,
1436 uint32_t tile_flags, struct nouveau_bo **);
1437 extern int nouveau_gem_object_new(struct drm_gem_object *);
1438 extern void nouveau_gem_object_del(struct drm_gem_object *);
1439 extern int nouveau_gem_object_open(struct drm_gem_object *, struct drm_file *);
1440 extern void nouveau_gem_object_close(struct drm_gem_object *,
1442 extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
1444 extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
1446 extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
1448 extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
1450 extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
1453 /* nouveau_display.c */
1454 int nouveau_display_create(struct drm_device *dev);
1455 void nouveau_display_destroy(struct drm_device *dev);
1456 int nouveau_display_init(struct drm_device *dev);
1457 void nouveau_display_fini(struct drm_device *dev);
1458 int nouveau_vblank_enable(struct drm_device *dev, int crtc);
1459 void nouveau_vblank_disable(struct drm_device *dev, int crtc);
1460 int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1461 struct drm_pending_vblank_event *event);
1462 int nouveau_finish_page_flip(struct nouveau_channel *,
1463 struct nouveau_page_flip_state *);
1464 int nouveau_display_dumb_create(struct drm_file *, struct drm_device *,
1465 struct drm_mode_create_dumb *args);
1466 int nouveau_display_dumb_map_offset(struct drm_file *, struct drm_device *,
1467 uint32_t handle, uint64_t *offset);
1468 int nouveau_display_dumb_destroy(struct drm_file *, struct drm_device *,
1472 int nv10_gpio_init(struct drm_device *dev);
1473 void nv10_gpio_fini(struct drm_device *dev);
1474 int nv10_gpio_drive(struct drm_device *dev, int line, int dir, int out);
1475 int nv10_gpio_sense(struct drm_device *dev, int line);
1476 void nv10_gpio_irq_enable(struct drm_device *, int line, bool on);
1479 int nv50_gpio_init(struct drm_device *dev);
1480 void nv50_gpio_fini(struct drm_device *dev);
1481 int nv50_gpio_drive(struct drm_device *dev, int line, int dir, int out);
1482 int nv50_gpio_sense(struct drm_device *dev, int line);
1483 void nv50_gpio_irq_enable(struct drm_device *, int line, bool on);
1484 int nvd0_gpio_drive(struct drm_device *dev, int line, int dir, int out);
1485 int nvd0_gpio_sense(struct drm_device *dev, int line);
1488 int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk,
1489 int *N1, int *M1, int *N2, int *M2, int *P);
1490 int nva3_calc_pll(struct drm_device *, struct pll_lims *,
1491 int clk, int *N, int *fN, int *M, int *P);
1493 #ifndef ioread32_native
1495 #define ioread16_native ioread16be
1496 #define iowrite16_native iowrite16be
1497 #define ioread32_native ioread32be
1498 #define iowrite32_native iowrite32be
1499 #else /* def __BIG_ENDIAN */
1500 #define ioread16_native ioread16
1501 #define iowrite16_native iowrite16
1502 #define ioread32_native ioread32
1503 #define iowrite32_native iowrite32
1504 #endif /* def __BIG_ENDIAN else */
1505 #endif /* !ioread32_native */
1507 /* channel control reg access */
1508 static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg)
1510 return ioread32_native(chan->user + reg);
1513 static inline void nvchan_wr32(struct nouveau_channel *chan,
1514 unsigned reg, u32 val)
1516 iowrite32_native(val, chan->user + reg);
1519 /* register access */
1520 static inline u32 nv_rd32(struct drm_device *dev, unsigned reg)
1522 struct drm_nouveau_private *dev_priv = dev->dev_private;
1523 return ioread32_native(dev_priv->mmio + reg);
1526 static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val)
1528 struct drm_nouveau_private *dev_priv = dev->dev_private;
1529 iowrite32_native(val, dev_priv->mmio + reg);
1532 static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val)
1534 u32 tmp = nv_rd32(dev, reg);
1535 nv_wr32(dev, reg, (tmp & ~mask) | val);
1539 static inline u8 nv_rd08(struct drm_device *dev, unsigned reg)
1541 struct drm_nouveau_private *dev_priv = dev->dev_private;
1542 return ioread8(dev_priv->mmio + reg);
1545 static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val)
1547 struct drm_nouveau_private *dev_priv = dev->dev_private;
1548 iowrite8(val, dev_priv->mmio + reg);
1551 #define nv_wait(dev, reg, mask, val) \
1552 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val))
1553 #define nv_wait_ne(dev, reg, mask, val) \
1554 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val))
1555 #define nv_wait_cb(dev, func, data) \
1556 nouveau_wait_cb(dev, 2000000000ULL, (func), (data))
1559 static inline u32 nv_ri32(struct drm_device *dev, unsigned offset)
1561 struct drm_nouveau_private *dev_priv = dev->dev_private;
1562 return ioread32_native(dev_priv->ramin + offset);
1565 static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val)
1567 struct drm_nouveau_private *dev_priv = dev->dev_private;
1568 iowrite32_native(val, dev_priv->ramin + offset);
1572 extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset);
1573 extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val);
1577 * Argument d is (struct drm_device *).
1579 #define NV_PRINTK(level, d, fmt, arg...) \
1580 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
1581 pci_name(d->pdev), ##arg)
1582 #ifndef NV_DEBUG_NOTRACE
1583 #define NV_DEBUG(d, fmt, arg...) do { \
1584 if (drm_debug & DRM_UT_DRIVER) { \
1585 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1589 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1590 if (drm_debug & DRM_UT_KMS) { \
1591 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1596 #define NV_DEBUG(d, fmt, arg...) do { \
1597 if (drm_debug & DRM_UT_DRIVER) \
1598 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1600 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1601 if (drm_debug & DRM_UT_KMS) \
1602 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1605 #define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
1606 #define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1607 #define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
1608 #define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1609 #define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
1610 #define NV_WARNONCE(d, fmt, arg...) do { \
1611 static int _warned = 0; \
1613 NV_WARN(d, fmt, ##arg); \
1618 /* nouveau_reg_debug bitmask */
1620 NOUVEAU_REG_DEBUG_MC = 0x1,
1621 NOUVEAU_REG_DEBUG_VIDEO = 0x2,
1622 NOUVEAU_REG_DEBUG_FB = 0x4,
1623 NOUVEAU_REG_DEBUG_EXTDEV = 0x8,
1624 NOUVEAU_REG_DEBUG_CRTC = 0x10,
1625 NOUVEAU_REG_DEBUG_RAMDAC = 0x20,
1626 NOUVEAU_REG_DEBUG_VGACRTC = 0x40,
1627 NOUVEAU_REG_DEBUG_RMVIO = 0x80,
1628 NOUVEAU_REG_DEBUG_VGAATTR = 0x100,
1629 NOUVEAU_REG_DEBUG_EVO = 0x200,
1630 NOUVEAU_REG_DEBUG_AUXCH = 0x400
1633 #define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1634 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1635 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1639 nv_two_heads(struct drm_device *dev)
1641 struct drm_nouveau_private *dev_priv = dev->dev_private;
1642 const int impl = dev->pci_device & 0x0ff0;
1644 if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
1645 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
1652 nv_gf4_disp_arch(struct drm_device *dev)
1654 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
1658 nv_two_reg_pll(struct drm_device *dev)
1660 struct drm_nouveau_private *dev_priv = dev->dev_private;
1661 const int impl = dev->pci_device & 0x0ff0;
1663 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
1669 nv_match_device(struct drm_device *dev, unsigned device,
1670 unsigned sub_vendor, unsigned sub_device)
1672 return dev->pdev->device == device &&
1673 dev->pdev->subsystem_vendor == sub_vendor &&
1674 dev->pdev->subsystem_device == sub_device;
1677 static inline void *
1678 nv_engine(struct drm_device *dev, int engine)
1680 struct drm_nouveau_private *dev_priv = dev->dev_private;
1681 return (void *)dev_priv->eng[engine];
1684 /* returns 1 if device is one of the nv4x using the 0x4497 object class,
1685 * helpful to determine a number of other hardware features
1688 nv44_graph_class(struct drm_device *dev)
1690 struct drm_nouveau_private *dev_priv = dev->dev_private;
1692 if ((dev_priv->chipset & 0xf0) == 0x60)
1695 return !(0x0baf & (1 << (dev_priv->chipset & 0x0f)));
1698 /* memory type/access flags, do not match hardware values */
1699 #define NV_MEM_ACCESS_RO 1
1700 #define NV_MEM_ACCESS_WO 2
1701 #define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO)
1702 #define NV_MEM_ACCESS_SYS 4
1703 #define NV_MEM_ACCESS_VM 8
1705 #define NV_MEM_TARGET_VRAM 0
1706 #define NV_MEM_TARGET_PCI 1
1707 #define NV_MEM_TARGET_PCI_NOSNOOP 2
1708 #define NV_MEM_TARGET_VM 3
1709 #define NV_MEM_TARGET_GART 4
1711 #define NV_MEM_TYPE_VM 0x7f
1712 #define NV_MEM_COMP_VM 0x03
1714 /* NV_SW object class */
1715 #define NV_SW 0x0000506e
1716 #define NV_SW_DMA_SEMAPHORE 0x00000060
1717 #define NV_SW_SEMAPHORE_OFFSET 0x00000064
1718 #define NV_SW_SEMAPHORE_ACQUIRE 0x00000068
1719 #define NV_SW_SEMAPHORE_RELEASE 0x0000006c
1720 #define NV_SW_YIELD 0x00000080
1721 #define NV_SW_DMA_VBLSEM 0x0000018c
1722 #define NV_SW_VBLSEM_OFFSET 0x00000400
1723 #define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
1724 #define NV_SW_VBLSEM_RELEASE 0x00000408
1725 #define NV_SW_PAGE_FLIP 0x00000500
1727 #endif /* __NOUVEAU_DRV_H__ */